aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
AgeCommit message (Collapse)AuthorFilesLines
2011-01-26re PR target/46997 (new ia64 vector instructions are broken on HP-UX ↵Steve Ellcey1-22/+53
(big-endian)) 2011-01-26 Steve Ellcey <sje@cup.hp.com> PR target/46997 * config/ia64/vect.md (mulv2si3): Enable and fix for TARGET_BIG_ENDIAN. (*mux2): Ditto. (vec_extract_evenodd_help): Ditto. (vec_extract_evenv4hi): Ditto. (vec_extract_oddv4hi): Ditto. (vec_interleave_lowv2si): Ditto. (vec_interleave_highv2si): Ditto. (vec_extract_evenv2si): Ditto. (vec_extract_oddv2si: Ditto. (vec_pack_trunc_v2si): Ditto. From-SVN: r169296
2011-01-26re PR tree-optimization/47237 (builtin_apply_args broken WRT local ABI changes.)Jan Hubicka1-3/+3
PR target/47237 * cgraph.h (cgraph_local_info): New field can_change_signature. * ipa-cp.c (ipcp_update_callgraph): Only compute args_to_skip if callee signature can change. (ipcp_estimate_growth): Call sequence simplify only if calle signature can change. (ipcp_insert_stage): Only compute args_to_skip if signature can change. (cgraph_function_versioning): We can not change signature of functions that don't allow that. * lto-cgraph.c (lto_output_node): Stream local.can_change_signature. (lto_input_node): Likewise. * ipa-inline.c (compute_inline_parameters): Compute local.can_change_signature. * ipa-split.c (visit_bb): Never split away APPLY_ARGS. * tree-sra.c (ipa_sra_preliminary_function_checks): Give up on functions that can not change signature. * i386.c (ix86_function_regparm, ix86_function_sseregparm, init_cumulative_args): Do not use local calling conventions for functions that can not change signature. From-SVN: r169290
2011-01-26re PR target/40125 (libgcc_s DLL installed in wrong directory in cross ↵Dave Korn3-2/+23
toolchain) gcc/ChangeLog: PR target/40125 * config.gcc (i[34567]86-*-pe | i[34567]86-*-cygwin*): Select suitable t-dlldir{,-x} fragment for build and add it to tmake_file. (i[34567]86-*-mingw* | x86_64-*-mingw*): Likewise. * Makefile.in (libgcc.mvars): Also export SHLIB_DLLDIR to libgcc. * config/i386/t-dlldir: New file. (SHLIB_DLLDIR): Define. * config/i386/t-dlldir-x: New file. (SHLIB_DLLDIR): Define. * config/i386/t-cygming: Error out if SHLIB_DLLDIR is not set. (SHLIB_INSTALL): Use it. libgcc/ChangeLog: PR target/40125 * configure.ac: Call ACX_NONCANONICAL_TARGET. (toolexecdir): Calculate and AC_SUBST. (toolexeclibdir): Likewise. * Makefile.in (target_noncanonical): Import. (toolexecdir): Likewise. (toolexeclibdir): Likewise. * configure: Regenerate. From-SVN: r169274
2011-01-26re PR target/47246 (Invalid immediate offset for Thumb VFP store regression)Chung-Lin Tang1-1/+5
2011-01-26 Chung-Lin Tang <cltang@codesourcery.com> PR target/47246 * config/arm/arm.c (thumb2_legitimate_index_p): Change the lower bound of the allowed Thumb-2 coprocessor load/store index range to -256. Add explaining comment. From-SVN: r169271
2011-01-25m32r.c: Define TARGET_EXCEPT_UNWIND_INFO to sjlj_except_unwind_info.Joel Sherrill1-1/+4
2011-01-25 Joel Sherrill <joel.sherrill@oarcorp.com> * config/m32r/m32r.c: Define TARGET_EXCEPT_UNWIND_INFO to sjlj_except_unwind_info. From-SVN: r169242
2011-01-25re PR target/45701 (Fail to prefer using r3 for padding a push/pop multiple ↵Jakub Jelinek1-2/+27
to 8-byte alignment) PR target/45701 * config/arm/arm.c (any_sibcall_uses_r3): New function. (arm_get_frame_offsets): Use it. 2011-01-25 Yao Qi <yao@codesourcery.com> PR target/45701 * gcc.target/arm/pr45701-1.c: New test. * gcc.target/arm/pr45701-2.c: New test. * gcc.target/arm/pr45701-3.c: New test. From-SVN: r169240
2011-01-25rx.h (LIBCALL_VALUE): Do not promote complex types.Nick Clifton3-25/+27
* config/rx/rx.h (LIBCALL_VALUE): Do not promote complex types. * config/rx/rx.c (rx_function_value): Likewise. (rx_promote_function_mode): Likewise. (gen_safe_add): Place an outsized immediate value inside an UNSPEC in order to make it legitimate. * config/rx/rx.md (adddi3_internal): If the second operand is a MEM make sure that the first operand is the same as the result register. (addsi3_unspec): Delete. (subdi3): Do not accept immediate operands. (subdi3_internal): Likewise. * gcc.target/rx/builtins.c: Allow -fipa-cp-clone. (saturate_add): Delete. (exchange): Delete. (main): Do not run saturate_add. (set_interrupts): Delete. From-SVN: r169232
2011-01-24Visit basic blocks using the work-list based algorithm.H.J. Lu2-22/+127
2011-01-24 H.J. Lu <hongjiu.lu@intel.com> PR target/46519 * config/i386/i386.c: Include sbitmap.h and fibheap.h. (block_info): Add scanned and prev. (move_or_delete_vzeroupper_2): Return if the basic block has been scanned and the upper 128bit state is unchanged from the last scan. (move_or_delete_vzeroupper_1): Return true if the exit state is changed. (move_or_delete_vzeroupper): Visit basic blocks using the work-list based algorithm based on vt_find_locations in var-tracking.c. * config/i386/t-i386: Also depend on sbitmap.h and $(FIBHEAP_H). From-SVN: r169173
2011-01-24v850.opt (mv850es): New option - alias for -mv850e1.Nick Clifton2-5/+15
* config/v850/v850.opt (mv850es): New option - alias for -mv850e1. * config/v850/v850.h (ASM_SPEC): If -mv850es is specified pass -mv850e1 to the assembler. If -mv850e1 or -mv850es is specified then define __v850e1__. * doc/invoke.texi: Document -mv850es. From-SVN: r169170
2011-01-24rx: Uncomplicate fp comparisons.Richard Henderson4-221/+15
It turns out that the middle-end will happily take care of doing the swapping and splitting of compound fp comparisons. No need for us to replicate that here. From-SVN: r169169
2011-01-24Fix PR 47408 and 47385Michael Meissner1-2/+2
From-SVN: r169167
2011-01-23s390.h (REGISTER_MOVE_COST, [...]): Remove.Anatoly Sokolov2-12/+29
* config/s390/s390.h (REGISTER_MOVE_COST, MEMORY_MOVE_COST): Remove. * config/s390/s390.c (s390_register_move_cost, s390_memory_move_cost): New. (TARGET_REGISTER_MOVE_COST, TARGET_MEMORY_MOVE_COST): Define. From-SVN: r169135
2011-01-22rx: Enable the compare-elim pass.Richard Henderson1-0/+3
From-SVN: r169133
2011-01-22mn10300: Enable the compare-elim pass.Richard Henderson1-0/+3
From-SVN: r169132
2011-01-22rx.md (cstoresf4): Pass comparison operator to rx_split_fp_compare.Nick Clifton1-1/+1
* config/rx/rx.md (cstoresf4): Pass comparison operator to rx_split_fp_compare. From-SVN: r169129
2011-01-22rx.md (UNSPEC_CONST): New.Nick Clifton2-54/+119
* config/rx/rx.md (UNSPEC_CONST): New. (deallocate_and_return): Wrap the amount popped off the stack in an UNSPEC_CONST in order to stop it being rejected by -mmax-constant-size. (pop_and_return): Add a "(return)" rtx. (call): Drop the immediate operand. (call_internal): Likewise. (call_value): Likewise. (call_value_internal): Likewise. (sibcall_internal): Likewise. (sibcall_value_internal): Likewise. (sibcall): Likewise. Generate an explicit call using sibcall_internal. (sibcall_value): Likewise. (mov<>): FAIL if a constant operand is not legitimate. (addsi3_unpsec): New pattern. * config/rx/rx.c (rx_print_operand_address): Handle UNPSEC CONSTs. (ok_for_max_constant): New function. (gen_safe_add): New function. (rx_expand_prologue): Use gen_safe_add. (rx_expand_epilogue): Likewise. (rx_is_legitimate_constant): Use ok_for_max_constant. Handle UNSPEC CONSTs. From-SVN: r169128
2011-01-21re PR bootstrap/47215 (Failed to bootstrap)Kai Tietz1-3/+4
2011-01-21 Kai Tietz <kai.tietz@onevision.com> PR bootstrap/47215 * decl.c (java_init_decl_processing): Remove va_list_type_node related type initializations. 2011-01-21 Kai Tietz <kai.tietz@onevision.com> PR bootstrap/47215 * config/i386/i386.c (ix86_local_alignment): Handle case for va_list_type_node is nil. (ix86_canonical_va_list_type): Likewise. From-SVN: r169080
2011-01-21Fix typo in comment.Mike Stump1-1/+1
From-SVN: r169078
2011-01-21rs6000-c.c (rs6000_cpu_cpp_builtins): Add builtin_define __CMODEL_MEDIUM__ ↵Alan Modra1-1/+15
and __CMODEL_LARGE__. * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Add builtin_define __CMODEL_MEDIUM__ and __CMODEL_LARGE__. From-SVN: r169077
2011-01-20Rename f_load to f_fpa_loads patchRamana Radhakrishnan5-23/+23
2011-01-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/arm.md (define_attr type): Rename f_load and f_store to f_fpa_load and f_fpa_store. Update. (write_conflict): Deal with rename fallout. (*push_fp_multi): Likewise. * config/arm/fpa.md (f_load): Use f_fpa_load. (f_store): Use f_fpa_store. (*movsf_fpa): Likewise. (*movdf_fpa): Likewise. (*movxf_fpa): Likewise. (*thumb2_movsf_fpa): Likewise. (*thumb2_movdf_fpa): Likewise. (*thumb2_movxf_fpa): Likewise. * config/arm/vfp.md (*thumb2_movdf_vfp): Fix attribute to f_loadd and f_stored. (*thumb2_movdi_vfp): Likewise. (*thumb2_movsf_vfp): Fix attribute to f_loads. (*thumb2_movsi_vfp): Likewise. * config/arm/cortex-m4-fpu.md (cortex_m4_f_load): Use f_loads instead of f_load. * config/arm/cortex-a5.md (cortex_a5_f_loads): Remove f_load. From-SVN: r169071
2011-01-20xtensa.h (GO_IF_MODE_DEPENDENT_ADDRESS): Remove.Anatoly Sokolov3-23/+28
* config/xtensa/xtensa.h (GO_IF_MODE_DEPENDENT_ADDRESS): Remove. * config/xtensa/xtensa-protos.h (constantpool_address_p): Remove. * config/xtensa/xtensa.c (TARGET_MODE_DEPENDENT_ADDRESS_P): Define. (xtensa_mode_dependent_address_p): New function. (constantpool_address_p): Make static. Change return type to bool. Change argument type to const_rtx. Use CONST_INT_P predicate. From-SVN: r169060
2011-01-19* config/spu/spu-elf.h (ASM_SPEC): Remove %{w:-W}.Joseph Myers1-3/+2
From-SVN: r169028
2011-01-19sysv4.h (LINK_PATH_SPEC): Remove.Joseph Myers1-21/+2
* config/rs6000/sysv4.h (LINK_PATH_SPEC): Remove. (LINK_SHLIB_SPEC): Don't use %(link_path). (SUBTARGET_EXTRA_SPECS): Remove link_path. From-SVN: r169026
2011-01-19sysv4.h (SHARED_LIB_SUPPORT): Remove conditional.Joseph Myers1-17/+2
* config/rs6000/sysv4.h (SHARED_LIB_SUPPORT): Remove conditional. (NO_SHARED_LIB_SUPPORT): Remove. (LINK_SHLIB_SPEC): Remove one conditional definition. From-SVN: r169025
2011-01-19linux64.h (LINK_SPEC): Remove %{non_shared} %{call_shared}.Joseph Myers5-8/+5
* config/mips/linux64.h (LINK_SPEC): Remove %{non_shared} %{call_shared}. * config/mips/mips.h (LINK_SPEC): Remove %{non_shared}. * config/mips/netbsd.h (LINK_SPEC): Remove %{call_shared}. * config/mips/openbsd.h (LINK_SPEC): Remove %{non_shared} %{call_shared} and conditionals on these options not being passed. * config/mips/sde.h (LINK_SPEC): Remove %{non_shared} %{call_shared}. From-SVN: r169024
2011-01-19mn10300: Use reg_or_am33_const_operand in mulsi3.Richard Henderson1-8/+8
From-SVN: r169017
2011-01-19* config/spu/spu.h (MOVE_RATIO): Return 4 in the !speed case.Ulrich Weigand1-1/+1
From-SVN: r169015
2011-01-19mn10300: Implement adddi3, subdi3.Richard Henderson2-0/+326
Via expander, pre- and post-reload patterns. The pre-reload pattern is defined to allow lower_subregs totally split the DImode values. From-SVN: r169014
2011-01-19mn10300: Emit retf instructionRichard Henderson3-49/+61
Now that we properly track the life of MDR, we can emit the RETF instruction if MDR has not been modified. This insn is 3-4 cycles faster since the return address is already loaded. From-SVN: r169013
2011-01-19mn10300: tidy pic address loadingRichard Henderson4-218/+99
There's little reason to greatly complicate things by splitting the pic_load patterns and using complex rtl to make it work out. Instead, use the %= marker to generate unique numbers and emit the entire load_pic sequence at once. At the same time, collect all references to outgoing_args_size into mn10300_frame_size, and all computations of register save area size into mn10300_initial_offset. From-SVN: r169012
2011-01-19mn10300: Cleanup all arithmetic.Richard Henderson6-950/+685
For addition and logicals, define an operation-plus-flags update pattern in preparation for compare elimination. In addition, clean up the way we compare and validate CC_MODEs. Define NEG in terms of NOT; this is smaller and allows a non-clobbering destination alternative. From-SVN: r169010
2011-01-19mn10300: Explicitly represent MDR in multiply and divide.Richard Henderson1-116/+154
Note that the mulsidi3_internal pattern is structured so as to let the lower-subregs pass fully split the result. From-SVN: r169008
2011-01-19mn10300: Expose the MDR register to register allocation.Richard Henderson4-19/+55
Note that nothing uses the "z" constraint yet except the one move pattern; this merely defines the register class properly. From-SVN: r169007
2011-01-19mn10300: Cleanup legitimate addressesRichard Henderson3-97/+147
Allow REG+REG and POST_MODIFY addressing for AM33. Fix AM33 base and index register classes. Remove a bunch of register class combinations that aren't really useful after this cleanup. From-SVN: r169006
2011-01-19mn10300: Cleanup secondary reloadsRichard Henderson4-82/+102
Handles output reloads for QI/HImode properly; previously we were only handing input reloads properly. Handles reloads involving the stack pointer better; note that the AM33 allows copying SP to DATA_REGS as well as ADDRESS and EXTENDED. From-SVN: r169005
2011-01-19mn10300: Re-write move patterns.Richard Henderson1-762/+173
Use the "D" and "A" constraints, and the enabled attribute to unify all ofthe integer move patterns. Delete the fake double word move patterns; let the middle-end generate subregs as required. Unfortunately, this somehow exposes a register pressure problem with the udivmod pattern. This is properly fixed with subsequent patches that expose the MDR register. In the meantime it is highly desirable to to preserve bisect-ability of the patch series, so disable this pattern for AM30. From-SVN: r169004
2011-01-18re PR target/46997 (new ia64 vector instructions are broken on HP-UX ↵Steve Ellcey2-30/+100
(big-endian)) PR target/46997 * ia64.c (ia64_expand_unpack): Fix code for TARGET_BIG_ENDIAN. (a64_expand_widen_sum): Ditto. * vect.md (mulv2si3): Disable for TARGET_BIG_ENDIAN. (vec_extract_evenodd_help): Ditto. (vec_extract_evenv4hi): Ditto. (vec_extract_oddv4hi): Ditto. (vec_extract_evenv2si): Ditto. (vec_extract_oddv2si): Ditto. (vec_extract_evenv2sf): Ditto. (vec_extract_oddv2sf): Ditto. (vec_pack_trunc_v4hi: Ditto. (vec_pack_trunc_v2si): Ditto. (vec_interleave_lowv8qi): Fix for TARGET_BIG_ENDIAN. (vec_interleave_highv8qi): Ditto. (mix1_r): Ditto. (vec_extract_oddv8qi): Ditto. (vec_interleave_lowv4hi): Ditto. (vec_interleave_highv4hi): Ditto. (vec_interleave_lowv2si): Ditto. (vec_interleave_highv2si): Ditto. From-SVN: r168970
2011-01-18extend.texi: Mention __float128 support on hppa HP-UX.John David Anglin4-5/+142
* doc/extend.texi: Mention __float128 support on hppa HP-UX. * config/pa/pa-hpux.h (HPUX_LONG_DOUBLE_LIBRARY): Define to 1. * config/pa/pa.c (pa_expand_builtin): New. Include "langhooks.h". (pa_c_mode_for_suffix): New. (TARGET_EXPAND_BUILTIN): Define. (TARGET_C_MODE_FOR_SUFFIX): Define. (pa_builtins): Define. (pa_init_builtins): Register __float128 type and init new support builtins. * config/pa/pa.h (HPUX_LONG_DOUBLE_LIBRARY): Define if not defined. * config/pa/quadlib.c (_U_Qfcopysign): New. From-SVN: r168969
2011-01-18re PR tree-optimization/47179 (SPU: errno misoptimization around malloc call)Ulrich Weigand1-0/+28
PR tree-optimization/47179 * config/spu/spu.c (spu_ref_may_alias_errno): New function. (TARGET_REF_MAY_ALIAS_ERRNO): Define. From-SVN: r168961
2011-01-18cortex-a9.md (cortex-a9-neon.md): Actually include.Ramana Radhakrishnan1-4/+8
2011-01-18 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/cortex-a9.md (cortex-a9-neon.md): Actually include. (cortex_a9_dp): Handle neon types correctly. From-SVN: r168950
2011-01-17rx: Split adddi3 and subdi3 after reload.Richard Henderson2-51/+214
The formulation of the pre-reload pattern allows the lower_subreg pass to properly split the patterns. This also required re-writing rx_source_operand and related predicates to accept subregs. From-SVN: r168929
2011-01-17rx: Replace sat builtin with ssaddsi3 pattern.Richard Henderson2-14/+31
A standalone __builtin_rx_sat isn't implementable due to needing to keep the flags live before reload. Instead provide a saturating add pattern, which hopefully will be pattern-matched by high-level optimizations. From-SVN: r168928
2011-01-17rx: Rewrite the bit manipulation patterns.Richard Henderson4-88/+166
The patterns represented with ashift 1 canonically need to have the ashift as the first operand of the logical operation. Leave insv represented as a zero_extract store. Implement a variable store to a 1 bit field as tst+bmne. Implement a variable store of a condition into a 1 bit field with bmcc. From-SVN: r168927
2011-01-17rx: Fix incorrect usage of + in output operands.Richard Henderson1-5/+5
From-SVN: r168926
2011-01-17rx: Cleanup non-VOIDmode SETs.Richard Henderson2-194/+76
SET should always have VOIDmode. A number of places used SImode or QImode for the mode of the SET rtx itself. From-SVN: r168925
2011-01-17rx: Cleanup flags generation.Richard Henderson3-69/+266
All arithmetic should only clobber the flags by default; setting the flags to a useful value should be done by a separate pattern. From-SVN: r168924
2011-01-17rx: Implement cstoresf4.Richard Henderson1-0/+92
From-SVN: r168923
2011-01-17rx: Remove %B workaround.Richard Henderson1-2/+0
This was delayed until all compare+operate patterns were converted. From-SVN: r168922
2011-01-17rx: Split movsicc post-reload.Richard Henderson1-38/+69
This will allow elimination of the compare. From-SVN: r168921
2011-01-17rx: Split cstoresi4 post-reload.Richard Henderson3-16/+29
This will allow elimination of the compare. From-SVN: r168920
generated by cgit v1.1 at 2025-02-12 21:14:14 +0000