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2017-01-01Update copyright years.Jakub Jelinek1345-1359/+1359
From-SVN: r243994
2016-12-30i386.md (*testqi_ext_3): Merge insn pattern and corresponding splitter to ↵Uros Bizjak1-34/+22
define_insn_and_split. * config/i386/i386.md (*testqi_ext_3): Merge insn pattern and corresponding splitter to define_insn_and_split. Use wi::shifted_mask helper function to calculate mask. From-SVN: r243977
2016-12-30predicates.md (ext_register_operand): Do not reject registers without upper ↵Uros Bizjak2-19/+21
parts here. * config/i386/predicates.md (ext_register_operand): Do not reject registers without upper parts here. * config/i386/i386.md (extv<mode>): Copy registers without upper parts in operand 1 to a pseudo. (extzv<mode>): Ditto. (insv<mode>): Ditto. From-SVN: r243976
2016-12-30* config/i386/i386.md (divmodqi4): Use lowpart_subreg.Uros Bizjak1-3/+2
From-SVN: r243969
2016-12-29re PR target/78904 (zero-extracts are not effective)Uros Bizjak1-28/+2
PR target/78904 * config/i386/i386.md (*extvqi): Remove insn pattern. (divmodqi4): Update expander to generate QImode zero-extract from AH. testsuite/ChangeLog: PR target/78904 * gcc.target/i386/pr78904-6.c: New test. From-SVN: r243968
2016-12-29rs6000.c (altivec_expand_builtin): Fix typos in error messages.Michael Meissner1-2/+2
2016-12-29 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.c (altivec_expand_builtin): Fix typos in error messages. From-SVN: r243963
2016-12-28re PR target/78904 (zero-extracts are not effective)Uros Bizjak3-1/+36
PR target/78904 * config/i386/constraints.md (Bn): New special memory constraint. * config/i386/predicates.md (norex_memory_operand): New predicate. * config/i386/i386.md (*extzvqi_mem_rex64): New insn pattern and corresponding peephole2 pattern. testsuite/ChangeLog: PR target/78904 * gcc.target/i386/pr78904-4.c: New test. * gcc.target/i386/pr78904-5.c: Ditto. From-SVN: r243955
2016-12-27predicates.md (const_0_to_12_operand): Rename predicate and change test from ↵Michael Meissner4-14/+14
0..11 to 0..12 to match the semantics of... [gcc] 2016-12-27 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/predicates.md (const_0_to_12_operand): Rename predicate and change test from 0..11 to 0..12 to match the semantics of the word extract/insert instructions. Change all callers. (const_0_to_11_operand): Likewise. * config/rs6000/rs6000.c (altivec_expand_builtin): Likewise. * config/rs6000/vsx.md (vextract4b): Likewise. (vextract4b_internal): Likewise. (vinsert4b): Likewise. (vinsert4b_internal): Likewise. (vinsert4b_di): Likewise. (vinsert4b_di_internal): Likewise. * config/rs6000/rs6000.md (zero_extendsi<mode>2): Fix offset used in xxextractuw to zero extend the word in the vector registers. (lfiwzx): Likewise. [gcc/testsuite] 2016-12-27 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p9-vinsert4b-2.c: Update test to test for 13 being out of bounds instead of 12. From-SVN: r243948
2016-12-27i386.c (ix86_secondary_reload): Require QImode intermediate for QImode mask ↵Uros Bizjak1-13/+8
register spill only for... * config/i386/i386.c (ix86_secondary_reload): Require QImode intermediate for QImode mask register spill only for !TARGET_AVX512DQ. Always use true_regnum to determine operand regno. From-SVN: r243945
2016-12-27i386.md (VI_512): Remove.Uros Bizjak1-14/+8
* config/i386/i386.md (VI_512): Remove. (vcond<V_512:mode><VI_AVX512BW:mode>): Use VI_AVX512BW mode iterator instead of VI_512. (vcondu<V_512:mode><VI_AVX512BW:mode>): Ditto. From-SVN: r243943
2016-12-27re PR translation/78922 (Comment submitted for translation in stringop.opt)Jakub Jelinek1-31/+0
PR translation/78922 * config/i386/stringop.opt: Remove. From-SVN: r243938
2016-12-27re PR target/78904 (zero-extracts are not effective)Uros Bizjak2-11/+17
PR target/78904 * config/i386/constraints.md (Bc): New special memory constraint. * config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use Bc constraint with nonimmediate_operand to allow constant memory operands. (*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1) (*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use Bc constraint with general_operand to allow constant memory operands. testsuite/ChangeLog: PR target/78904 * gcc.target/i386/pr78904-3.c: New test. From-SVN: r243937
2016-12-27i386.md (andqi_ext_1): Use general_operand predicate for operand 2.Uros Bizjak1-11/+12
* config/i386/i386.md (andqi_ext_1): Use general_operand predicate for operand 2. From-SVN: r243934
2016-12-27re PR target/78904 (zero-extracts are not effective)Uros Bizjak2-22/+10
PR target/78904 * config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use nonimmediate_operand instead of nonimmediate_x64nomem_operand. (*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1) (*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use general_operand instead of general_x64nomem_operand. * config/i386/predicates.md (nonimmediate_x64nomem_operand): Remove. (general_x64nomem_operand): Ditto. testsuite/ChangeLog: PR target/78904 * gcc.target/i386/pr78904-2.c: New test. From-SVN: r243933
2016-12-26re PR target/78904 (zero-extracts are not effective)Uros Bizjak2-246/+212
PR target/78904 * config/i386/i386.md (addqi_ext_1): Canonicalize insn pattern w.r.t. zero_extract RTXes. (*addqi_ext_2): Ditto. (testqi_ext_ccno_0): Canonicalize expander w.r.t. zero_extract RTXes. (testqi_ext_1_ccno): Rename from testqi_ext_ccno_0. (*testqi_ext_0): Merge with *testqi_ext_1. (*testqi_ext_1): Canonicalize insn pattern w.r.t. zero_extract RTXes. Update corresponding splitter. (*testqi_ext_2): Canonicalize insn pattern w.r.t. zero_extract RTXes. (*andqi_ext_0): Merge with *andqi_ext_1. (andqi_ext_1): Canonicalize insn pattern w.r.t. zero_extract RTXes. Rename from *andqi_ext_1. Update corresponding splitter and peephole2 patterns. (*andqi_ext_1_cc): Rename from *andqi_ext_0_cc. (*andqi_ext_2): Canonicalize insn pattern w.r.t. zero_extract RTXes. (*<any_or:code>qi_ext_0): Merge with *andqi_ext_1. (*<any_or:code>qi_ext_1): Canonicalize insn pattern w.r.t. zero_extract RTXes. Update corresponding splitter. (*<any_or:code>qi_ext_2): Canonicalize insn pattern w.r.t. zero_extract RTXes. (xorqi_cc_ext_1): Canonicalize expander w.r.t. zero_extract RTXes. (xorqi_ext_1_cc): Rename from xorqi_cc_ext_1. (*xorqi_cc_ext_1): Canonicalize insn pattern w.r.t. zero_extract RTXes. Update corresponding splitter. (*xorqi_ext_1_cc): Rename from *xorqi_cc_ext_1. (isinfxf2): Update calls to renamed expanders. (isinf<mode>2): Ditto. * config/i386/i386.c (ix86_expand_fp_compare): Ditto. (ix86_emit_fp_unordered_jump): Ditto. (ix86_emit_i387_round): Ditto. testsuite/ChangeLog: PR target/78904 * gcc.target/i386/pr78904.c: New test. From-SVN: r243929
2016-12-22Run tests only if the machine supports the instruction set.Dominik Vogt1-0/+17
gcc/ChangeLog: 2016-12-22 Dominik Vogt <vogt@linux.vnet.ibm.com> * config/s390/s390-c.c (s390_cpu_cpp_builtins_internal): Define __S390_ARCH_LEVEL__. gcc/testsuite/ChangeLog: 2016-12-22 Dominik Vogt <vogt@linux.vnet.ibm.com> * gcc.target/s390/md/setmem_long-1.c: Use "s390_useable_hw". * gcc.target/s390/md/rXsbg_mode_sXl.c: Likewise. * gcc.target/s390/md/andc-splitter-1.c: Likewise. * gcc.target/s390/md/andc-splitter-2.c: Likewise. * lib/gcc-dg.exp (gcc-dg-runtest): Export torture_current_flags. * gcc.target/s390/s390.exp: Import torture_current_flags. (check_effective_target_s390_useable_hw): New. (check_effective_target_s390_z900_hw): New. (check_effective_target_s390_z990_hw): New. (check_effective_target_s390_z9_ec_hw): New. (check_effective_target_s390_z10_hw): New. (check_effective_target_s390_z196_hw): New. (check_effective_target_s390_zEC12_hw): New. (check_effective_target_s390_z13_hw): New. (check_effective_target_z10_instructions): Removed. (torture tests): Add optimization level without -march=. Reorder torture tests for good cache usage. From-SVN: r243887
2016-12-21re PR rtl-optimization/11488 (Pre-regalloc scheduling severely worsens ↵Pat Haugen1-0/+35
performance) PR rtl-optimization/11488 * common/config/rs6000/rs6000-common.c (rs6000_option_optimization_table): Enable -fsched-pressure. * config/rs6000/rs6000.c (TARGET_COMPUTE_PRESSURE_CLASSES): Define target hook. (rs6000_option_override_internal): Set default -fsched-pressure algorithm. (rs6000_compute_pressure_classes): Implement target hook. From-SVN: r243866
2016-12-21[PATCH, v2, rs6000] pr65479 Add -fasynchronous-unwind-tables when the ↵Bill Seurer1-0/+7
-fsanitize=address option is seen. All feedback from the earlier version has been taken into account now. This patch adds the -fasynchronous-unwind-tables option to compilations when the -fsanitize=address option is seen but not if any -fasynchronous-unwind-tables options were already specified. -fasynchronous-unwind-tables causes a full strack trace to be produced when the sanitizer detects an error. Without the full trace several of the asan test cases fail on powerpc. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65479 for more information. Bootstrapped and tested on powerpc64le-unknown-linux-gnu, powerpc64be-unknown-linux-gnu, and x86_64-pc-linux-gnu with no regressions. Is this ok for trunk? [gcc] 2016-12-21 Bill Seurer <seurer@linux.vnet.ibm.com> PR sanitizer/65479 * config/rs6000/rs6000.c (rs6000_option_override_internal): Add -fasynchronous-unwind-tables option when -fsanitize=address is specified. From-SVN: r243863
2016-12-21re PR target/71321 (x86: worse code for uint8_t % 10 and / 10)Bernd Schmidt2-0/+55
PR target/71321 * config/i386/i386.md (lea<mode>_general_2b, lea<mode>_general_3b): New patterns. * config/i386/predicates.md (const123_operand): New. PR target/71321 * gcc.target/i386/pr71321.c: New test. From-SVN: r243861
2016-12-21nvptx: do not assume that crtl->is_leaf is unsetAlexander Monakov1-3/+4
PR target/78831 * config/nvptx/nvptx.c (init_softstack_frame): Remove assert. Compute crtl->is_leaf only if unset. Adjust comment. From-SVN: r243855
2016-12-20[ARM] PR target/78694: Avoid invalid RTL sharing in minipool codeKyrylo Tkachov1-5/+7
PR target/78694 * config/arm/arm.c (dump_minipool): Copy mp->value before emitting it in the minipool to avoid invalid RTL sharing. * gcc.c-torture/compile/pr78694.c: New test. From-SVN: r243820
2016-12-19rs6000-protos.h (expand_strn_compare): Declare.Aaron Sawdey4-4/+417
* config/rs6000/rs6000-protos.h (expand_strn_compare): Declare. * config/rs6000/rs6000.md (UNSPEC_CMPB): New unspec. (cmpb<mode>3): pattern for generating cmpb. (cmpstrnsi): pattern to expand strncmp (). * config/rs6000/rs6000.opt (mstring-compare-inline-limit): Add a new target option for controlling how much code inline expansion of strncmp() will be allowed to generate. * config/rs6000/rs6000.c (expand_strncmp_align_check): generate code for runtime page crossing check of strncmp () args. (expand_strn_compare): Function to do builtin expansion of strncmp (). From-SVN: r243813
2016-12-19i386.md (*popcounthi2_1): New insn_and_split pattern.Uros Bizjak1-0/+18
* config/i386/i386.md (*popcounthi2_1): New insn_and_split pattern. testsuite/ChangeLog: * gcc.target/i386/pr59874-3.c: New test. From-SVN: r243811
2016-12-19rs6000.c: Add handling for early expansion of vector multiply builtins.Will Schmidt1-0/+30
2016-12-19 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000.c: Add handling for early expansion of vector multiply builtins. [gcc/testsuite] 2016-12-19 Will Schmidt <will_schmidt@vnet.ibm.com> * gcc.dg/vmx/mult-even-odd-be-order.c : Mark variables as volatile. * gcc.target/powerpc/fold-vec-mult-char.c : New. * gcc.target/powerpc/fold-vec-mult-float.c : New. * gcc.target/powerpc/fold-vec-mult-floatdouble.c : New. * gcc.target/powerpc/fold-vec-mult-int.c : New. * gcc.target/powerpc/fold-vec-mult-int128-p8.c : New. * gcc.target/powerpc/fold-vec-mult-int128-p9.c : New. * gcc.target/powerpc/fold-vec-mult-longlong.c : New. * gcc.target/powerpc/fold-vec-mult-short.c : New. From-SVN: r243807
2016-12-19rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of ↵Will Schmidt1-0/+18
vector subtract builtins. 2016-12-19 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vector subtract builtins. [gcc/testsuite] 2016-12-19 Will Schmidt <will_schmidt@vnet.ibm.com> * gcc.target/powerpc/fold-vec-sub-char.c: New. * gcc.target/powerpc/fold-vec-sub-float.c: New. * gcc.target/powerpc/fold-vec-sub-floatdouble.c: New. * gcc.target/powerpc/fold-vec-sub-int.c: New. * gcc.target/powerpc/fold-vec-sub-int128.c: New. * gcc.target/powerpc/fold-vec-sub-longlong.c: New. * gcc.target/powerpc/fold-vec-sub-short.c: New. From-SVN: r243806
2016-12-19PR target/78748: S/390: Fix ICE with ANDC splitter.Dominik Vogt1-1/+5
gcc/ChangeLog: 2016-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com> PR target/78748 * config/s390/s390.md ("*andc_split_<mode>"): Allow memory destination only if it coincides with operand 2. gcc/testsuite/ChangeLog: 2016-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com> PR target/78748 * gcc.c-torture/compile/pr78748.c: New test. From-SVN: r243793
2016-12-19netbsd.h (LINK_EH_SPEC): Define.Krister Walfridsson1-0/+4
2016-12-19 Krister Walfridsson <krister.walfridsson@gmail.com> * config/netbsd.h (LINK_EH_SPEC): Define. From-SVN: r243791
2016-12-17avx512bwintrin.h: Add new k-mask intrinsics.Andrew Senkevich5-3/+47
* config/i386/avx512bwintrin.h: Add new k-mask intrinsics. * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512fintrin.h: Ditto. * config/i386/i386-builtin.def (__builtin_ia32_kaddqi, __builtin_ia32_kaddhi, __builtin_ia32_kaddsi, __builtin_ia32_kadddi): New. * config/i386/sse.md (kadd<mode>): New. testsuite/ChangeLog: * gcc.target/i386/avx512bw-kaddd-1.c: New test. * gcc.target/i386/avx512bw-kaddq-1.c: Ditto. * gcc.target/i386/avx512dq-kaddb-1.c: Ditto. * gcc.target/i386/avx512f-kaddw-1.c: Ditto. From-SVN: r243774
2016-12-17i386.md (*tzcnt<mode>_1): Merge *tzcnt<mode>_1_falsedep_1 and *tzcnt<mode>_1 ↵Uros Bizjak1-147/+106
to define_insn_and_split pattern. * config/i386/i386.md (*tzcnt<mode>_1): Merge *tzcnt<mode>_1_falsedep_1 and *tzcnt<mode>_1 to define_insn_and_split pattern. Adjust split condition to split after epilogue_completed. (ctz<mode>2): Remove expander. (ctz<mode>2): Merge *ctz<mode>2_falsedep_1 and *ctz<mode>2 to define_insn_and_split pattern. Adjust split condition to split after epilogue_completed. (clz<mode>2_lznct): Remove expander. (clz<mode>2_lzcnt): Merge *clz<mode>2_lzcnt_falsedep_1 and *clz<mode>2 to define_insn_and_split pattern. Adjust split condition to split after epilogue_completed. (<lt_zcnt>_<mode>): Remove expander. (<lt_zcnt>_<mode>): Merge *<lt_zcnt>_<mode>_falsedep_1 and *<lt_zcnt>_<mode> to define_insn_and_split pattern. Adjust split condition to split after epilogue_completed. (<lt_zcnt>_hi): New insn pattern. (popcount<mode>2): Remove expander. (popcount<mode>2): Merge *popcount<mode>2_falsedep_1 and *popcount<mode>2 to define_insn_and_split pattern. Adjust split condition to split after epilogue_completed. (popcounthi2): New insn pattern. From-SVN: r243772
2016-12-17byte-in-either-range-0.c: New test.Kelvin Nilsen3-0/+229
gcc/testsuite/ChangeLog: 2016-12-16 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/byte-in-either-range-0.c: New test. * gcc.target/powerpc/byte-in-either-range-1.c: New test. * gcc.target/powerpc/byte-in-range-0.c: New test. * gcc.target/powerpc/byte-in-range-1.c: New test. * gcc.target/powerpc/byte-in-set-0.c: New test. * gcc.target/powerpc/byte-in-set-1.c: New test. * gcc.target/powerpc/byte-in-set-2.c: New test. gcc/ChangeLog: 2016-12-16 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/altivec.md (UNSPEC_CMPRB): New unspec value. (UNSPEC_CMPRB2): New unspec value. (UNSPEC_CMPEQB): New unspec value. (cmprb): New expansion. (*cmprb_internal): New insn. (*setb_internal): New insn. (cmprb2): New expansion. (*cmprb2_internal): New insn. (cmpeqb): New expansion. (*cmpeqb_internal): New insn. * config/rs6000/rs6000-builtin.def (BU_P9_2): New macro. (BU_P9_64BIT_2): Likewise. (BU_P9_OVERLOAD_2): Likewise. (CMPRB): Add byte-in-range built-in function. (CMBRB2): Add byte-in-either-range built-in function. (CMPEQB): Add byte-in-set built-in function. (CMPRB): Add overload support for byte-in-range function. (CMPRB2): Add overload support for byte-in-either-range function. (CMPEQB): Add overload support for byte-in-set built-in function. * config/rs6000/rs6000-c.c (P9_BUILTIN_CMPRB): Macro expansion to define argument types for new builtin. (P9_BUILTIN_CMPRB2): Likewise. (P9_BUILTIN_CMPEQB): Likewise. * doc/extend.texi (PowerPC AltiVec Built-in Functions): Rearrange the order of presentation for certain built-in functions (scalar_extract_exp, scalar_extract_sig, scalar_insert_exp) (scalar_cmp_exp_gt, scalar_cmp_exp_lt, scalar_cmp_exp_eq) (scalar_cmp_exp_unordered, scalar_test_data_class) (scalar_test_neg) to improve locality and flow. Document the new __builtin_scalar_byte_in_set, __builtin_scalar_byte_in_range, and __builtin_scalar_byte_in_either_range functions. From-SVN: r243770
2016-12-16[AArch64] Split X-reg UBFIZ into W-reg LSL when possibleKyrylo Tkachov1-0/+18
* config/aarch64/aarch64.md: New define_split above bswap<mode>2. * gcc.target/aarch64/ubfiz_lsl_1.c: New test. From-SVN: r243756
2016-12-16[AArch64] Split X-reg UBFX into W-reg LSR when possibleKyrylo Tkachov1-0/+20
* config/aarch64/aarch64.md: New define_split above insv<mode>. * gcc.target/aarch64/ubfx_lsr_1.c: New test. From-SVN: r243755
2016-12-16The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2 ↵Wilco Dijkstra2-36/+12
doesn't support RSC with an immediate. The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2 doesn't support RSC with an immediate. We can however emulate RSC with zero using a shifted SBC. If we add this to subsi3_carryin the negdi patterns can be merged, simplifying things a bit. This should generate identical code in all cases. gcc/ * config/arm/arm.md (subsi3_carryin): Add Thumb-2 RSC #0. (arm_negdi2) Rename to negdi2_insn, allow on Thumb-2. * config/arm/thumb2.md (thumb2_negdi2): Remove pattern. From-SVN: r243745
2016-12-16Thumb uses a special register allocation order to increase the use of low ↵Wilco Dijkstra1-1/+1
registers. Thumb uses a special register allocation order to increase the use of low registers. Oddly enough, LR appears before R12, which means that LR must be saved and restored even if R12 is available. Swapping R12 and LR means this simple example now uses R12 as a temporary (just like ARM): int f(long long a, long long b) { if (a < b) return 1; return a + b; } gcc/ * config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14. From-SVN: r243744
2016-12-16[ARC] Remove old prof patterns.Claudiu Zissulescu1-63/+0
gcc/ 2016-12-16 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (call_prof): Remove. (call_value_prof): Likewise. (sibcall_prof): Likewise. (sibcall_value_prof): Likewise. From-SVN: r243743
2016-12-16[ARC] Rework code for profiling.Claudiu Zissulescu5-204/+16
gcc/ 2016-12-16 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.h (LINK_SPEC): Tidy up. (ENDFILE_SPEC): Likewise. (LIB_SPEC): Likewise. (STARTFILE_SPEC): Include gcrt0 when profiling. (FUNCTION_PROFILER): Use __mcount. * config/arc/arc.opt (mucb-mcount): Remove. * doc/invoke.texi (ARC): Remove mucb-mcount doc. * arc/arc-protos.h (arc_profile_call): Remove. * config/arc/arc.c (write_profile_sections): Likewise. (arc_profile_call): Likewise. (unspec_prof_hash): Likewise. (unspec_prof_htab_eq): Likewise. (arc_legitimate_constant_p): Remove UNSPEC_PROF. (arc_reorg): Remove call to write_profile_sections. * config/arc/arc.md (call): Remove call to arc_profile_call. (call_value): Likewise. (sibcall): Likewise. (sibcall_value): Likewise. (define_constants): Remove UNSPEC_PROF. libgcc/ * config.host (arc*-*-linux-uclibc*): Remove libgmon, crtg, and crtgend. (arc*-*-elf*): Likewise. * config/arc/t-arc: Remove old gmon lib targets. * config/arc/crtg.S: Remove. * config/arc/crtgend.S: Likewise. * config/arc/gmon/atomic.h: Likewise. * config/arc/gmon/auxreg.h: Likewise. * config/arc/gmon/dcache_linesz.S: Likewise. * config/arc/gmon/gmon.c: Likewise. * config/arc/gmon/machine-gmon.h: Likewise. * config/arc/gmon/mcount.c: Likewise. * config/arc/gmon/prof-freq-stub.S: Likewise. * config/arc/gmon/prof-freq.c: Likewise. * config/arc/gmon/profil.S: Likewise. * config/arc/gmon/sys/gmon.h: Likewise. * config/arc/gmon/sys/gmon_out.h: Likewise. * config/arc/t-arc-newlib: Likewise. * config/arc/t-arc700-uClibc: Renamed to t-arc-uClibc. From-SVN: r243742
2016-12-16[ARC] Rework ARC600 64-bit multiplication patterns.Claudiu Zissulescu1-24/+40
Previously users of mulsidi_600 and umulsidi_600 had to take care of moving the multiplication result into the final destination themselves (from the MUL64_OUT_REG register). This commit converts these two instruction patterns into insn_and_split patterns that now take the final destination as an extra operand. The insn_and_split patterns generate the multiplication using two new multiplication instruction patterns, then generate the move of the result from the MUL64_OUT_REG register into the final destination. This is a clean up commit, there should be no user visible changes after this commit. 2016-12-16 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (mulsidi_600): Change to insn_and_split, generate new mul64 insn for core multiplication work. (umulsidi_600): Likewise, but use mulu64 insn. (mul64): New pattern, content taken from old mulsidi_600 insn pattern. (mulu64): Likewise, but using umulsidi_600. (mulsidi3): Remove move to destination, this is now handled by mulsidi_600 insn_and_split. (umulsidi3): Likewise, but using umulsidi_600. From-SVN: r243741
2016-12-15avx512bwintrin.h: Add new k-mask intrinsics.Andrew Senkevich5-5/+120
* config/i386/avx512bwintrin.h: Add new k-mask intrinsics. * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512fintrin.h: Ditto. * config/i386/i386-builtin.def (__builtin_ia32_kmovb, __builtin_ia32_kmovd, __builtin_ia32_kmovq): New. (__builtin_ia32_kmov16): Rename to __builtin_ia32_kmovw. * config/i386/sse.md (kmov<mskmodesuffix>): New. testsuite/ChangeLog: * gcc.target/i386/avx512bw-kmovd-1.c: New test. * gcc.target/i386/avx512bw-kmovd-2.c: Ditto. * gcc.target/i386/avx512bw-kmovd-3.c: Ditto. * gcc.target/i386/avx512bw-kmovd-4.c: Ditto. * gcc.target/i386/avx512bw-kmovq-1.c: Ditto. * gcc.target/i386/avx512bw-kmovq-2.c: Ditto. * gcc.target/i386/avx512bw-kmovq-3.c: Ditto. * gcc.target/i386/avx512bw-kmovq-4.c: Ditto. * gcc.target/i386/avx512dq-kmovb-2.c: Ditto. * gcc.target/i386/avx512dq-kmovb-3.c: Ditto. * gcc.target/i386/avx512dq-kmovb-4.c: Ditto. * gcc.target/i386/avx512dq-kmovb-5.c: Ditto. * gcc.target/i386/avx512f-kmovw-2.c: Ditto. * gcc.target/i386/avx512f-kmovw-3.c: Ditto. * gcc.target/i386/avx512f-kmovw-4.c: Ditto. * gcc.target/i386/avx512f-kmovw-5.c: Ditto. From-SVN: r243728
2016-12-15i386.md (ffs<mode>2): Generate CCCmode flags register for TARGET_BMI.Uros Bizjak2-134/+108
* config/i386/i386.md (ffs<mode>2): Generate CCCmode flags register for TARGET_BMI. (ffssi2_no_cmove): Ditto. (*tzcnt<mode>_1_falsedep_1): New insn_and_split pattern. (*tzcnt<mode>_1_falsedep): New insn pattern. (LT_ZCNT): New mode iterator. (lt_zcnt): New mode attribute. (lt_zcnt_type): New mode attribute. (<lt_zcnt>_<mode>): Macroize expander from bmi_tzcnt_<mode> and lzcnt_<mode> using LT_ZCNT mode iterator. (*<lt_zcnt>_<mode>_falsedep_1): Macroize insn from *bmi_tzcnt_<mode>_falsedep_1 and *lzcnt_<mode>_falsedep_1 using LT_ZCNT mode iterator. (*<lt_zcnt>_<mode>_falsedep): Macroize insn from *bmi_tzcnt_<mode>_falsedep and *lzcnt_<mode>_falsedep using LT_ZCNT mode iterator. (*<lt_zcnt>_<mode>): Macroize insn from *bmi_tzcnt_<mode> and *lzcnt_<mode> using LT_ZCNT mode iterator. * config/i386/i386-builtin.def (__builtin_ia32_tzcnt_u16) (__builtin_ia32_tzcnt_u32, __builtin_ia32_tzcnt_u64, __builtin_ctzs): Update for rename. From-SVN: r243727
2016-12-15Using leaf_function_p in a backend is dangerous as it incorrectly returns ↵Wilco Dijkstra2-22/+5
false... Using leaf_function_p in a backend is dangerous as it incorrectly returns false if it is called while in a sequence (for example during prolog/epilog generation). Replace all uses with crtl->is_leaf as this is now initialized early enough in ira.c. This typically causes no code generation differences unless there was a bug due to leaf_function_p returning the wrong value. gcc/ * config/arm/arm.h (TARGET_BACKTRACE): Use crtl->is_leaf. * config/arm/arm.c (arm_option_check_internal): Improve comment. (thumb_force_lr_save): Use crtl->is_leaf. (arm_get_frame_offsets): Remove comment. Use crtl->is_leaf. (thumb_far_jump_used_p): Remove comment. (arm_frame_pointer_required): Use crtl->is_leaf. From-SVN: r243720
2016-12-15[arm] Add missing arm-isa.hRichard Earnshaw1-0/+156
From-SVN: r243718
2016-12-15[arm] Permit 'auto' in -mfpuRichard Earnshaw7-67/+117
Now we finally have the infrastructure in place we can now derive details of the FPU from a CPU entry. This patch enables this for the existing cores that already have an explicit FPU in their product names. * arm-fpus.def: Add CNAME field to all FPU definitions. * genopt.sh: Use explicit enumeration tags for FPU entries. * arm-tables.opt: Regenerated. * arm.opt (mfpu): Provide initial value. * arm-opts.h (enum fpu_type): Build the enumeration from the list of available FPUs. Add 'auto' entry on the end. * arm.c (arm_configure_build_target): Only do explicit configuration of the FPU features if the selected FPU is not 'auto'. (arm_option_override): Adjust initialization of arm_fpu_index. Emit an error if we have a hard float ABI request, but the processor does not support floating-point. (arm_option_print): Handle -mfpu=auto. (arm_valid_target_attribute_rec): Don't permit fpu=auto in pragmas or function attributes. (arm_identify_fpu_from_isa): Handle effective soft-float when the FPU is automatically detected. * arm-cores.def (arm1136jf-s): Add feature ISA_FP_DBL. (arm1176jzf-s): Likewise. (mpcore): Likewise. (arm1156t2f-s): Likewise. From-SVN: r243716
2016-12-15[arm] Remove FEATURES field from FPU descriptionsRichard Earnshaw3-58/+24
Now that everything uses the new ISA features, we can remove the FEATURES field from the FPU descriptions, along with all the macros and definitions associated with it. * arm-fpus.def (ARM_FPU): Remove features field from all definitions. * arm.h (arm_fpu_feature_set): Delete typedef. (FPU_FL_NONE): Delete. (FPU_FL_NEON): Delete. (FPU_FL_FP16): Delete. (FPU_FL_CRYPTO): Delete. (FPU_FL_DBL): Delete. (FPU_FL_D32): Delete. (FPU_FL_VFPv2): Delete. (FPU_FL_VFPv3): Delete. (FPU_FL_VFPv4): Delete. (FPU_FL_VFPv5): Delete. (FPU_FL_AMRv8): Delete. (FPU_VFPv2): Delete. (FPU_VFPv3): Delete. (FPU_VFPv4): Delete. (FPU_VFPv5): Delete. (FPU_ARMv8): Delete. (FPU_DBL): Delete. (FPU_D32): Delete. (FPU_NEON): Delete. (FPU_CRYPTO): Delete. (FPU_FP16): Delete. (arm_fpu_desc): Delete features field. * arm.c (all_fpus): Don't initialize feature field. From-SVN: r243715
2016-12-15[arm] Use ISA feature sets for determining inlinabilityRichard Earnshaw1-8/+19
Now that we can construct the build target isa from the cl_target_options data we can use this to determine inlinability. This eliminates the final remaining use of the FPU features field. * arm.c (arm_can_inline_p): Use ISA features for determining inlinability. From-SVN: r243714
2016-12-15[arm] Use cl_target_options for configuring the active targetRichard Earnshaw3-14/+27
It now becomes apparent that it would be better to use the the cl_target_options as the basis for calling arm_configure_build_target; it already contains exactly the same fields that we need. I chose not to rewrite the earlier patches as that would make the progression of changes seem less logical than it currently is, with several early changes having no immediate justification. * arm-protos.h (arm_configure_build_target): Change second argument to cl_target_options. * arm.c (arm_configure_build_target): Likewise. (arm_option_restore): Update accordingly. (arm_option_override): Create the target_option_default_node before calling arm_configure_build_target. Use it in call of latter. Resynchronize after all other overrides have been calculated. (arm_valid_target_attribute_tree): Use the target options for reconfiguration. Resynchronize after performing override checks. * arm-c.c (arm_pragma_target_parse): Use target optiosn from cur_tree to reconfigure the build target. From-SVN: r243713
2016-12-15[arm] Use arm_active_target for most FP feature testsRichard Earnshaw2-21/+15
Now that the isa feature bits are all available in arm_active_target we can use that for most of the feature tests that are needed. * arm.h (TARGET_VFPD32): Use arm_active_target. (TARGET_VFP3): Likewise. (TARGET_VFP5): Likewise. (TARGET_VFP_SINGLE): Likewise. (TARGET_VFP_DOUBLE): Likewise. (TARGET_NEON_FP16): Likewise. (TARGET_FP16): Likewise. (TARGET_FMA): Likewise. (TARGET_FPU_ARMV8): Likewise. (TARGET_CRYPTO): Likewise. (TARGET_NEON): Likewise. (TARGET_FPU_FEATURES): Delete. * arm.c (arm_option_check_internal): Check for iwmmxt conflict with Neon using arm_active_target. From-SVN: r243712
2016-12-15[arm] Eliminate TARGET_FPU_NAMERichard Earnshaw2-3/+24
Rather than assuming a specific fpu name has been selected, we work out the FPU from the ISA properties. This is necessary since once we have default FPUs selected by the processor, there will be no explicit entry in the table of fpus to refer to. This also fixes a bug with the code I added recently to permit new aliases for existing FPU names: the new names cannot be passed to the assembler since it does not recognize them. By mapping the ISA features back to the canonical names we avoid having to teach the assembler about the new names. * arm.h (TARGET_FPU_NAME): Delete. * arm.c (arm_identify_fpu_from_isa): New function. (arm_declare_function_name): Use it to get the name for the FPU. From-SVN: r243711
2016-12-15[arm] Initialize fpu capability bits in arm_active_targetRichard Earnshaw4-26/+55
Now that we can describe the FPU with the standard ISA bits we need to initialize them. However, the FPU settings can be changed with target build attributes, so we also need to reset them if things change. This requires a bit of juggling about with the existing code to ensure that the active target is reconfigured after each change to the target options. * arm-protos.h: Include sbitmap.h (arm_configure_build_target): Make public. * arm.c (arm_configure_build_target): Now not static. (arm_valid_target_attribute_rec): Move internal option check to... (arm_valid_target_attribute_tree0: ... here. Also reconfingure the active target. (arm_override_options_after_change): Call arm_configure_build_target. (isa_all_fpubits): Renamed from isa_fpubits. (arm_option_restore): New function. (TARGET_OPTION_RESTORE): Register it. (arm_configure_build_target): Initialize the FPU capability bits in the isa. (arm_option_override): Move the code that forces the setting of the FPU option before the call to arm_configure_build_target. * arm.opt (march): Mark as Save. (mcpu, mtune): Likewise. * arm-c.c (arm_pragma_target_parse): Reconfigure the build target after pragmas change the target options. From-SVN: r243710
2016-12-15[arm] Add isa features to FPU descriptionsRichard Earnshaw4-29/+30
Similar to the new CPU and architecture ISA feature lists, we now add similar capabilities to each FPU description. We don't use these yet, that will come in later patches. These follow the same style as the newly modified flag sets, but use slightly different defaults that more accurately reflect the ISA specifications. * arm-isa.h (isa_feature): Add bits for VFPv4, FPv5, fp16conv, fP_dbl, fp_d32 and fp_crypto. (ISA_ALL_FPU): Add all the new bits. (ISA_VFPv2, ISA_VFPv3, ISA_VFPv4, ISA_FPv5): New macros. (ISA_FP_ARMv8, ISA_FP_DBL, ISA_FP_D32, ISA_NEON, ISA_CRYPTO): Likewise. * arm-fpus.def: Add ISA features to all FPUs. * arm.h: (arm_fpu_desc): Add new field for ISA bits. * arm.c (all_fpus): Initialize it. * arm-tables.opt: Regenerated. From-SVN: r243709
2016-12-15[arm] Remove FPU rev fieldRichard Earnshaw3-30/+46
Similar to the main ISA, we convert the FPU revision into a set of feature bits. This permits a more complex set of capability relationships to be expressed more easily. For now we continue to use the traditional bitmasks. * arm.h (FPU_FL_VFPv2) New feature bit. (FPU_FL_VFPv3, FPU_FL_VFPv4, FPU_FL_VFPv5, FPU_FL_ARMv8): Likewise. (FPU_VFPv2, FPU_VFPv3, FPU_VFPv4, FPU_VFPv5, FPU_ARMv8): New helper macros. (FPU_DBL, FPU_D32, FPU_NEON, FPU_CRYPTO, FPU_FP16): Likewise. (TARGET_FPU_REV): Delete. (TARGET_VFP3): Use feature bits. (TARGET_VFP5): Likewise. (TARGET_FMA): Likewise. (TARGET_FPU_ARMV8): Likewise. (struct arm_fpu_desc): Delete rev field. * arm-fpus.def: Delete REV entry, use new feature bits and macros. * arm.c (all_fpus): Delete rev field. From-SVN: r243708
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