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2022-10-17RISC-V: Fix format[NFC]Ju-Zhe Zhong1-1/+1
2022-10-17RISC-V: Reorganize mangle_builtin_type.[NFC]Ju-Zhe Zhong1-13/+13
2022-10-16Add new constraints for upcoming autoinc fixesJeff Law2-0/+37
2022-10-16Rename "z" constraint to "Zz" on the H8/300Jeff Law2-5/+5
2022-10-15Fix bug in register move costing on H8/300Jeff Law1-1/+1
2022-10-14Fix PR target/107248Eric Botcazou1-12/+12
2022-10-14middle-end, c++, i386, libgcc: std::bfloat16_t and __bf16 arithmetic supportJakub Jelinek4-69/+94
2022-10-13machmode: Introduce GET_MODE_NEXT_MODE with previous GET_MODE_WIDER_MODE mean...Jakub Jelinek1-1/+1
2022-10-13[AArch64] Improve bit tests [PR105773]Wilco Dijkstra3-44/+72
2022-10-12RISC-V: Remove TUPLE size macro define. [NFC]Ju-Zhe Zhong1-3/+0
2022-10-12RISC-V: Apply clang-format for riscv-vector-builtins.* [NFC]Ju-Zhe Zhong3-7/+6
2022-10-12RISC-V: Refine register_builtin_types function. [NFC]Ju-Zhe Zhong2-40/+50
2022-10-12RISC-V: Move function place to make it looks better. [NFC]Ju-Zhe Zhong2-19/+19
2022-10-12Remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDSCui,Lili2-12/+8
2022-10-11i386: Fix up RTL checking ICE [PR107185]Jakub Jelinek1-1/+1
2022-10-11amdgcn: Add vector integer negate insnAndrew Stubbs1-0/+13
2022-10-11amdgcn: vec_init for multiple vector sizesAndrew Stubbs2-26/+143
2022-10-11amdgcn: Add vec_extract for partial vectorsAndrew Stubbs3-1/+44
2022-10-11amdgcn: Resolve insn conditions at compile timeAndrew Stubbs2-4/+30
2022-10-11amdgcn: add multiple vector sizesAndrew Stubbs4-425/+938
2022-10-11Add define_insn_and_split to support general version of "kxnor".liuhongt1-0/+71
2022-10-11Tigthen the addition of -lgcc_eh to vxworks_libgcc_specOlivier Hainque1-4/+44
2022-10-11RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" ...Ju-Zhe Zhong3-25/+25
2022-10-11RISC-V: Add missing vsetvl instruction type.Ju-Zhe Zhong1-1/+2
2022-10-10RISC-V: Add newline to the end of file [NFC]Kito Cheng1-1/+1
2022-10-10Fix unrecognizable insn of cvtss2si.liuhongt1-2/+2
2022-10-10arc: Remove obsolete mRcq and mRcw options.Claudiu Zissulescu1-4/+6
2022-10-10arc: Remove Rcq constraint.Claudiu Zissulescu3-116/+104
2022-10-10arc: Remove Rcw constraintClaudiu Zissulescu2-124/+110
2022-10-10arc: Remove Rcr constraintClaudiu Zissulescu2-28/+18
2022-10-10arc: Use negative enter pattern instruction's offsetsClaudiu Zissulescu1-3/+3
2022-10-09pru: Add cbranchdi4 patternDimitar Dimitrov3-0/+202
2022-10-09pru: Optimize DI shiftsDimitar Dimitrov1-0/+196
2022-10-09MIPS: improve -march=native arch detectionYunQiang Su1-3/+22
2022-10-07Specialize paths to version.h in _vxworks-versions.hOlivier Hainque1-5/+14
2022-10-07fix clang warningsMartin Liska1-2/+2
2022-10-07Downgrade DWARF_VERSION_DEFAULT to 3 for VxWorks >= 7Olivier Hainque1-1/+1
2022-10-07Introduce DWARF_VERSION_DEFAULT and redefine for VxWorksOlivier Hainque2-12/+6
2022-10-06aarch64: Remove redundant zero-extends with LDARKyrylo Tkachov1-0/+17
2022-10-06aarch64: update Ampere-1 core definitionPhilipp Tomsich1-1/+1
2022-10-06aarch64: fix off-by-one in reading cpuinfoPhilipp Tomsich1-2/+2
2022-10-06arc: Remove max-page-size and common-page-size forced settingClaudiu Zissulescu1-1/+0
2022-10-05rs6000: Remove the wD constraintSegher Boessenkool1-6/+0
2022-10-05rs6000: Rework vsx_extract_<mode>Segher Boessenkool1-43/+37
2022-10-05rs6000: Remove "wD" from *vsx_extract_<mode>_storeSegher Boessenkool1-2/+3
2022-10-05RISC-V: Introduce RVV header to enable builtin typesJu-Zhe Zhong9-13/+210
2022-10-05RISC-V: remove deprecate pic code model macroVineet Gupta1-5/+0
2022-10-04aarch64: Define __ARM_FEATURE_RCPCRichard Sandiford4-6/+8
2022-10-03gcc/config/t-i386: add build dependencies on i386-builtin-types.incSergei Trofimovich1-0/+5
2022-10-03vect: while_ult for integer masksAndrew Stubbs1-1/+7
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