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2015-08-05gcc * config/rl78/rl78.c (rl78_force_nonfar_3): Remove optimizationNick Clifton1-7/+0
to allow identical far pointers to remain. tests * gcc.target/rl78: New directory. * gcc.target/rl78/rl78.exp: New file: Test driver. * gcc.target/rl78/test_addm3.c: New file: Test adds. From-SVN: r226624
2015-08-05Disable AVX-512VL insns for scalar mode operands on -march=knl.Kirill Yukhin2-14/+23
gcc/ * config/i386/i386.md (define_attr "isa"): Addd avx512vl and noavx512vl. (define_attr "enabled"): Handle avx521vl and noavx512vl. * config/i386/sse.md (define_insn "vec_dupv2df<mask_name>"): Split AVX-512 alternative out of SSE. (define_insn "*vec_concatv2df"): Ditto. From-SVN: r226612
2015-08-05Merge SSE and AVX ptest patterns.Kirill Yukhin2-25/+28
gcc/ * config/i386/i386.c (bdesc_args): Rename CODE_FOR_sse4_1_ptest into CODE_FOR_sse4_1_ptestv2di and CODE_FOR_avx_vtestps256 into CODE_FOR_avx_ptestv4di. * config/i386/sse.md (define_mode_iterator V_AVX): New. (define_mode_attr sse4_1): Extend to other 128/256-bit modes. (define_insn "avx_ptest256"): Merge this ... (define_insn "sse4_1_ptest"): And this ... (define_insn "<sse4_1>_ptest<mode>"): Into this. Use V_AVX iterator. From-SVN: r226611
2015-08-04[MOXIE] Hookize PRINT_OPERAND and PRINT_OPERAND_ADDRESSAnatoly Sokolov3-10/+7
From-SVN: r226594
2015-08-04[AArch64] PR target/66731 Fix fnmul insn with -frounding-math (rtx costs)Szabolcs Nagy1-5/+17
2015-08-04 Szabolcs Nagy <szabolcs.nagy@arm.com> PR target/66731 * config/aarch64/aarch64.c (aarch64_rtx_costs): Fix NEG cost for FNMUL. (aarch64_rtx_mult_cost): Fix MULT cost with -frounding-math. From-SVN: r226586
2015-08-04aarch64.c: Change inner loop statement cost to be consistent with other targets.Pawel Kupidura1-8/+2
gcc/ 2015-08-04 Pawel Kupidura <pawel.kupidura@arm.com> * config/aarch64/aarch64.c: Change inner loop statement cost to be consistent with other targets. From-SVN: r226575
2015-08-04neon.md (neon_vget_lanev2di): Handle big-endian targets.Christophe Lyon1-1/+16
2015-08-04 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/neon.md (neon_vget_lanev2di): Handle big-endian targets. From-SVN: r226574
2015-08-04nvptx.h (struct nvptx_pseudo_info): Delete.Nathan Sidwell1-7/+0
* config/nvptx/nvptx.h (struct nvptx_pseudo_info): Delete. (machine_function): Remove pseudos field. From-SVN: r226573
2015-08-04[AArch64][14/14] Reuse target_option_current_node when passing pragma string ↵Kyrylo Tkachov1-0/+12
to target attribute * config/aarch64/aarch64.c (aarch64_option_valid_attribute_p): Exit early and use target_option_current_node if processing current pragma. From-SVN: r226567
2015-08-04[AArch64][11/14] Re-layout SIMD builtin types on builtin expansionKyrylo Tkachov4-3/+63
* config/aarch64/aarch64.c (aarch64_option_valid_attribute_p): Initialize simd builtins if TARGET_SIMD. * config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins): Make sure that the builtins are initialized only once no matter how many times the function is called. (aarch64_init_builtins): Unconditionally initialize crc builtins. (aarch64_relayout_simd_param): New function. (aarch64_simd_expand_args): Use above during argument expansion. * config/aarch64/aarch64-c.c (aarch64_pragma_target_parse): Initialize simd builtins if TARGET_SIMD. * config/aarch64/aarch64-protos.h (aarch64_init_simd_builtins): New prototype. (aarch64_relayout_simd_types): Likewise. * gcc.target/aarch64/target_attr_crypto_ice_1.c: New test. From-SVN: r226564
2015-08-04[AArch64][10/14] Implement target pragmasKyrylo Tkachov7-90/+237
* config.gcc (aarch64*-*-*): Specify c_target_objs and cxx_target_objs. * config/aarch64/aarch64.h (REGISTER_TARGET_PRAGMAS): Define. (TARGET_CPU_CPP_BUILTINS): Redefine to call aarch64_cpu_cpp_builtins. * config/aarch64/aarch64.c (aarch64_override_options_internal): Remove static keyword. (aarch64_reset_previous_fndecl): New function. (aarch64_handle_attr_isa_flags): Handle "+nothing" in the beginning of the string. * config/aarch64/aarch64-c.c: New file. * config/aarch64/arm_acle.h: Add pragma +crc+nofp at the top. Push and pop options at beginning and end. Remove ifdef __ARM_FEATURE_CRC32. * config/aarch64/arm_neon.h: Remove #ifdef check on __ARM_NEON. Add pragma +nothing+simd and +nothing+crypto where appropriate. * config/aarch64/t-aarch64 (aarch64-c.o): New rule. * config/aarch64/aarch64-protos.h (aarch64_cpu_cpp_builtins): Define prototype. (aarch64_register_pragmas): Likewise. (aarch64_reset_previous_fndecl): Likewise. (aarch64_process_target_attr): Likewise. (aarch64_override_options_internal): Likewise. * gcc.target/aarch64/arm_neon-nosimd-error.c: Delete. From-SVN: r226563
2015-08-04[AArch64][9/14] Implement TARGET_CAN_INLINE_PKyrylo Tkachov1-0/+110
* config/aarch64/aarch64.c (aarch64_tribools_ok_for_inlining_p): New function. (aarch64_can_inline_p): Likewise. (TARGET_CAN_INLINE_P): Define. From-SVN: r226561
2015-08-04[AArch64][8/14] Implement TARGET_OPTION_VALID_ATTRIBUTE_PKyrylo Tkachov2-0/+502
* common/config/aarch64/aarch64-common.c (aarch64_handle_option): Remove static. Handle OPT_mgeneral_regs_only, OPT_mfix_cortex_a53_835769, OPT_mstrict_align, OPT_momit_leaf_frame_pointer. * config/aarch64/aarch64.c: Include opts.h and diagnostic.h (aarch64_attr_opt_type): New enum. (aarch64_attribute_info): New struct. (aarch64_handle_attr_arch): New function. (aarch64_handle_attr_cpu): Likewise. (aarch64_handle_attr_tune): Likewise. (aarch64_handle_attr_isa_flags): Likewise. (aarch64_attributes): New table. (aarch64_process_one_target_attr): New function. (num_occurences_in_str): Likewise. (aarch64_process_target_attr): Likewise. (aarch64_option_valid_attribute_p): Likewise. (TARGET_OPTION_VALID_ATTRIBUTE_P): Define. * config/aarch64/aarch64-protos.h: Include input.h (aarch64_handle_option): Declare prototype. From-SVN: r226560
2015-08-04[AArch64][7/14] Implement TARGET_SET_CURRENT_FUNCTIONKyrylo Tkachov2-0/+59
* config/aarch64/aarch64.h (SWITCHABLE_TARGET): Define. * config/aarch64/aarch64.c: Include target-globals.h (aarch64_previous_fndecl): New variable. (aarch64_set_current_function): New function. (TARGET_SET_CURRENT_FUNCTION): Define. From-SVN: r226559
2015-08-04[AArch64][6/14] Implement TARGET_OPTION_SAVE/TARGET_OPTION_RESTOREKyrylo Tkachov4-59/+205
* config/aarch64/aarch64.opt (explicit_tune_core): New TargetVariable. (explicit_arch): Likewise. (x_aarch64_isa_flags): Likewise. (mgeneral-regs-only): Mark as Save. (mfix-cortex-a53-835769): Likewise. (mcmodel=): Likewise. (mstrict-align): Likewise. (momit-leaf-frame-pointer): Likewise. (mtls-dialect): Likewise. (master=): Likewise. * config/aarch64/aarch64.h (ASM_DECLARE_FUNCTION_NAME): Define. (aarch64_isa_flags): Remove extern declaration. * config/aarch64/aarch64.c (aarch64_validate_mcpu): Return a bool to indicate success or failure. (aarch64_validate_march): Likewise. (aarch64_validate_mtune): Likewise. (aarch64_isa_flags): Delete. (aarch64_override_options_internal): Access opts->x_aarch64_isa_flags instead of aarch64_isa_flags. (aarch64_get_tune_cpu): New function. (aarch64_get_arch): Likewise. (aarch64_override_options): Use above and set up explicit_tune_core and explicit_arch. (aarch64_print_extension): Move earlier in file. Add isa_flags argument and use that instead of the global aarch64_isa_flags. (aarch64_option_save): New function. (aarch64_option_restore): Likewise. (aarch64_option_print): Likewise. (aarch64_declare_function_name): Likewise. (aarch64_start_file): Delete. (TARGET_ASM_FILE_START): Do not define. (TARGET_OPTION_RESTORE, TARGET_OPTION_PRINT): Define. * config/aarch64/aarch64-protos.h (aarch64_declare_function_name): Declare prototype. From-SVN: r226558
2015-08-04[AArch64][5/14] Make flag_omit_leaf_frame_pointer intialize to 2. Define and ↵Kyrylo Tkachov1-1/+1
use TARGET_OMIT_LEAF_FRAME_POINTER * config/aarch64/aarch64.opt (momit-leaf-frame-pointer): Initialize flag_omit_leaf_frame_pointer to 2. From-SVN: r226557
2015-08-04[AArch64][4/14] Create TARGET_FIX_ERR_A53_835769 and use that instead of ↵Kyrylo Tkachov4-12/+17
aarch64_fix_a53_err835769 * config/aarch64/aarch64.h (TARGET_FIX_ERR_A53_835769_DEFAULT): Always define to 0 or 1. (TARGET_FIX_ERR_A53_835769): New macro. * config/aarch64/aarch64.c (aarch64_override_options_internal): Remove handling of opts->x_aarch64_fix_a53_err835769. (aarch64_madd_needs_nop): Check for TARGET_FIX_ERR_A53_835769 rather than aarch64_fix_a53_err835769. * config/aarch64/aarch64-elf-raw.h: Update for above changes. * config/aarch64/aarch64-linux.h: Likewise. From-SVN: r226556
2015-08-04i386.c (ix86_expand_int_movcc): Check result of ix86_expand_int_movcc as ↵Uros Bizjak1-1/+1
boolean. * config/i386/i386.c (ix86_expand_int_movcc): Check result of ix86_expand_int_movcc as boolean. From-SVN: r226555
2015-08-04[AArch64][3/14] Refactor option override codeKyrylo Tkachov2-145/+308
* config/aarch64/aarch64.opt (aarch64_arch_string): Delete. (aarch64_cpu_string): Likewise. (aarch64_tune_string): Likewise. * config/aarch64/aarch64.c (aarch64_parse_opt_result): New enum. (aarch64_parse_extension): Return aarch64_parse_opt_result. Add extra argument to put result into. (aarch64_parse_arch): Likewise. Do not set selected_cpu. (aarch64_parse_cpu): Add arguments to put results into. Return aarch64_parse_opt_result. (aarch64_parse_tune): Likewise. (aarch64_override_options_after_change_1): New function. (aarch64_override_options_internal): New function. (aarch64_validate_mcpu): Likewise. (aarch64_validate_march): Likewise. (aarch64_validate_mtune): Likewise. (aarch64_override_options): Update to reflect above changes. Move some logic into aarch64_override_options_internal. Initialize target_option_default_node and target_option_current_node. (aarch64_override_options_after_change): Move logic into aarch64_override_options_after_change_1 and call it with global_options. (initialize_aarch64_code_model): Take a gcc_options pointer and use the flag values from that. * gcc.target/aarch64/cpu-diagnostics-3.c: Update expected error message. From-SVN: r226554
2015-08-04[AArch64][2/14] Refactor arches handling, add arch enum identifierKyrylo Tkachov6-37/+56
* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_ARCH_8A directly rather than with cpp_define_formatted. * config/aarch64/aarch64.c (struct processor): Add arch field. (all_architectures): Handle above, move above all_cores. (all_cores): Handle above. (aarch64_parse_arch): Handle above changes. * config/aarch64/aarch64-arches.def (armv8-a): Extend according to above. Update comments. (armv8.1-a): Likewise. * config/aarch64/aarch64-cores.def: Update according to above. * config/aarch64/aarch64-opts.h (aarch64_arch): New enum. * config/aarch64/driver-aarch64.c (struct aarch64_arch): Rename to aarch64_arch_driver_info. From-SVN: r226553
2015-08-04[AArch64][1/14] Add ident field to struct processorKyrylo Tkachov1-8/+10
* config/aarch64/aarch64.c (struct processor): Add ident field. Rename core sched_core. (all_cores): Handle above changes. (all_architectures): Likewise. (aarch64_parse_arch): Likewise. (aarch64_override_options): Likewise. From-SVN: r226552
2015-08-03htm.md (tabort.): Restrict the source operand to using a base register.Peter Bergner1-1/+1
gcc/ * config/rs6000/htm.md (tabort.): Restrict the source operand to using a base register. gcc/testsuite/ * gcc.target/powerpc/htm-tabort-no-r0.c: New test. From-SVN: r226532
2015-08-03re PR target/67060 (FAIL: gcc.dg/pr56228.c (test for excess errors))John David Anglin1-6/+0
PR target/67060 * config/pa/pa.md (call_reg_64bit): Remove reg:DI 1 clobber. Adjust splits to match new pattern. From-SVN: r226522
2015-08-03vector.md (VEC_L): Add KFmode and TFmode.Michael Meissner7-16/+209
2015-08-03 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vector.md (VEC_L): Add KFmode and TFmode. (VEC_M): Likewise. (VEC_N): Likewise. (mov<mode>, VEC_M iterator): Add support for IEEE 128-bit floating point in VSX registers. * config/rs6000/constraints.md (wb constraint): Document unused w<x> constraint. (we constraint): Likewise. (wo constraint): Likewise. (wp constraint): New constraint for IEEE 128-bit floating point in VSX registers. (wq constraint): Likewise. * config/rs6000/predicates.md (easy_fp_constant): Add support for IEEE 128-bit floating point in VSX registers. (easy_scalar_constant): Likewise. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add new constraints (wp, wq) for IEEE 128-bit floating point in VSX registers. (rs6000_init_hard_regno_mode_ok): Likewise. * config/rs6000/vsx.md (VSX_LE_128): Add support for IEEE 128-bit floating point in VSX registers. (VSX_L): Likewise. (VSX_M): Likewise. (VSX_M2): Likewise. (VSm): Likewise. (VSs): Likewise. (VSr): Likewise. (VSa): Likewise. (VSv): Likewise. (vsx_le_permute_<mode>): Add support to properly swap bytes for IEEE 128-bit floating point in VSX registers on little endian. (vsx_le_undo_permute_<mode>): Likewise. (vsx_le_perm_load_<mode>): Likewise. (vsx_le_perm_store_<mode>): Likewise. (splitters for IEEE 128-bit fp moves): Likewise. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wp and wq constraints. * config/rs6000/altivec.md (VM): Add support for IEEE 128-bit floating point in VSX registers. (VM2): Likewise. * doc/md.text (Machine Constraints): Document wp and wq constraints on PowerPC. From-SVN: r226520
2015-08-03[ARM] PR target/66731 Fix vnmul insn with -frounding-mathSzabolcs Nagy2-1/+31
gcc: PR target/66731 * config/arm/vfp.md (negmuldf3_vfp): Add new pattern. (negmulsf3_vfp): Likewise. (muldf3negdf_vfp): Disable for -frounding-math. (mulsf3negsf_vfp): Likewise. * config/arm/arm.c (arm_new_rtx_costs): Fix NEG cost for VNMUL, fix MULT cost with -frounding-math. gcc/testsuite: PR target/66731 * gcc.target/arm/vnmul-1.c: New. * gcc.target/arm/vnmul-2.c: New. * gcc.target/arm/vnmul-3.c: New. * gcc.target/arm/vnmul-4.c: New. From-SVN: r226496
2015-08-02arm.md (*arm_smin_cmp): New pattern.Michael Collison1-0/+38
2015-08-01 Michael Collison <michael.collison@linaro.org Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> * gcc/config/arm/arm.md (*arm_smin_cmp): New pattern. (*arm_umin_cmp): Likewise. * gcc.target/arm/mincmp.c: New test. From-SVN: r226476
2015-07-31re PR target/67049 (sh64-elf: internal compiler error: in df_uses_record, at ↵Kaz Kojima1-1/+1
df-scan.c:3001) PR target/67049 * config/sh/sh.md (GOTaddr2picreg): Fix typo added with the last change. From-SVN: r226457
2015-07-31[ARM][2/3] Make if_neg_move and if_move_neg into insn_and_splitKyrylo Tkachov1-22/+38
* config/arm/arm.md (*if_neg_move): Convert to insn_and_split. Enable for TARGET_32BIT. (*if_move_neg): Likewise. From-SVN: r226447
2015-07-31m32r.c (m32r_attribute_identifier): New function.Nick Clifton1-0/+10
* config/m32r/m32r.c (m32r_attribute_identifier): New function. Returns true for __model__. (TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P): Define. From-SVN: r226445
2015-07-31re PR go/66870 (split stack issues on ppc64le and ppc64)Alan Modra1-0/+4
PR target/66870 * config/rs6000/rs6000.c (machine_function): Add split_stack_argp_used. (rs6000_emit_prologue): Set it. (rs6000_set_up_by_prologue): Specify r12 when split_stack_argp_used. From-SVN: r226443
2015-07-31Refactoring masked built-in decls to use proper mask type.Petr Murzin2-2134/+1919
gcc/ * config/i386/i386.c (bdesc_special_args): Convert mask type from signed to unsigned for masked builtins. (ix86_expand_args_builtin): Do not handle UINT_FTYPE_V2DF, UINT64_FTYPE_V2DF, UINT64_FTYPE_V4SF, V16QI_FTYPE_V8DI, V16HI_FTYPE_V16SI, V16SI_FTYPE_V16SI, V16SF_FTYPE_FLOAT, V8HI_FTYPE_V8DI, V8UHI_FTYPE_V8UHI, V8SI_FTYPE_V8DI, V8SF_FTYPE_V8DF, V8DI_FTYPE_INT64, V8DI_FTYPE_V4DI, V8DI_FTYPE_V8DI, V8DF_FTYPE_DOUBLE, V8DF_FTYPE_V8SI, V16SI_FTYPE_V16SI_V16SI, V16SF_FTYPE_V16SF_V16SI, V8DI_FTYPE_V8DI_V8DI, V8DF_FTYPE_V8DF_V8DI, V4SI_FTYPE_V4SF_V4SF, V4SF_FTYPE_V4SF_UINT64, V2UDI_FTYPE_V4USI_V4USI, V2DI_FTYPE_V2DF_V2DF, V2DF_FTYPE_V2DF_UINT64, V4UDI_FTYPE_V8USI_V8USI, QI_FTYPE_V8DI_V8DI, HI_FTYPE_V16SI_V16SI, HI_FTYPE_HI_INT, V16SF_FTYPE_V16SF_V16SF_V16SF, V16SF_FTYPE_V16SF_V16SI_V16SF, V16SF_FTYPE_V16SI_V16SF_HI, V16SF_FTYPE_V16SI_V16SF_V16SF, V16SI_FTYPE_V16SF_V16SI_HI, V8DI_FTYPE_V8SF_V8DI_QI, V8SF_FTYPE_V8DI_V8SF_QI, V8DI_FTYPE_PV4DI, V8DF_FTYPE_V8DI_V8DF_QI, V16SI_FTYPE_V16SI_V16SI_V16SI, V2DI_FTYPE_V2DI_V2DI_V2DI, V8DI_FTYPE_V8DF_V8DI_QI, V8DF_FTYPE_PV4DF, V8SI_FTYPE_V8SI_V8SI_V8SI, V8DF_FTYPE_V8DF_V8DF_V8DF, UINT_FTYPE_V4SF, V8DF_FTYPE_V8DF_V8DI_V8DF, V8DF_FTYPE_V8DI_V8DF_V8DF, V8DF_FTYPE_V8SF_V8DF_QI, V8DI_FTYPE_V8DI_V8DI_V8DI, V16SF_FTYPE_PV4SF, V8SF_FTYPE_V8DF_V8SF_QI, V8SI_FTYPE_V8DF_V8SI_QI, V16SI_FTYPE_PV4SI, V2DF_FTYPE_V2DF_V4SF_V2DF_QI, V4SF_FTYPE_V4SF_V2DF_V4SF_QI, V8DI_FTYPE_V8DI_SI_V8DI_V8DI, QI_FTYPE_V8DF_V8DF_INT_QI, HI_FTYPE_V16SF_V16SF_INT_HI, V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI, VOID_FTYPE_PDOUBLE_V2DF_QI, VOID_FTYPE_PFLOAT_V4SF_QI, V2DF_FTYPE_PCDOUBLE_V2DF_QI, V4SF_FTYPE_PCFLOAT_V4SF_QI. * config/i386/i386-builtin-types.def (V16QI_FTYPE_V16SI): Remove. (V8DF_FTYPE_V8SI): Ditto. (V8HI_FTYPE_V8DI): Ditto. (V8SI_FTYPE_V8DI): Ditto. (V8SF_FTYPE_V8DF): Ditto. (V8SF_FTYPE_V8DF_V8SF_QI): Ditto. (V16HI_FTYPE_V16SI): Ditto. (V16SF_FTYPE_V16HI): Ditto. (V16SF_FTYPE_V16HI_V16SF_HI): Ditto. (V16SF_FTYPE_V16SI): Ditto. (V4DI_FTYPE_V4DI): Ditto. (V16SI_FTYPE_V16SF): Ditto. (V16SF_FTYPE_FLOAT): Ditto. (V8DF_FTYPE_DOUBLE): Ditto. (V8DI_FTYPE_INT64): Ditto. (V8DI_FTYPE_V4DI): Ditto. (V16QI_FTYPE_V8DI): Ditto. (UINT_FTYPE_V4SF): Ditto. (UINT64_FTYPE_V4SF): Ditto. (UINT_FTYPE_V2DF): Ditto. (UINT64_FTYPE_V2DF): Ditto. (V16SI_FTYPE_V16SI): Ditto. (V8DI_FTYPE_V8DI): Ditto. (V16SI_FTYPE_PV4SI): Ditto. (V16SF_FTYPE_PV4SF): Ditto. (V8DI_FTYPE_PV2DI): Ditto. (V8DF_FTYPE_PV2DF): Ditto. (V4DI_FTYPE_PV2DI): Ditto. (V4DF_FTYPE_PV2DF): Ditto. (V16SI_FTYPE_PV2SI): Ditto. (V16SF_FTYPE_PV2SF): Ditto. (V8DI_FTYPE_PV4DI): Ditto. (V8DF_FTYPE_PV4DF): Ditto. (V8SF_FTYPE_FLOAT): Ditto. (V4SF_FTYPE_FLOAT): Ditto. (V4DF_FTYPE_DOUBLE): Ditto. (V8SF_FTYPE_PV4SF): Ditto. (V8SI_FTYPE_PV4SI): Ditto. (V4SI_FTYPE_PV2SI): Ditto. (V8SF_FTYPE_PV2SF): Ditto. (V8SI_FTYPE_PV2SI): Ditto. (V16SF_FTYPE_PV8SF): Ditto. (V16SI_FTYPE_PV8SI): Ditto. (V8DI_FTYPE_V8SF): Ditto. (V4DI_FTYPE_V4SF): Ditto. (V2DI_FTYPE_V4SF): Ditto. (V64QI_FTYPE_QI): Ditto. (V32HI_FTYPE_HI): Ditto. (V8UHI_FTYPE_V8UHI): Ditto. (V16UHI_FTYPE_V16UHI): Ditto. (V32UHI_FTYPE_V32UHI): Ditto. (V2UDI_FTYPE_V2UDI): Ditto. (V4UDI_FTYPE_V4UDI): Ditto. (V8UDI_FTYPE_V8UDI): Ditto. (V4USI_FTYPE_V4USI): Ditto. (V8USI_FTYPE_V8USI): Ditto. (V16USI_FTYPE_V16USI): Ditto. (V2DF_FTYPE_V2DF_UINT64): Ditto. (V2DI_FTYPE_V2DF_V2DF): Ditto. (V2UDI_FTYPE_V4USI_V4USI): Ditto. (V8DF_FTYPE_V8DF_V8DI): Ditto. (V4SF_FTYPE_V4SF_UINT64): Ditto. (V4SI_FTYPE_V4SF_V4SF): Ditto. (V16SF_FTYPE_V16SF_V16SI): Ditto. (V64QI_FTYPE_V32HI_V32HI): Ditto. (V32HI_FTYPE_V16SI_V16SI): Ditto. (V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI): Ditto. (V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI): Ditto. (V32HI_FTYPE_V64QI_V64QI): Ditto. (V32HI_FTYPE_V32HI_V32HI): Ditto. (V16HI_FTYPE_V16HI_V16HI_INT_V16HI_HI): Ditto. (V16SI_FTYPE_V16SI_V4SI): Ditto. (V16SI_FTYPE_V16SI_V16SI): Ditto. (V16SI_FTYPE_V32HI_V32HI): Ditto. (V16SI_FTYPE_V16SI_SI): Ditto. (V8DI_FTYPE_V8DI_V8DI): Ditto. (V4UDI_FTYPE_V8USI_V8USI): Ditto. (V8DI_FTYPE_V16SI_V16SI): Ditto. (V8DI_FTYPE_V8DI_V2DI): Ditto. (QI_FTYPE_QI): Ditto. (SI_FTYPE_SI): Ditto. (DI_FTYPE_DI): Ditto. (QI_FTYPE_QI_QI): Ditto. (QI_FTYPE_QI_INT): Ditto. (HI_FTYPE_HI_INT): Ditto. (SI_FTYPE_SI_INT): Ditto. (DI_FTYPE_DI_INT): Ditto. (HI_FTYPE_V16QI_V16QI): Ditto. (SI_FTYPE_V32QI_V32QI): Ditto. (DI_FTYPE_V64QI_V64QI): Ditto. (QI_FTYPE_V8HI_V8HI): Ditto. (HI_FTYPE_V16HI_V16HI): Ditto. (SI_FTYPE_V32HI_V32HI): Ditto. (QI_FTYPE_V4SI_V4SI): Ditto. (QI_FTYPE_V8SI_V8SI): Ditto. (QI_FTYPE_V2DI_V2DI): Ditto. (QI_FTYPE_V4DI_V4DI): Ditto. (QI_FTYPE_V8DI_V8DI): Ditto. (HI_FTYPE_V16SI_V16SI): Ditto. (HI_FTYPE_V16SI_V16SI_INT_HI): Ditto. (QI_FTYPE_V8DF_V8DF_INT_QI): Ditto. (HI_FTYPE_V16SF_V16SF_INT_HI): Ditto. (V32HI_FTYPE_V32HI_V32HI_V32HI): Ditto. (V4SF_FTYPE_V4SF_V2DF_V4SF_QI): Ditto. (V8DF_FTYPE_V8DF_V8DF_V8DF): Ditto. (V16SF_FTYPE_V16SF_V16SF_V16SF): Ditto. (V8DF_FTYPE_V8SF_V8DF_QI): Ditto. (V8DI_FTYPE_V8DF_V8DI_QI): Ditto. (V8DF_FTYPE_V8DI_V8DF_V8DF): Ditto. (V2DF_FTYPE_V2DF_V4SF_V2DF_QI): Ditto. (V16SF_FTYPE_V16SI_V16SF_HI): Ditto. (V16SF_FTYPE_V16SI_V16SF_V16SF): Ditto. (V8SI_FTYPE_V8DF_V8SI_QI): Ditto. (V8DI_FTYPE_PCCHAR_V8DI_QI): Ditto. (V8SF_FTYPE_PCFLOAT_V8SF_QI): Ditto. (V4SF_FTYPE_PCFLOAT_V4SF_QI): Ditto. (V4DF_FTYPE_PCDOUBLE_V4DF_QI): Ditto. (V2DF_FTYPE_PCDOUBLE_V2DF_QI): Ditto. (V8SI_FTYPE_PCCHAR_V8SI_QI): Ditto. (V4SI_FTYPE_PCCHAR_V4SI_QI): Ditto. (V4DI_FTYPE_PCCHAR_V4DI_QI): Ditto. (V2DI_FTYPE_PCCHAR_V2DI_QI): Ditto. (V16SF_FTYPE_PCV8SF_V16SF_HI): Ditto. (V16SI_FTYPE_PCV8SI_V16SI_HI): Ditto. (V8DF_FTYPE_PCV2DF_V8DF_QI): Ditto. (V8SF_FTYPE_PCV4SF_V8SF_QI): Ditto. (V8DI_FTYPE_PCV2DI_V8DI_QI): Ditto. (V8SI_FTYPE_PCV4SI_V8SI_QI): Ditto. (V4DF_FTYPE_PCV2DF_V4DF_QI): Ditto. (V4DI_FTYPE_PCV2DI_V4DI_QI): Ditto. (VOID_FTYPE_PDOUBLE_V2DF_QI): Ditto. (VOID_FTYPE_PFLOAT_V4SF_QI): Ditto. (V16SI_FTYPE_V16SF_V16SI_HI): Ditto. (V8DI_FTYPE_V8SF_V8DI_QI): Ditto. (V8SF_FTYPE_V8DI_V8SF_QI): Ditto. (V8DF_FTYPE_V8DI_V8DF_QI): Ditto. (V2DF_FTYPE_V2DF_V2DF_V2DI): Ditto. (V4SF_FTYPE_V4SF_V4SF_V4SI): Ditto. (V2UDI_FTYPE_V2UDI_V2UDI_V2UDI): Ditto. (V4USI_FTYPE_V4USI_V4USI_V4USI): Ditto. (V8UHI_FTYPE_V8UHI_V8UHI_V8UHI): Ditto. (V16UQI_FTYPE_V16UQI_V16UQI_V16UQI): Ditto. (V4DF_FTYPE_V4DF_V4DF_V4DI): Ditto. (V8SF_FTYPE_V8SF_V8SF_V8SI): Ditto. (V8DI_FTYPE_V8DI_V8DI_V8DI): Ditto. (V16SI_FTYPE_V16SI_V16SI_V16SI): Ditto. (V2DF_FTYPE_V2DF_V2DI_V2DF): Ditto. (V4DF_FTYPE_V4DF_V4DI_V4DF): Ditto. (V8DF_FTYPE_V8DF_V8DI_V8DF): Ditto. (V4SF_FTYPE_V4SF_V4SI_V4SF): Ditto. (V8SF_FTYPE_V8SF_V8SI_V8SF): Ditto. (V16SF_FTYPE_V16SF_V16SI_V16SF): Ditto. (V8DI_FTYPE_V8DI_SI_V8DI_V8DI): Ditto. (PVOID_FTYPE_PVOID_PVOID_ULONG): Ditto. (V4SF_FTYPE_V2DF_V4SF_QI): Convert mask type from signed to unsigned. (V4SF_FTYPE_V4DF_V4SF_QI): Ditto. (V4SF_FTYPE_V8HI_V4SF_QI): Ditto. (V8SF_FTYPE_V8HI_V8SF_QI): Ditto. (V16SI_FTYPE_V16SI_V16SI_HI): Ditto. (V8DI_FTYPE_V8DI_V8DI_QI): Ditto. (V2DF_FTYPE_V4DF_INT_V2DF_QI): Ditto. (V2DF_FTYPE_V8DF_INT_V2DF_QI): Ditto. (V2DI_FTYPE_V2DI_INT_V2DI_QI): Ditto. (V4DF_FTYPE_V8DF_INT_V4DF_QI): Ditto. (V4SF_FTYPE_V8SF_INT_V4SF_QI): Ditto. (V4SI_FTYPE_V2DF_V4SI_QI): Ditto. (V4SI_FTYPE_V4SI_INT_V4SI_QI): Ditto. (V4SI_FTYPE_V8HI_V8HI_V4SI_QI): Ditto. (V4SI_FTYPE_V8SI_INT_V4SI_QI): Ditto. (V8HI_FTYPE_V16QI_V16QI_V8HI_QI): Ditto. (V8HI_FTYPE_V8SF_INT_V8HI_QI): Ditto. (V8HI_FTYPE_V4SF_INT_V8HI_QI): Ditto. (V8SF_FTYPE_V16SF_INT_V8SF_QI): Ditto. (V4SF_FTYPE_V16SF_INT_V4SF_QI): Ditto. (V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI): Ditto. (V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI): Ditto. (V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI): Ditto. (V8DF_FTYPE_V8DF_INT_V8DF_QI): Ditto. (V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI): Ditto. (V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI): Ditto. (V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI): Ditto. (V16SF_FTYPE_V16SF_INT_V16SF_HI): Ditto. (V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI): Ditto. (V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI): Ditto. (V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI): Ditto. (V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI): Ditto. (V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI): Ditto. (V16HI_FTYPE_V32QI_V32QI_V16HI_HI): Ditto. (V32HI_FTYPE_V64QI_V64QI_V32HI_SI): Ditto. (V16HI_FTYPE_V16SF_INT_V16HI_HI): Ditto. (V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI): Ditto. (V4SI_FTYPE_V16SI_INT_V4SI_QI): Ditto. (V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI): Ditto. (V8SI_FTYPE_V16HI_V16HI_V8SI_QI): Ditto. (V16SI_FTYPE_V32HI_V32HI_V16SI_HI): Ditto. (V8SI_FTYPE_V8SI_INT_V8SI_QI): Ditto. (V8SI_FTYPE_V16SI_INT_V8SI_QI): Ditto. (V16SI_FTYPE_V16SI_V4SI_V16SI_HI): Ditto. (V16SI_FTYPE_V16SI_INT_V16SI_HI): Ditto. (V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI): Ditto. (V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI): Ditto. (V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI): Ditto. (V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI): Ditto. (V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI): Ditto. (V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI): Ditto. (V4DI_FTYPE_V8DI_INT_V4DI_QI): Ditto. (V8DI_FTYPE_V8DI_V2DI_V8DI_QI): Ditto. (V8DI_FTYPE_V8DI_INT_V8DI_QI): Ditto. (V4DI_FTYPE_V4DI_INT_V4DI_QI): Ditto. (V2DI_FTYPE_V4DI_INT_V2DI_QI): Ditto. (V2DI_FTYPE_V8DI_INT_V2DI_QI): Ditto. (HI_FTYPE_HI): Ditto. (HI_FTYPE_V16QI): Ditto. (SI_FTYPE_V32QI): Ditto. (DI_FTYPE_V64QI): Ditto. (QI_FTYPE_V8HI): Ditto. (HI_FTYPE_V16HI): Ditto. (SI_FTYPE_V32HI): Ditto. (QI_FTYPE_V4SI): Ditto. (QI_FTYPE_V8SI): Ditto. (HI_FTYPE_V16SI): Ditto. (QI_FTYPE_V2DI): Ditto. (QI_FTYPE_V4DI): Ditto. (QI_FTYPE_V8DI): Ditto. (V16QI_FTYPE_HI): Ditto. (V32QI_FTYPE_SI): Ditto. (V64QI_FTYPE_DI): Ditto. (V8HI_FTYPE_QI): Ditto. (V16HI_FTYPE_HI): Ditto. (V32HI_FTYPE_SI): Ditto. (V4SI_FTYPE_QI): Ditto. (V4SI_FTYPE_HI): Ditto. (V8SI_FTYPE_QI): Ditto. (V8SI_FTYPE_HI): Ditto. (V2DI_FTYPE_QI): Ditto. (V4DI_FTYPE_QI): Ditto. (HI_FTYPE_HI_HI): Ditto. (SI_FTYPE_SI_SI): Ditto. (DI_FTYPE_DI_DI): Ditto. (HI_FTYPE_V16QI_V16QI_HI): Ditto. (HI_FTYPE_V16QI_V16QI_INT_HI): Ditto. (SI_FTYPE_V32QI_V32QI_SI): Ditto. (SI_FTYPE_V32QI_V32QI_INT_SI): Ditto. (DI_FTYPE_V64QI_V64QI_DI): Ditto. (DI_FTYPE_V64QI_V64QI_INT_DI): Ditto. (QI_FTYPE_V8HI_V8HI_QI): Ditto. (QI_FTYPE_V8HI_V8HI_INT_QI): Ditto. (HI_FTYPE_V16HI_V16HI_HI): Ditto. (HI_FTYPE_V16HI_V16HI_INT_HI): Ditto. (SI_FTYPE_V32HI_V32HI_SI): Ditto. (SI_FTYPE_V32HI_V32HI_INT_SI): Ditto. (QI_FTYPE_V4SI_V4SI_QI): Ditto. (QI_FTYPE_V4SI_V4SI_INT_QI): Ditto. (QI_FTYPE_V8SI_V8SI_QI): Ditto. (QI_FTYPE_V8SI_V8SI_INT_QI): Ditto. (QI_FTYPE_V2DI_V2DI_QI): Ditto. (QI_FTYPE_V2DI_V2DI_INT_QI): Ditto. (QI_FTYPE_V4DI_V4DI_QI): Ditto. (QI_FTYPE_V4DI_V4DI_INT_QI): Ditto. (QI_FTYPE_V8DI_V8DI_QI): Ditto. (HI_FTYPE_V16SI_V16SI_HI): Ditto. (QI_FTYPE_V8DI_V8DI_INT): Ditto. (QI_FTYPE_V8DI_V8DI_INT_QI): Ditto. (HI_FTYPE_V16SI_V16SI_INT): Ditto. (HI_FTYPE_V16SI_V16SI_INT _HI): Ditto. (QI_FTYPE_V8DF_V8DF_INT): Ditto. (QI_FTYPE_V8DF_V8DF_INT_QI_INT): Ditto. (HI_FTYPE_V16SF_V16SF_INT): Ditto. (HI_FTYPE_V16SF_V16SF_INT_HI_INT): Ditto. (QI_FTYPE_V2DF_V2DF_INT): Ditto. (QI_FTYPE_V2DF_V2DF_INT_QI): Ditto. (QI_FTYPE_V2DF_V2DF_INT_QI_INT): Ditto. (QI_FTYPE_V4SF_V4SF_INT): Ditto. (QI_FTYPE_V4SF_V4SF_INT_QI): Ditto. (QI_FTYPE_V4SF_V4SF_INT_QI_INT): Ditto. (V16SI_FTYPE_HI): Ditto. (V8DI_FTYPE_QI): Ditto. (V2DF_FTYPE_V2DI_V2DF_V2DF_QI): Ditto. (V2DF_FTYPE_V2DF_V2DI_V2DF_QI): Ditto. (V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI): Ditto. (V4SF_FTYPE_V4SI_V4SF_V4SF_QI): Ditto. (V4SF_FTYPE_V4SF_V4SI_V4SF_QI): Ditto. (V4SF_FTYPE_V4SF_V4SF_V4SF_QI): Ditto. (V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI): Ditto. (V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI): Ditto. (V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI): Ditto. (V2DF_FTYPE_V2DF_V2DF_QI): Ditto. (V2DF_FTYPE_V4SF_V2DF_QI): Ditto. (V2DF_FTYPE_V4SI_V2DF_QI): Ditto. (V4DF_FTYPE_V4DF_V4DF_QI): Ditto. (V4DF_FTYPE_V4SF_V4DF_QI): Ditto. (V4DF_FTYPE_V4SI_V4DF_QI): Ditto. (V8DF_FTYPE_V8DF_V8DF_QI): Ditto. (V8DF_FTYPE_V8SI_V8DF_QI): Ditto. (V2DI_FTYPE_V4SI_V2DI_QI): Ditto. (V2DI_FTYPE_V8HI_V2DI_QI): Ditto. (V4DI_FTYPE_V4DF_V4DI_QI): Ditto. (V2DI_FTYPE_V2DF_V2DI_QI): Ditto. (V2DI_FTYPE_V2DI_V2DI_V2DI_QI): Ditto. (V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI): Ditto. (V4DI_FTYPE_V4DI_V4DI_V4DI_QI): Ditto. (V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI): Ditto. (V8DI_FTYPE_V8SI_V8DI_QI): Ditto. (V8DI_FTYPE_V8HI_V8DI_QI): Ditto. (V8DI_FTYPE_V16QI_V8DI_QI): Ditto. (V2DI_FTYPE_V16QI_V2DI_QI): Ditto. (V4DI_FTYPE_V16QI_V4DI_QI): Ditto. (V4DI_FTYPE_V4DI_V4DI_QI): Ditto. (V4DI_FTYPE_V4SI_V4DI_QI): Ditto. (V4DI_FTYPE_V8HI_V4DI_QI): Ditto. (V8DI_FTYPE_V8DI_V8DI_V8DI_QI): Ditto. (V8DF_FTYPE_V8DI_V8DF_V8DF_QI): Ditto. (V8DF_FTYPE_V8DF_V8DI_V8DF_QI): Ditto. (V4DF_FTYPE_V4DI_V4DF_V4DF_QI): Ditto. (V4DF_FTYPE_V4DF_V4DI_V4DF_QI): Ditto. (V4DF_FTYPE_V4DF_V4DF_V4DF_QI): Ditto. (V8DF_FTYPE_V8DF_V8DF_V8DF_QI): Ditto. (V16QI_FTYPE_V16QI_V16QI_V16QI_HI): Ditto. (V16HI_FTYPE_V16HI_V16HI_V16HI_HI): Ditto. (V16SI_FTYPE_V16SI_V16SI_V16SI_HI): Ditto. (V2DF_FTYPE_V2DF_V2DF_V2DF_QI): Ditto. (V32HI_FTYPE_V32HI_V32HI_V32HI_SI): Ditto. (V64QI_FTYPE_V64QI_V64QI_V64QI_DI): Ditto. (V32QI_FTYPE_V32QI_V32QI_V32QI_SI): Ditto. (V8HI_FTYPE_V8HI_V8HI_V8HI_QI): Ditto. (V4SF_FTYPE_V4SF_V4SF_QI): Ditto. (V4SF_FTYPE_V4SI_V4SF_QI): Ditto. (V8SF_FTYPE_V8SF_V8SF_QI): Ditto. (V8SF_FTYPE_V8SI_V8SF_QI): Ditto. (V16SF_FTYPE_V16SF_V16SF_HI): Ditto. (V4SI_FTYPE_V16QI_V4SI_QI): Ditto. (V4SI_FTYPE_V8HI_V4SI_QI): Ditto. (V8SI_FTYPE_V8SI_V8SI_QI): Ditto. (V8SI_FTYPE_V8HI_V8SI_QI): Ditto. (V8SI_FTYPE_V16QI_V8SI_QI): Ditto. (V4SI_FTYPE_V4SI_V4SI_V4SI_QI): Ditto. (V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI): Ditto. (V8SF_FTYPE_V8SF_V8SF_V8SF_QI): Ditto. (V8SF_FTYPE_V8SI_V8SF_V8SF_QI): Ditto. (V8SF_FTYPE_V8SF_V8SI_V8SF_QI): Ditto. (V8SI_FTYPE_V8SI_V8SI_V8SI_QI): Ditto. (V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI): Ditto. (V16SF_FTYPE_V16SF_V16SF_V16SF_HI): Ditto. (V16SF_FTYPE_V16SI_V16SF_V16SF_HI): Ditto. (V16SF_FTYPE_V16SF_V16SI_V16SF_HI): Ditto. (V16SF_FTYPE_V8SF_V16SF_HI): Ditto. (V16SF_FTYPE_V4SF_V16SF_HI): Ditto. (V8DF_FTYPE_V4DF_V8DF_QI): Ditto. (V8DF_FTYPE_V2DF_V8DF_QI): Ditto. (V16SI_FTYPE_V8SI_V16SI_HI): Ditto. (V16SI_FTYPE_V4SI_V16SI_HI): Ditto. (V16SI_FTYPE_SI_V16SI_HI): Ditto. (V16SI_FTYPE_V16HI_V16SI_HI): Ditto. (V16SI_FTYPE_V16QI_V16SI_HI): Ditto. (V8DI_FTYPE_V4DI_V8DI_QI): Ditto. (V4SI_FTYPE_V4DF_V4SI_QI): Ditto. (V8DI_FTYPE_V2DI_V8DI_QI): Ditto. (V8DI_FTYPE_DI_V8DI_QI): Ditto. (V16QI_FTYPE_V16SI_V16QI_HI): Ditto. (V16QI_FTYPE_V8DI_V16QI_QI): Ditto. (V32HI_FTYPE_V32HI_V32HI_SI): Ditto. (V32HI_FTYPE_V32QI_V32HI_SI): Ditto. (V16HI_FTYPE_V16HI_V16HI_HI): Ditto. (V16HI_FTYPE_V16QI_V16HI_HI): Ditto. (V8HI_FTYPE_V16QI_V8HI_QI): Ditto. (V8SF_FTYPE_V4SF_V8SF_QI): Ditto. (V4DF_FTYPE_V2DF_V4DF_QI): Ditto. (V8SI_FTYPE_V4SI_V8SI_QI): Ditto. (V8SI_FTYPE_SI_V8SI_QI): Ditto. (V4SI_FTYPE_V4SI_V4SI_QI): Ditto. (V4SI_FTYPE_SI_V4SI_QI): Ditto. (V4DI_FTYPE_V2DI_V4DI_QI): Ditto. (V4DI_FTYPE_DI_V4DI_QI): Ditto. (V2DI_FTYPE_V2DI_V2DI_QI): Ditto. (V2DI_FTYPE_DI_V2DI_QI): Ditto. (V64QI_FTYPE_V64QI_V64QI_DI): Ditto. (V64QI_FTYPE_V16QI_V64QI_DI): Ditto. (V64QI_FTYPE_QI_V64QI_DI): Ditto. (V32QI_FTYPE_V32QI_V32QI_SI): Ditto. (V32QI_FTYPE_V16QI_V32QI_SI): Ditto. (V32QI_FTYPE_QI_V32QI_SI): Ditto. (V16QI_FTYPE_V16QI_V16QI_HI): Ditto. (V16QI_FTYPE_QI_V16QI_HI): Ditto. (V32HI_FTYPE_V8HI_V32HI_SI): Ditto. (V32HI_FTYPE_HI_V32HI_SI): Ditto. (V16HI_FTYPE_V8HI_V16HI_HI): Ditto. (V16HI_FTYPE_HI_V16HI_HI): Ditto. (V8HI_FTYPE_V8HI_V8HI_QI): Ditto. (V8HI_FTYPE_HI_V8HI_QI): Ditto. (V64QI_FTYPE_PCV64QI_V64QI_DI): Ditto. (V32HI_FTYPE_PCV32HI_V32HI_SI): Ditto. (V32QI_FTYPE_PCV32QI_V32QI_SI): Ditto. (V16SF_FTYPE_PCV16SF_V16SF_HI): Ditto. (V8DF_FTYPE_PCV8DF_V8DF_QI): Ditto. (V16SI_FTYPE_PCV16SI_V16SI_HI): Ditto. (V16HI_FTYPE_PCV16HI_V16HI_HI): Ditto. (V16QI_FTYPE_PCV16QI_V16QI_HI): Ditto. (V8SF_FTYPE_PCV8SF_V8SF_QI): Ditto. (V8DI_FTYPE_PCV8DI_V8DI_QI): Ditto. (V8SI_FTYPE_PCV8SI_V8SI_QI): Ditto. (V8HI_FTYPE_PCV8HI_V8HI_QI): Ditto. (V4DF_FTYPE_PCV4DF_V4DF_QI): Ditto. (V4SF_FTYPE_PCV4SF_V4SF_QI): Ditto. (V4DI_FTYPE_PCV4DI_V4DI_QI): Ditto. (V4SI_FTYPE_PCV4SI_V4SI_QI): Ditto. (V2DF_FTYPE_PCV2DF_V2DF_QI): Ditto. (V2DI_FTYPE_PCV2DI_V2DI_QI): Ditto. (V16HI_FTYPE_V16SI_V16HI_HI): Ditto. (V8SI_FTYPE_V8DI_V8SI_QI): Ditto. (V8HI_FTYPE_V8DI_V8HI_QI): Ditto. (V16QI_FTYPE_V8HI_V16QI_QI): Ditto. (V16QI_FTYPE_V16HI_V16QI_HI): Ditto. (V16QI_FTYPE_V4SI_V16QI_QI): Ditto. (V16QI_FTYPE_V8SI_V16QI_QI): Ditto. (V8HI_FTYPE_V4SI_V8HI_QI): Ditto. (V8HI_FTYPE_V8SI_V8HI_QI): Ditto. (V16QI_FTYPE_V2DI_V16QI_QI): Ditto. (V16QI_FTYPE_V4DI_V16QI_QI): Ditto. (V8HI_FTYPE_V2DI_V8HI_QI): Ditto. (V8HI_FTYPE_V4DI_V8HI_QI): Ditto. (V4SI_FTYPE_V2DI_V4SI_QI): Ditto. (V4SI_FTYPE_V4DI_V4SI_QI): Ditto. (V32QI_FTYPE_V32HI_V32QI_SI): Ditto. (V2DF_FTYPE_V2DF_INT_V2DF_QI): Ditto. (V4DF_FTYPE_V4DF_INT_V4DF_QI): Ditto. (V4SF_FTYPE_V4SF_INT_V4SF_QI): Ditto. (V8SF_FTYPE_V8SF_INT_V8SF_QI): Ditto. (V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI): Ditto. (V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI): Ditto. (V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI): Ditto. (V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI): Ditto. (VOID_FTYPE_PV8DF_V8DF_QI): Ditto. (VOID_FTYPE_PV8SI_V8DI_QI): Ditto. (VOID_FTYPE_PV8HI_V8DI_QI): Ditto. (VOID_FTYPE_PV8HI_V4DI_QI): Ditto. (VOID_FTYPE_PV8HI_V2DI_QI): Ditto. (VOID_FTYPE_PV4SI_V4DI_QI): Ditto. (VOID_FTYPE_PV4SI_V2DI_QI): Ditto. (VOID_FTYPE_PV8HI_V8SI_QI): Ditto. (VOID_FTYPE_PV8HI_V4SI_QI): Ditto. (VOID_FTYPE_PV4DF_V4DF_QI): Ditto. (VOID_FTYPE_PV2DF_V2DF_QI): Ditto. (VOID_FTYPE_PV16SF_V16SF_HI): Ditto. (VOID_FTYPE_PV8SF_V8SF_QI): Ditto. (VOID_FTYPE_PV4SF_V4SF_QI): Ditto. (VOID_FTYPE_PV8DI_V8DI_QI): Ditto. (VOID_FTYPE_PV4DI_V4DI_QI): Ditto. (VOID_FTYPE_PV2DI_V2DI_QI): Ditto. (VOID_FTYPE_PV16SI_V16SI_HI): Ditto. (VOID_FTYPE_PV16HI_V16SI_HI): Ditto. (VOID_FTYPE_PV16QI_V16SI_HI): Ditto. (VOID_FTYPE_PV16QI_V8SI_QI): Ditto. (VOID_FTYPE_PV16QI_V4SI_QI): Ditto. (VOID_FTYPE_PV16QI_V8DI_QI): Ditto. (VOID_FTYPE_PV16QI_V4DI_QI): Ditto. (VOID_FTYPE_PV16QI_V2DI_QI): Ditto. (VOID_FTYPE_PV8SI_V8SI_QI): Ditto. (VOID_FTYPE_PV4SI_V4SI_QI): Ditto. (VOID_FTYPE_PV32HI_V32HI_SI): Ditto. (VOID_FTYPE_PV16HI_V16HI_HI): Ditto. (VOID_FTYPE_PV8HI_V8HI_QI): Ditto. (VOID_FTYPE_PV64QI_V64QI_DI): Ditto. (VOID_FTYPE_PV32QI_V32QI_SI): Ditto. (VOID_FTYPE_PV16QI_V16QI_HI): Ditto. (V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI): Ditto. (V8SI_FTYPE_V8SF_V8SI_QI): Ditto. (V4SI_FTYPE_V4SF_V4SI_QI): Ditto. (V4DI_FTYPE_V4SF_V4DI_QI): Ditto. (V2DI_FTYPE_V4SF_V2DI_QI): Ditto. (V4SF_FTYPE_V4DI_V4SF_QI): Ditto. (V4SF_FTYPE_V2DI_V4SF_QI): Ditto. (V4DF_FTYPE_V4DI_V4DF_QI): Ditto. (V2DF_FTYPE_V2DI_V2DF_QI): Ditto. (V32HI_FTYPE_V32HI_INT_V32HI_SI): Ditto. (V32HI_FTYPE_V32HI_V8HI_V32HI_SI): Ditto. (V16HI_FTYPE_V16HI_INT_V16HI_HI): Ditto. (V16HI_FTYPE_V16HI_V8HI_V16HI_HI): Ditto. (V8HI_FTYPE_V8HI_INT_V8HI_QI): Ditto. (V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI): Ditto. (V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI): Ditto. (V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI): Ditto. (V64QI_FTYPE_V32HI_V32HI_V64QI_DI): Ditto. (V32QI_FTYPE_V16HI_V16HI_V32QI_SI): Ditto. (V16QI_FTYPE_V8HI_V8HI_V16QI_HI): Ditto. (V32HI_FTYPE_V16SI_V16SI_V32HI_SI): Ditto. (V16HI_FTYPE_V8SI_V8SI_V16HI_HI): Ditto. (V8HI_FTYPE_V4SI_V4SI_V8HI_QI): Ditto. (V8DI_FTYPE_V16SI_V16SI_V8DI_QI): Ditto. (V4DI_FTYPE_V8SI_V8SI_V4DI_QI): Ditto. (V2DI_FTYPE_V4SI_V4SI_V2DI_QI): Ditto. (V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI): Ditto. (V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI): Ditto. (V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI): Ditto. (V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI): Ditto. (V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI): Ditto. (V8SI_FTYPE_V8SI_V4SI_V8SI_QI): Ditto. (V4DI_FTYPE_V4DI_V2DI_V4DI_QI): Ditto. (QI_FTYPE_V4DF_V4DF_INT_QI): Ditto. (QI_FTYPE_V8SF_V8SF_INT_QI): Ditto. (QI_FTYPE_V8DF_INT_QI): Ditto. (QI_FTYPE_V4DF_INT_QI): Ditto. (QI_FTYPE_V2DF_INT_QI): Ditto. (HI_FTYPE_V16SF_INT_HI): Ditto. (QI_FTYPE_V8SF_INT_QI): Ditto. (QI_FTYPE_V4SF_INT_QI): Ditto. (V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT): Ditto. From-SVN: r226431
2015-07-31[V850] Hookize LIBCALL_VALUEAnatoly Sokolov3-8/+14
From-SVN: r226418
2015-07-30[AArch64] Removed unused VRL2/3/4 iterator valuesAlan Lawrence1-12/+3
* config/aarch64/iterators.md (VRL2, VRL3, VRL4): Remove values for 128-bit vector modes. From-SVN: r226408
2015-07-30aarch64-simd.md (aarch64_ext<mode>): Replace call to GET_MODE_SIZE ↵David Sherwood7-25/+22
(GET_MODE_INNER (m)) with GET_MODE_UNIT_SIZE (m). gcc/ 2015-07-30 David Sherwood <david.sherwood@arm.com> * config/aarch64/aarch64-simd.md (aarch64_ext<mode>): Replace call to GET_MODE_SIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_SIZE (m). * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Likewise. * config/arm/arm.c (neon_valid_immediate): Likewise. * config/i386/i386.c (classify_argument, ix86_expand_int_vcond) (expand_vec_perm_blend, expand_vec_perm_pshufb): Likewise. (expand_vec_perm_pshufb2, expand_vec_perm_vpshufb2_vpermq): Likewise. (expand_vec_perm_vpshufb2_vpermq): Likewise. (expand_vec_perm_vpshufb2_vpermq_even_odd): Likewise. (expand_vec_perm_vpshufb4_vpermq2): Likewise. * config/i386/sse.md (<extract_type>_vinsert<shuffletype><extract_suf>_mask): Likewise. (*ssse3_palignr<mode>_perm): Likewise. * config/rs6000/rs6000.c (rs6000_complex_function_value): Likewise. * config/spu/spu.c (arith_immediate_p): Likewise. * simplify-rtx.c (simplify_const_unary_operation): Likewise. (simplify_binary_operation_1, simplify_ternary_operation): Likewise. From-SVN: r226403
2015-07-30re PR target/66217 (PowerPC rotate/shift/mask instructions not optimal)Segher Boessenkool1-16/+19
PR target/66217 PR target/67045 * config/rs6000/rs6000.md (and<mode>3): Put a CONST_INT_P check around those cases that need one. From-SVN: r226378
2015-07-29Define DBX_REGISTER_NUMBER for IA MCUH.J. Lu1-0/+11
Since IA MCU uses the same debug register map as Linux/x86, we copy DBX_REGISTER_NUMBER together with TARGET_ASM_FILE_START_FILE_DIRECTIVE and ASM_COMMENT_START from i386/gnu-user.h to i386/iamcu.h. * config/i386/iamcu.h (TARGET_ASM_FILE_START_FILE_DIRECTIVE): New. Copied from config/i386/gnu-user.h. (ASM_COMMENT_START): Likewise. (DBX_REGISTER_NUMBER): Likewise. From-SVN: r226363
2015-07-29[AArch64] Add basic FP16 supportAlan Lawrence6-4/+119
gcc/: * config/aarch64/aarch64-builtins.c (aarch64_fp16_type_node): New. (aarch64_init_builtins): Make aarch64_fp16_type_node, use for __fp16. * config/aarch64/aarch64-modes.def: Add HFmode. * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_FP16_FORMAT_IEEE and __ARM_FP16_ARGS. Set bit 1 of __ARM_FP. * config/aarch64/aarch64.c (aarch64_init_libfuncs, aarch64_promoted_type): New. (aarch64_float_const_representable_p): Disable HFmode. (aarch64_mangle_type): Mangle half-precision floats to "Dh". (TARGET_PROMOTED_TYPE): Define to aarch64_promoted_type. (TARGET_INIT_LIBFUNCS): Define to aarch64_init_libfuncs. * config/aarch64/aarch64.md (mov<mode>): Include HFmode using GPF_F16. (movhf_aarch64, extendhfsf2, extendhfdf2, truncsfhf2, truncdfhf2): New. * config/aarch64/iterators.md (GPF_F16): New. gcc/testsuite/: * gcc.target/aarch64/f16_movs_1.c: New test. From-SVN: r226346
2015-07-28arm.c (neon_element_bits, [...]): Call GET_MODE_INNER unconditionally.David Sherwood3-18/+10
gcc/ 2015-07-28 David Sherwood <david.sherwood@arm.com> * config/arm/arm.c (neon_element_bits, neon_valid_immediate): Call GET_MODE_INNER unconditionally. * config/spu/spu.c (arith_immediate_p): Likewise. * config/i386/i386.c (ix86_build_signbit_mask): Likewise. * expmed.c (synth_mult): Remove check for VOIDmode result from GET_MODE_INNER. (expand_mult_const): Likewise. * fold-const.c (fold_binary_loc): Replace call to element_precision with call to GET_MODE_PRECISION. * genmodes.c (emit_mode_inner_inline): Replace void_mode->name with m->name. (emit_mode_inner): Likewise. * lto-streamer-out.c (lto_write_mode_table): Update GET_MODE_INNER result check. * machmode.h (GET_MODE_UNIT_SIZE): Simplify. (GET_MODE_UNIT_PRECISION): Likewise. * rtlanal.c (subreg_get_info): Call GET_MODE_INNER unconditionally. * simplify-rtx.c (simplify_immed_subreg): Likewise. * stor-layout.c (bitwise_type_for_mode): Update assert. (element_precision): Remove. From-SVN: r226328
2015-07-28fr30.md (indirect_jump): Use pmode_register_operand instead of ↵Richard Sandiford1-2/+2
nonimmediate_operand. gcc/ * config/fr30/fr30.md (indirect_jump): Use pmode_register_operand instead of nonimmediate_operand. Remove C condiition. From-SVN: r226320
2015-07-28[AArch64] Properly handle simple arith+extend ops in rtx costsKyrylo Tkachov1-2/+9
* config/aarch64/aarch64.c (aarch64_rtx_arith_op_extract_p): Handle simple SIGN_EXTEND or ZERO_EXTEND. (aarch64_rtx_costs): Properly strip extend or extract before passing down to rtx costs again. From-SVN: r226309
2015-07-28rl78.c (rl78_addsi3_internal): New function.Nick Clifton3-4/+32
* config/rl78/rl78.c (rl78_addsi3_internal): New function. Optimizes the case where -mes0 is active and a constant symbolic address is used. * config/rl78/rl78-protos.h: Prototype the new function. * config/rl78/rl78.md (addsi3_internal_real): Call new function. From-SVN: r226306
2015-07-27[PATCH][AArch64] Improve spill code - swap order in shr patternsWilco Dijkstra1-13/+14
gcc/ * gcc/config/aarch64/aarch64.md (aarch64_lshr_sisd_or_int_<mode>3): Place integer variant first. (aarch64_ashr_sisd_or_int_<mode>3): Likewise. From-SVN: r226253
2015-07-27[ARM] PR/63870 Add a __builtin_lane_checkAlan Lawrence1-4/+34
* config/arm/arm-builtins.c (enum arm_builtins): Add ARM_BUILTIN_NEON_BASE and ARM_BUILTIN_NEON_LANE_CHECK. (ARM_BUILTIN_NEON_BASE): Rename macro to.... (ARM_BUILTIN_NEON_PATTERN_START): ...this. (arm_init_neon_builtins): Register __builtin_arm_lane_check. (arm_expand_neon_builtin): Handle ARM_BUILTIN_NEON_LANE_CHECK. From-SVN: r226252
2015-07-27[ARM] PR/63870 Add qualifier to check lane bounds in expandAlan Lawrence5-91/+101
* config/arm/arm-builtins.c (enum arm_type_qualifiers): Add qualifier_lane_index. (arm_binop_imm_qualifiers, BINOP_IMM_QUALIFIERS): New. (arm_getlane_qualifiers): Use qualifier_lane_index. (arm_lanemac_qualifiers): Rename to... (arm_mac_n_qualifiers): ...this. (LANEMAC_QUALIFIERS): Rename to... (MAC_N_QUALIFIERS): ...this. (arm_mac_lane_qualifiers, MAC_LANE_QUALIFIERS): New. (arm_setlane_qualifiers): Use qualifier_lane_index. (arm_ternop_imm_qualifiers, TERNOP_IMM_QUALIFIERS): New. (enum builtin_arg): Add NEON_ARG_LANE_INDEX. (arm_expand_neon_args): Handle NEON_ARG_LANE_INDEX. (arm_expand_neon_builtin): Handle qualifier_lane_index. * config/arm/arm-protos.h (neon_lane_bounds): Add const_tree parameter. * config/arm/arm.c (bounds_check): Likewise, improve error message. (neon_lane_bounds, neon_const_bounds): Add arguments to bounds_check. * config/arm/arm_neon_builtins.def (vshrs_n, vshru_n, vrshrs_n, vrshru_n, vshrn_n, vrshrn_n, vqshrns_n, vqshrnu_n, vqrshrns_n, vqrshrnu_n, vqshrun_n, vqrshrun_n, vshl_n, vqshl_s_n, vqshl_u_n, vqshlu_n, vshlls_n, vshllu_n): Change qualifiers to BINOP_IMM. (vsras_n, vsrau_n, vrsras_n, vrsrau_n, vsri_n, vsli_n): Change qualifiers to TERNOP_IMM. (vdup_lane): Change qualifiers to GETLANE. (vmla_lane, vmlals_lane, vmlalu_lane, vqdmlal_lane, vmls_lane, vmlsls_lane, vmlslu_lane, vqdmlsl_lane): Change qualifiers to MAC_LANE. (vmla_n, vmlals_n, vmlalu_n, vqdmlal_n, vmls_n, vmlsls_n, vmlslu_n, vqdmlsl_n): Change qualifiers to MAC_N. * config/arm/neon.md (neon_vget_lane<mode>, neon_vget_laneu<mode>, neon_vget_lanedi, neon_vget_lanev2di, neon_vset_lane<mode>, neon_vset_lanedi, neon_vdup_lane<mode>, neon_vdup_lanedi, neon_vdup_lanev2di, neon_vmul_lane<mode>, neon_vmul_lane<mode>, neon_vmull<sup>_lane<mode>, neon_vqdmull_lane<mode>, neon_vq<r>dmulh_lane<mode>, neon_vq<r>dmulh_lane<mode>, neon_vmla_lane<mode>, neon_vmla_lane<mode>, neon_vmlal<sup>_lane<mode>, neon_vqdmlal_lane<mode>, neon_vmls_lane<mode>, neon_vmls_lane<mode>, neon_vmlsl<sup>_lane<mode>, neon_vqdmlsl_lane<mode>): Remove call to neon_lane_bounds. From-SVN: r226251
2015-07-27[PATCH][AArch64] Improve spill code - swap order in shl patternWilco Dijkstra1-7/+7
gcc/ * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3): Place integer variant first. From-SVN: r226247
2015-07-27arm-arches.def: Add "armv6kz".Matthew Wahab8-19/+39
2015-07-27 Matthew Wahab <matthew.wahab@arm.com> * config/arm/arm-arches.def: Add "armv6kz". Replace 6ZK with 6KZ and FL_FOR_ARCH6ZK with FL_FOR_ARCH6KZ. * config/arm/arm-c.c (arm_cpu_builtins): Emit "__ARM_ARCH_6ZK__" for armv6kz targets. * config/arm/arm-cores.def: Replace 6ZK with 6KZ. * config/arm/arm-protos.h (FL_ARCH6KZ): New. (FL_FOR_ARCH6ZK): Remove. (FL_FOR_ARCH6KZ): New. (arm_arch6zk): New declaration. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.c (arm_arch6kz): New. (arm_option_override): Set arm_arch6kz. * config/arm/arm.h (BASE_ARCH_6ZK): Rename to BASE_ARCH_6KZ. * config/arm/driver-arm.c: Add comment to "armv6zk" entry. * doc/invoke.texi: Replace "armv6zk" with "armv6kz". From-SVN: r226243
2015-07-26alpha.c: Use SUBREG_P predicate.Uros Bizjak2-8/+8
* config/alpha/alpha.c: Use SUBREG_P predicate. * config/alpha/predicates.md: Ditto. From-SVN: r226232
2015-07-25re PR target/66930 (gengtype.c is miscompiled during stage2)Oleg Endo1-0/+1
gcc/ PR target/66930 * config/sh/sh.c (sh_split_movrt_negc_to_movt_xor): Add missing T bit register modified_between_p check. From-SVN: r226218
2015-07-25i386.c: Use SUBREG_P predicate.Uros Bizjak4-33/+33
* config/i386/i386.c: Use SUBREG_P predicate. * config/i386/i386.md: Ditto. * config/i386/sse.md: Ditto. * config/i386/predicates.md: Ditto. From-SVN: r226216
2015-07-25re PR target/67004 (valgrind error in recog_memoized & shorten_branches)Uros Bizjak1-5/+6
PR target/67004 * config/i386/i386.h (ADJUST_INSN_LENGTH): Use NONDEBUG_INSN_P (INSN) predicate and INSN_CODE (INSN) >= 0 to check for valid instruction. From-SVN: r226215
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