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2020-01-15i386: Fix wrong-code x86 issue with avx512{f,vl} fma PR93009Jakub Jelinek1-16/+16
As mentioned in the PR, the following testcase is miscompiled with avx512vl. The reason is that the fma *_bcst_1 define_insns have two alternatives: "=v,v" "0,v" "v,0" "m,m" and use the same vfmadd213* %3<avx512bcst>, %2, %0<sd_mask_op4> pattern. If the first alternative is chosen, everything is ok, but if the second alternative is chosen, %2 and %0 are the same register, so instead of doing dest=dest*another+membcst we do dest=dest*dest+membcst. Now, to fix this, either we'd need separate: "vfmadd213<ssemodesuffix>\t{%3<avx512bcst>, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<avx512bcst>} vfmadd213<ssemodesuffix>\t{%3<avx512bcst>, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %3<avx512bcst>}" where for the second alternative, we'd just use %1 instead of %2, but what I think is actually cleaner is just use a single alternative and make the two multiplication operands commutative, which they really are. 2020-01-15 Jakub Jelinek <jakub@redhat.com> PR target/93009 * config/i386/sse.md (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1, *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1, *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1, *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use just a single alternative instead of two, make operands 1 and 2 commutative. * gcc.target/i386/avx512vl-pr93009.c: New test.
2020-01-14PR target/93254 - -msse generates sse2 instructionsUros Bizjak1-1/+1
* config/i386/i386.md (*movsf_internal): Require SSE2 ISA for alternatives 9 and 10.
2020-01-13Add initial octeontx2 support.Andrew Pinski2-1/+11
This adds octeontx2 naming. It currently uses the cortexa57 cost model and schedule model until I submit this. This is more a place holder to get the naming of the cores in GCC 10. I will submit the cost model in the next couple of days. ChangeLog: * config/aarch64/aarch64-cores.def (octeontx2): New define. (octeontx2t98): New define. (octeontx2t96): New define. (octeontx2t93): New define. (octeontx2f95): New define. (octeontx2f95n): New define. (octeontx2f95mm): New define. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (-mcpu=): Document the new cpu types.
2020-01-10aarch64.c (aarch64_invalid_conversion): New function for target hook.Stam Markianos-Wright1-0/+58
gcc/ChangeLog: 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function for target hook. (aarch64_invalid_unary_op): New function for target hook. (aarch64_invalid_binary_op): New function for target hook. gcc/testsuite/ChangeLog: 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> * g++.target/aarch64/bfloat_cpp_typecheck.C: New test. * gcc.target/aarch64/bfloat16_scalar_typecheck.c: New test. * gcc.target/aarch64/bfloat16_vector_typecheck_1.c: New test. * gcc.target/aarch64/bfloat16_vector_typecheck_2.c: New test. From-SVN: r280130
2020-01-10config.gcc: Add arm_bf16.h.Stam Markianos-Wright10-45/+164
2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> * config.gcc: Add arm_bf16.h. * config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type): Add BFmode. (aarch64_init_simd_builtin_types): Define element types for vector types. (aarch64_init_bf16_types): New function. (aarch64_general_init_builtins): Add arm_init_bf16_types function call. * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector modes. * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types. * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move patterns. * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF. (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF. * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Add support for BF types. (aarch64_gimplify_va_arg_expr): Add support for BF types. (aarch64_vq_mode): Add support for BF types. (aarch64_simd_container_mode): Add support for BF types. (aarch64_mangle_type): Add support for BF scalar type. * config/aarch64/aarch64.md: Add BFmode to movhf pattern. * config/aarch64/arm_bf16.h: New file. * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types. * config/aarch64/iterators.md: Add BF types to mode attributes. (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New. 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> * g++.dg/abi/mangle-neon-aarch64.C: Add Bfloat SIMD types to test. * g++.dg/ext/arm-bf16/bf16-mangle-aarch64-1.C: New test. * gcc.target/aarch64/bfloat16_scalar_1.c: New test. * gcc.target/aarch64/bfloat16_scalar_2.c: New test. * gcc.target/aarch64/bfloat16_scalar_3.c: New test. * gcc.target/aarch64/bfloat16_scalar_4.c: New test. * gcc.target/aarch64/bfloat16_simd_1.c: New test. * gcc.target/aarch64/bfloat16_simd_2.c: New test. * gcc.target/aarch64/bfloat16_simd_3.c: New test. From-SVN: r280129
2020-01-10[AArch64] Make -msve-vector-bits=128 generate VL-specific codeRichard Sandiford2-9/+21
related_vector_mode and compatible_vector_types_p make it possible to generate 128-bit SVE code while still maintaining the distinction between SVE vectors and Advanced SIMD vectors. We can therefore generate VL-specific code for -msve-vector-bits=128 on little-endian targets. In theory we could do the same for big-endian targets, but it could have quite a high overhead; see the comment in the patch for details. 2020-01-10 Richard Sandiford <richard.sandiford@arm.com> gcc/ * doc/invoke.texi (-msve-vector-bits=): Document that -msve-vector-bits=128 now generates VL-specific code for little-endian targets. * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use build_vector_type_for_mode to construct the data vector types. * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate VL-specific code for -msve-vector-bits=128 on little-endian targets. (aarch64_simd_container_mode): Always prefer Advanced SIMD modes for 128-bit vectors. gcc/testsuite/ * gcc.target/aarch64/sve/struct_vect_1.c (N): Protect with #ifndef. * gcc.target/aarch64/sve/pcs/return_1_128.c: New test. * gcc.target/aarch64/sve/pcs/return_4_128.c: Likewise. * gcc.target/aarch64/sve/pcs/return_5_128.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_128.c: Likewise. * gcc.target/aarch64/sve/pcs/stack_clash_1_128.c: Likewise. * gcc.target/aarch64/sve/pcs/stack_clash_2_128.c: Likewise. * gcc.target/aarch64/sve/single_5.c: Likewise. * gcc.target/aarch64/sve/struct_vect_25.c: Likewise. * gcc.target/aarch64/sve/struct_vect_26.c: Likewise. From-SVN: r280125
2020-01-10[AArch64] Fix reversed vcond_mask invocation in aarch64_evpc_selRichard Sandiford1-1/+3
aarch64_evpc_sel (new in GCC 10) got the true and false vectors the wrong way round, leading to execution failures with fixed-length 128-bit SVE. Now that the ACLE types are in trunk, it's much easier to match the exact asm sequence for a permute. 2020-01-10 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask invocation. gcc/testsuite/ * gcc.target/aarch64/sve/sel_1.c: Use SVE types for the arguments and return values. Use check-function-bodies instead of scan-assembler. * gcc.target/aarch64/sve/sel_2.c: Likewise * gcc.target/aarch64/sve/sel_3.c: Likewise. From-SVN: r280121
2020-01-10[AArch64] Tighten mode checks in aarch64_builtin_vectorized_functionRichard Sandiford1-12/+5
aarch64_builtin_vectorized_function checked vectors based on the number of elements and the element mode. This doesn't interact well with fixed-length 128-bit SVE, where SVE modes can have those same properties. (And we can't just use the built-ins for SVE because the types use a different ABI. SVE handles this kind of thing using optabs instead.) 2020-01-10 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-builtins.c (aarch64_builtin_vectorized_function): Check for specific vector modes, rather than checking the number of elements and the element mode. From-SVN: r280114
2020-01-09[AArch64] Add support for the SVE2 ACLERichard Sandiford17-308/+5542
This patch adds support for the SVE2 ACLE, The implementation and tests follow the same pattern as the exiting SVE ACLE support. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to extra_objs. * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and aarch64-sve-builtins-sve2.h. (aarch64-sve-builtins-sve2.o): New rule. * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro. (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise. (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise. (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and TARGET_SVE2_SM4. * config/aarch64/aarch64-sve.md: Update comments with SVE2 instructions that are handled here. (@cond_asrd<mode>): Generalize to... (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this. (*cond_asrd<mode>_2): Generalize to... (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this. (*cond_asrd<mode>_z): Generalize to... (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this. * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec. (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise. (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise. * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New pattern. (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>) (@aarch64_scatter_stnt<mode>): Likewise. (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>) (@aarch64_mul_lane_<mode>): Likewise. (@aarch64_sve_suqadd<mode>_const): Likewise. (*<sur>h<addsub><mode>): Generalize to... (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this new pattern. (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander. (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern. (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise. (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise. (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise. (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise. (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise. (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise. (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander. (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern. (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise. (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise. (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise. (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>) (@aarch64_sve_add_mul_lane_<mode>): Likewise. (@aarch64_sve_sub_mul_lane_<mode>): Likewise. (@aarch64_sve2_xar<mode>): Likewise. (@aarch64_sve2_bcax<mode>): Likewise. (*aarch64_sve2_eor3<mode>): Rename to... (@aarch64_sve2_eor3<mode>): ...this. (@aarch64_sve2_bsl<mode>): New expander. (@aarch64_sve2_nbsl<mode>): Likewise. (@aarch64_sve2_bsl1n<mode>): Likewise. (@aarch64_sve2_bsl2n<mode>): Likewise. (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise. (*aarch64_sve2_sra<mode>): Add MOVPRFX support. (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern. (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise. (@aarch64_sve2_<USMAX:su>aba<mode>): New expander. (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern. (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise. (<su>mull<bt><Vwide>): Generalize to... (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new pattern. (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>) (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>) (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>) (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>) (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>) (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>) (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns. (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>) (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise. (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise. (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise. (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise. (<SHRNB:r>shrnb<mode>): Generalize to... (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this new pattern. (<SHRNT:r>shrnt<mode>): Generalize to... (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this new pattern. (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern. (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise. (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander. (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern. (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise. (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise. (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise. (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise. (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise. (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise. (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise. (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander. (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern. (@aarch64_sve2_cvtnt<mode>): Likewise. (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise. (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander. (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern. (@aarch64_sve2_cvtxnt<mode>): Likewise. (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise. (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander. (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern. (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise. (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander. (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern. (@aarch64_sve2_pmul<mode>): Likewise. (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise. (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise. (@aarch64_sve2_tbl2<mode>): Likewise. (@aarch64_sve2_tbx<mode>): Likewise. (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise. (@aarch64_sve2_histcnt<mode>): Likewise. (@aarch64_sve2_histseg<mode>): Likewise. (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise. (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise. (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise. (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise. (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise. (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise. (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise. (<su>mulh<r>s<mode>3): Update after above pattern name changes. * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY) (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI) (SVE2_PMULL_PAIR_I): New mode iterators. (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP) (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT) (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA) (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT) (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT) (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP) (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT) (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP) (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH) (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR) (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT) (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB) (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT) (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP) (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT) (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90) (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB) (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB) (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB) (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB) (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT) (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB) (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT) (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT) (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT) (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT) (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT) (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs. (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT) (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS) (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move further down file. (VNARROW, Ventype): New mode attributes. (Vewtype): Handle VNx2DI. Fix typo in comment. (VDOUBLE): New mode attribute. (sve_lane_con): Handle VNx8HI. (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2. (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus. (sve_int_op, sve_int_op_rev): Handle the above codes. (sve_pred_int_rhs2_operand): Likewise. (MULLBT, SHRNB, SHRNT): Delete. (SVE_INT_SHIFT_IMM): New int iterator. (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI and UNSPEC_WHILEHS for TARGET_SVE2. (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT) (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG) (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB) (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR) (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators. (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise. (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD) (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise. (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA) (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG) (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise. (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE) (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE) (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise. (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise. (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise. (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise. (optab): Handle the new unspecs. (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB and UNSPEC_RSHRNT. (lr): Handle the new unspecs. (bt): Delete. (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs. (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op) (sve_int_qsub_op): New int attributes. (sve_fp_op, rot): Handle the new unspecs. * config/aarch64/aarch64-sve-builtins.h (function_resolver::require_matching_pointer_type): Declare. (function_resolver::resolve_unary): Add an optional boolean argument. (function_resolver::finish_opt_n_resolution): Add an optional type_suffix_index argument. (gimple_folder::redirect_call): Declare. (gimple_expander::prepare_gather_address_operands): Add an optional bool parameter. * config/aarch64/aarch64-sve-builtins.cc: Include aarch64-sve-builtins-sve2.h. (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros. (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise. (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise. (TYPES_hsd_integer): Use TYPES_hsd_signed. (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros. (TYPES_s_unsigned): Likewise. (TYPES_s_integer): Use TYPES_s_unsigned. (TYPES_sd_signed, TYPES_sd_unsigned): New macros. (TYPES_sd_integer): Use them. (TYPES_d_unsigned): New macro. (TYPES_d_integer): Use it. (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros. (TYPES_cvt_narrow): Likewise. (DEF_SVE_TYPES_ARRAY): Include the new types macros above. (preds_mx): New variable. (function_builder::add_overloaded_function): Allow the new feature set to be more restrictive than the original one. (function_resolver::infer_pointer_type): Remove qualifiers from the pointer type before printing it. (function_resolver::require_matching_pointer_type): New function. (function_resolver::resolve_sv_displacement): Handle functions that don't support 32-bit vector indices or svint32_t vector offsets. (function_resolver::finish_opt_n_resolution): Take the inferred type as a separate argument. (function_resolver::resolve_unary): Optionally treat all forms in the same way as normal merging functions. (gimple_folder::redirect_call): New function. (function_expander::prepare_gather_address_operands): Add an argument that says whether scaled forms are available. If they aren't, handle scaling of vector indices and don't add the extension and scaling operands. (function_expander::map_to_unspecs): If aarch64_sve isn't available, fall back to using cond_* instead. * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function): Split out the member variables into... (rtx_code_function_base): ...this new base class. (rtx_code_function_rotated): Inherit rtx_code_function_base. (unspec_based_function): Split out the member variables into... (unspec_based_function_base): ...this new base class. (unspec_based_function_rotated): Inherit unspec_based_function_base. (unspec_based_function_exact_insn): New class. (unspec_based_add_function, unspec_based_add_lane_function) (unspec_based_lane_function, unspec_based_pred_function) (unspec_based_qadd_function, unspec_based_qadd_lane_function) (unspec_based_qsub_function, unspec_based_qsub_lane_function) (unspec_based_sub_function, unspec_based_sub_lane_function): New typedefs. (unspec_based_fused_function): New class. (unspec_based_mla_function, unspec_based_mls_function): New typedefs. (unspec_based_fused_lane_function): New class. (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New typedefs. (CODE_FOR_MODE1): New macro. (fixed_insn_function): New class. (while_comparison): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane) (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n) (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr) (load_ext_gather_index_restricted, load_ext_gather_offset_restricted) (load_gather_sv_restricted, shift_left_imm_long): Declare. (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise. (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise. (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted) (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane) (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate) (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint) (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt) (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication): Also add an initial argument for unary_convert_narrowt, regardless of the predication type. (build_32_64): Allow loads and stores to specify MODE_none. (build_sv_index64, build_sv_uint_offset): New functions. (long_type_suffix): New function. (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes. (binary_imm_long_base, load_gather_sv_base): Likewise. (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise. (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise. (unary_narrowb_base, unary_narrowt_base): Likewise. (binary_long_lane_def, binary_long_lane): New shape. (binary_long_opt_n_def, binary_long_opt_n): Likewise. (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise. (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise. (binary_to_uint_def, binary_to_uint): Likewise. (binary_wide_def, binary_wide): Likewise. (binary_wide_opt_n_def, binary_wide_opt_n): Likewise. (compare_def, compare): Likewise. (compare_ptr_def, compare_ptr): Likewise. (load_ext_gather_index_restricted_def, load_ext_gather_index_restricted): Likewise. (load_ext_gather_offset_restricted_def, load_ext_gather_offset_restricted): Likewise. (load_gather_sv_def): Inherit from load_gather_sv_base. (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape. (shift_left_imm_def, shift_left_imm): Likewise. (shift_left_imm_long_def, shift_left_imm_long): Likewise. (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise. (store_scatter_index_restricted_def, store_scatter_index_restricted): Likewise. (store_scatter_offset_restricted_def, store_scatter_offset_restricted): Likewise. (tbl_tuple_def, tbl_tuple): Likewise. (ternary_long_lane_def, ternary_long_lane): Likewise. (ternary_long_opt_n_def, ternary_long_opt_n): Likewise. (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base. (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base. (ternary_qq_rotate_def, ternary_qq_rotate): New shape. (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise. (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise. (ternary_uint_def, ternary_uint): Likewise. (unary_convert): Fix typo in comment. (unary_convert_narrowt_def, unary_convert_narrowt): New shape. (unary_long_def, unary_long): Likewise. (unary_narrowb_def, unary_narrowb): Likewise. (unary_narrowt_def, unary_narrowt): Likewise. (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise. (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise. (unary_to_int_def, unary_to_int): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla) (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions. (svasrd_impl): Delete. (svcadd_impl::expand): Handle integer operations too. (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the new functions to derive the unspec numbers. (svmla_svmls_lane_impl): Replace with... (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle integer operations too. (svwhile_impl): Rename to... (svwhilelx_impl): ...this and inherit from while_comparison. (svasrd): Use unspec_based_function. (svmla_lane): Use svmla_lane_impl. (svmls_lane): Use svmls_lane_impl. (svrecpe, svrsqrte): Handle unsigned integer operations too. (svwhilele, svwhilelt): Use svwhilelx_impl. * config/aarch64/aarch64-sve-builtins-sve2.h: New file. * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise. * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise. * config/aarch64/aarch64-sve-builtins.def: Include aarch64-sve-builtins-sve2.def. gcc/testsuite/ * g++.target/aarch64/sve/acle/general-c++/mul_lane_1.c: New test. * g++.target/aarch64/sve2/acle: New directory. * gcc.target/aarch64/pragma_cpp_predefs_3.c: New test. * gcc.target/aarch64/sve/acle/asm/test_sve_acle.h (TEST_TYPE_CHANGE_Z) (TEST_DUAL_ZD, TEST_TYPE_CHANGE_ZX, TEST_TBL2, TEST_TBL2_REV): New macros. * gcc.target/aarch64/sve/acle/general-c/binary_lane_1.c: Do not expect an error saying that the function has no f32 form, but instead expect an error about SVE2 being required if the current target doesn't support SVE2. * gcc.target/aarch64/sve/acle/general-c/ternary_lane_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/ternary_lane_rotate_1.c Likewise. * gcc.target/aarch64/sve/acle/general-c/binary_long_lane_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_long_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_narrowb_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_narrowt_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_wide_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_wide_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/compare_1.c, * gcc.target/aarch64/sve/acle/general-c/compare_ptr_1.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_index_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_2.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_3.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_4.c, * gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_2.c, * gcc.target/aarch64/sve/acle/general-c/mul_lane_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_left_imm_long_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_left_imm_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_left_imm_to_uint_2.c, * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowb_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowb_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowt_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowt_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/store_scatter_index_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/store_scatter_offset_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/tbl_tuple_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_long_lane_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_long_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_qq_lane_rotate_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_qq_rotate_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_shift_right_imm_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_convert_narrowt_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_narrowb_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_narrowb_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_narrowt_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_narrowt_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_to_int_1.c: New tests. * gcc.target/aarch64/sve2/bcax_1.c: Likewise. * gcc.target/aarch64/sve2/acle: New directory. From-SVN: r280060
2020-01-09[AArch64] Pass a mode to some SVE immediate queriesRichard Sandiford3-23/+17
It helps the SVE2 ACLE support if aarch64_sve_arith_immediate_p and aarch64_sve_sqadd_sqsub_immediate_p accept scalars as well as vectors. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p) (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument. * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p) (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar immediates as well as vector ones. * config/aarch64/predicates.md (aarch64_sve_arith_immediate) (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate) (aarch64_sve_qsub_immediate): Update calls accordingly. From-SVN: r280059
2020-01-09[AArch64] Add banner comments to aarch64-sve2.mdRichard Sandiford2-79/+186
This patch imposes the same sort of structure on aarch64-sve2.md as we already have for aarch64-sve.md, before it grows a lot more patterns. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve2.md: Add banner comments. (<su>mulh<r>s<mode>3): Move further up file. (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>) (*aarch64_sve2_sra<mode>): Move further down file. * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too. From-SVN: r280058
2020-01-09[AArch64] Simplify WHILERW and WHILEWR definitionRichard Sandiford3-28/+10
I'd made WHILERW and WHILEWR use separate patterns from the SVE WHILE instructions, but they're similar enough that we can use a single pattern. This means that we also get the flag-related patterns "for free". 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW and UNSPEC_WHILEWR. (while_optab_cmp): Handle them. * config/aarch64/aarch64-sve.md (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public and add a "@" marker. * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it instead of gen_aarch64_sve2_while_ptest. (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete. From-SVN: r280054
2020-01-09[AArch64] Rename UNSPEC_WHILE* to match instruction mnemonicsRichard Sandiford4-17/+17
The UNSPEC_WHILE*s had an underscore before the condition code, whereas almost all other SVE unspecs are taken directly from the mnemonic. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to... (UNSPEC_WHILELE): ...this. (UNSPEC_WHILE_LO): Rename to... (UNSPEC_WHILELO): ...this. (UNSPEC_WHILE_LS): Rename to... (UNSPEC_WHILELS): ...this. (UNSPEC_WHILE_LT): Rename to... (UNSPEC_WHILELT): ...this. * config/aarch64/iterators.md (SVE_WHILE): Update accordingly. (cmp_op, while_optab_cmp): Likewise. * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise. (svwhilelt): Likewise. From-SVN: r280053
2020-01-09[AArch64] Rename SVE shape "unary_count" to "unary_to_uint"Richard Sandiford3-25/+25
The SVE ACLE shape names use "_int" and "_uint" for arguments that are signed-integer or unsigned-integer variants of the main vector type. With SVE2 this variation also becomes common for return values, which the main SVE2 patch handles using "_to_int" and "_to_uint". This patch renames the existing unary_count shape to match the new scheme. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete. (unary_to_uint): Define. * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def) (unary_count): Rename to... (unary_to_uint_def, unary_to_uint): ...this. * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general-c/unary_count_1.c: Rename to... * gcc.target/aarch64/sve/acle/general-c/unary_to_uint_1.c: ...this. * gcc.target/aarch64/sve/acle/general-c/unary_count_2.c: Rename to... * gcc.target/aarch64/sve/acle/general-c/unary_to_uint_2.c: ...this. * gcc.target/aarch64/sve/acle/general-c/unary_count_3.c: Rename to... * gcc.target/aarch64/sve/acle/general-c/unary_to_uint_3.c: ...this. From-SVN: r280052
2020-01-09[AArch64] Specify some SVE ACLE functions in a more generic wayRichard Sandiford2-55/+28
This patch generalises some boilerplate that becomes much more common with SVE2 intrinsics. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve-builtins-functions.h (code_for_mode_function): New class. (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros. * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl) (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete. (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0. (svmul_lane, svtmad): Use CODE_FOR_MODE0. From-SVN: r280051
2020-01-09[AArch64] Tweak iterator usage for [SU]Q{ADD,SUB}Richard Sandiford6-51/+30
The pattern: ;; <su>q<addsub> (define_insn "aarch64_<su_optab><optab><mode>" [(set (match_operand:VSDQ_I 0 "register_operand" "=w") (BINQOPS:VSDQ_I (match_operand:VSDQ_I 1 "register_operand" "w") (match_operand:VSDQ_I 2 "register_operand" "w")))] "TARGET_SIMD" "<su_optab><optab>\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>" [(set_attr "type" "neon_<optab><q>")] ) meant that we overloaded "optab" to be "qadd" for both SQADD and UQADD. Most other "optab" entries are instead the full optab name, which for these patterns would be "ssadd" and "usadd" respectively. (Unfortunately, the optabs don't extend to vectors yet, something that would be good to fix in GCC 11.) This patch therefore does what the comment implies and uses q<addsub> to distinguish qadd and qsub instead. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (addsub): New code attribute. * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>): Re-express as... (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change in the asm string and attributes. Fix indentation. * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>): Re-express as... (@aarch64_sve_<optab><mode>): ...this. * config/aarch64/aarch64-sve-builtins.h (function_expander::expand_signed_unpred_op): Delete. * config/aarch64/aarch64-sve-builtins.cc (function_expander::expand_signed_unpred_op): Likewise. (function_expander::map_to_rtx_codes): If the optab isn't defined, try using code_for_aarch64_sve instead. * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete. (svqsub_impl): Likewise. (svqadd, svqsub): Use rtx_code_function instead. From-SVN: r280050
2020-01-09[AArch64] Remove fictitious [SU]RHSUB instructionsRichard Sandiford1-7/+1
We've had skeleton support for "SRHSUB" and "URHSUB" since the initial commit of the port, but no such instructions exist. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete. (HADDSUB, sur, addsub): Remove them. From-SVN: r280049
2020-01-09Add a compatible_vector_types_p target hookRichard Sandiford2-2/+18
One problem with adding an N-bit vector extension to an existing architecture is to decide how N-bit vectors should be passed to functions and returned from functions. Allowing all N-bit vector types to be passed in registers breaks backwards compatibility, since N-bit vectors could be used (and emulated) before the vector extension was added. But always passing N-bit vectors on the stack would be inefficient for things like vector libm functions. For SVE we took the compromise position of predefining new SVE vector types that are distinct from all existing vector types, including GNU-style vectors. The new types are passed and returned in an efficient way while existing vector types are passed and returned in the traditional way. In the right circumstances, the two types are inter-convertible. The SVE types are created using: vectype = build_distinct_type_copy (vectype); SET_TYPE_STRUCTURAL_EQUALITY (vectype); TYPE_ARTIFICIAL (vectype) = 1; The C frontend maintains this distinction, using VIEW_CONVERT_EXPR to convert from one type to the other. However, the distinction can be lost during gimple, which treats two vector types with the same mode, number of elements, and element type as equivalent. And for most targets that's the right thing to do. This patch therefore adds a hook that lets the target choose whether such vector types are indeed equivalent. Note that the new tests fail for -mabi=ilp32 in the same way as other ACLE-based tests. I'm still planning to fix that as a follow-on. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * target.def (compatible_vector_types_p): New target hook. * hooks.h (hook_bool_const_tree_const_tree_true): Declare. * hooks.c (hook_bool_const_tree_const_tree_true): New function. * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook. * doc/tm.texi: Regenerate. * gimple-expr.c: Include target.h. (useless_type_conversion_p): Use targetm.compatible_vector_types_p. * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New function. (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define. * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred): Use the original predicate if it already has a suitable type. gcc/testsuite/ * gcc.target/aarch64/sve/pcs/gnu_vectors_1.c: New test. * gcc.target/aarch64/sve/pcs/gnu_vectors_2.c: Likewise. From-SVN: r280047
2020-01-09re PR inline-asm/93202 ([RISCV] ICE when using inline asm 'h' operand modifier)Jakub Jelinek1-1/+2
PR inline-asm/93202 * config/riscv/riscv.c (riscv_print_operand_reloc): Use output_operand_lossage instead of gcc_unreachable. * doc/md.texi (riscv f constraint): Fix typo. * gcc.target/riscv/pr93202.c: New test. From-SVN: r280030
2020-01-09re PR target/93141 (Missed optimization : Use of adc when checking overflow)Jakub Jelinek1-12/+169
PR target/93141 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of SWI. Use <general_hilo_operand> instead of <general_operand>. Use CONST_SCALAR_INT_P instead of CONST_INT_P. (*subv<mode>4_1): Rename to ... (subv<mode>4_1): ... this. (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New define_insn_and_split patterns. (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn patterns. * gcc.target/i386/pr93141-1.c: Add tests with constants that have MSB of the low half of the constant set. * gcc.target/i386/pr93141-2.c: New test. From-SVN: r280029
2020-01-08RISC-V: Disable use of TLS copy relocs.Jim Wilson1-0/+3
Musl and lld don't support TLS copy relocs, and don't want to add support for this feature which is unique to RISC-V. Only GNU ld and glibc support them. In the pasbi discussion, people have pointed out various problems with using them, so we are deprecating them. There doesn't seem to be an ABI break from dropping them so this patch modifies gcc to stop creating them. I'm using an ifdef for now in case a problem turns up and the code has to be re-enabled. The plan is to add an initial to local exec relaxation as a replacement, though this has not been defined or implemented yet. gcc/ * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out use of TLS_MODEL_LOCAL_EXEC when not pic. From-SVN: r280025
2020-01-08re PR target/93187 (ICE in extract_insn, at recog.c:2294)Jakub Jelinek1-0/+2
PR target/93187 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2, *stack_protect_set_3 peephole2): Also check that the second insns source is general_operand. * g++.dg/opt/pr93187.C: New test. From-SVN: r280012
2020-01-08re PR target/93174 (ICE building glibc __sha512_process_block for i686)Jakub Jelinek1-5/+5
PR target/93174 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand predicate for output operand instead of register_operand. (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with memory destination and non-memory operands[2]. * gcc.c-torture/compile/pr93174.c: New test. From-SVN: r280011
2020-01-08Add -nodevicespecs option for avr.Georg-Johann Lay2-4/+8
gcc/ Add -nodevicespecs option for avr. PR target/93182 * config/avr/avr.opt (-nodevicespecs): New driver option. * config/avr/driver-avr.c (avr_devicespecs_file): Only issue "-specs=device-specs/..." if that option is not set. * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document. From-SVN: r279995
2020-01-08Implement 64-bit double functions.Georg-Johann Lay4-1/+53
gcc/ PR target/92055 * config.gcc (tm_defines) [target=avr]: Support --with-libf7, --with-double-comparison. * doc/install.texi: Document them. * config/avr/avr-c.c (avr_cpu_cpp_builtins) <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS> <WITH_DOUBLE_COMPARISON>: New built-in defines. * doc/invoke.texi (AVR Built-in Macros): Document them. * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New. * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function. * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro. libgcc/ PR target/92055 * config.host (tmake_file) [target=avr]: Add t-libf7, t-libf7-math, t-libf7-math-symbols as specified by --with-libf7=. * config/avr/t-avrlibc: Don't copy libgcc.a if there are modules depending on sizeof (double) or sizeof (long double). * config/avr/libf7: New folder. libgcc/config/avr/libf7/ PR target/92055 * t-libf7: New file. * t-libf7-math: New file. * t-libf7-math-symbols: New file. * libf7-common.mk: New file. * libf7-asm-object.mk: New file. * libf7-c-object.mk: New file. * asm-defs.h: New file. * libf7.h: New file. * libf7.c: New file. * libf7-asm.sx: New file. * libf7-array.def: New file. * libf7-const.def: New file. * libf7-constdef.h: New file. * f7renames.sh: New script. * f7wraps.sh: New script. * f7-renames.h: New generated file. * f7-wraps.h: New generated file. From-SVN: r279994
2020-01-08arm: Fix rmprofile multilibs when architecture includes +mp or +sec (PR ↵Richard Earnshaw1-0/+9
target/93188) When only the rmprofile multilibs are built, compiling for armv7-a should select the generic v7 multilibs. This used to work before +sec and +mp were added to the architecture options but it was broken by that update. This patch fixes those variants and adds some tests to ensure that they remain fixed ;-) PR target/93188 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants when only building rm-profile multilibs. * gcc.target/arm/multilib.exp: Add new tests for rm-profile only. From-SVN: r279993
2020-01-07Revert patch accidentily created on the wrong sandboxMichael Meissner1-86/+0
From-SVN: r279973
2020-01-07Restore patch reverted on trunk instead of a branchMichael Meissner1-0/+86
From-SVN: r279972
2020-01-07[amdgcn] Add more modes for vector comparisonsAndrew Stubbs3-50/+111
2020-01-07 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator. (VEC_ALLREG_ALT): New iterator. (VEC_ALLREG_INT_MODE): New iterator. (VCMP_MODE): New iterator. (VCMP_MODE_INT): New iterator. (vec_cmpu<mode>di): Use VCMP_MODE_INT. (vec_cmp<u>v64qidi): New define_expand. (vec_cmp<mode>di_exec): Use VCMP_MODE. (vec_cmpu<mode>di_exec): New define_expand. (vec_cmp<u>v64qidi_exec): New define_expand. (vec_cmp<mode>di_dup): Use VCMP_MODE. (vec_cmp<mode>di_dup_exec): Use VCMP_MODE. (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ... (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this. (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ... (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this. (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ... (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this. (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ... (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to this. * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes. * config/gcn/gcn.md (expander): Add sign_extend and zero_extend. From-SVN: r279961
2020-01-07Disallow 'B' constraints on amdgcn addc/subbAndrew Stubbs4-159/+70
2020-01-07 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/constraints.md (DA): Update description and match. (DB): Likewise. (Db): New constraint. * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second parameter. * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter. Implement 'Db' mixed immediate type. * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints. (addcv64si3_dup<exec_vcc>): Delete. (subcv64si3<exec_vcc>): Rework constraints. (addv64di3): Rework constraints. (addv64di3_exec): Rework constraints. (subv64di3): Rework constraints. (addv64di3_dup): Delete. (addv64di3_dup_exec): Delete. (addv64di3_zext): Rework constraints. (addv64di3_zext_exec): Rework constraints. (addv64di3_zext_dup): Rework constraints. (addv64di3_zext_dup_exec): Rework constraints. (addv64di3_zext_dup2): Rework constraints. (addv64di3_zext_dup2_exec): Rework constraints. (addv64di3_sext_dup2): Rework constraints. (addv64di3_sext_dup2_exec): Rework constraints. From-SVN: r279959
2020-01-07Add a generic lhd_simulate_enum_declRichard Sandiford1-1/+4
Normally we only create SVE ACLE functions when arm_sve.h is included. But for LTO we need to do it at start-up, so that the functions are already defined when streaming in the LTO objects. One hitch with doing that is that LTO doesn't yet implement the simulate_enum_decl langhook. This patch adds a simple default implementation that it can use. 2020-01-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * langhooks-def.h (lhd_simulate_enum_decl): Declare. (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it. * langhooks.c: Include stor-layout.h. (lhd_simulate_enum_decl): New function. * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call handle_arm_sve_h for the LTO frontend. (register_vector_type): Cope with null returns from pushdecl. gcc/testsuite/ * gcc.target/aarch64/sve/pcs/asm_4.c: New test. From-SVN: r279954
2020-01-07[AArch64] Use type attributes to mark types that use the SVE PCSRichard Sandiford3-87/+65
The SVE port needs to maintain a different type identity for GNU vectors and "SVE vectors", since the types use different ABIs. Until now we've done that using pointer equality between the TYPE_MAIN_VARIANT and the built-in SVE type. However, as Richard B noted, that doesn't work well for LTO, where we stream both GNU and SVE types from a file instead of creating them directly. We need a mechanism for distinguishing the types using streamed type information. This patch does that using a new type attribute. This attribute is only meant to be used for the built-in SVE types and shouldn't be user-visible. The patch tries to ensure this by including a space in the attribute name, like we already do for things like "fn spec" and "omp declare simd". 2020-01-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p) (aarch64_sve::nvectors_if_data_type): Replace with... (aarch64_sve::builtin_type_p): ...this. * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h. (find_vector_type): Delete. (add_sve_type_attribute): New function. (lookup_sve_type_attribute): Likewise. (register_builtin_types): Add an "SVE type" attribute to each type. (register_tuple_type): Likewise. (svbool_type_p, nvectors_if_data_type): Delete. (mangle_builtin_type): Use lookup_sve_type_attribute. (builtin_type_p): Likewise. Add an overload that returns the number of constituent vector and predicate registers. * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete. (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p instead of aarch64_sve_argument_p. (aarch64_takes_arguments_in_sve_regs_p): Likewise. (aarch64_pass_by_reference): Likewise. (aarch64_function_value_1): Likewise. (aarch64_return_in_memory): Likewise. (aarch64_layout_arg): Likewise. gcc/testsuite/ * g++.target/aarch64/sve/acle/general-c++/mangle_5.C: New test. * gcc.target/aarch64/sve/pcs/asm_1.c: Likewise. * gcc.target/aarch64/sve/pcs/asm_2.c: Likewise. * gcc.target/aarch64/sve/pcs/asm_3.c: Likewise. From-SVN: r279953
2020-01-07Refactor some code for a future change.Michael Meissner1-15/+26
2020-01-06 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New helper function to return the valid addressing formats for a given hard register and mode. (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 279912) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -6729,6 +6729,30 @@ rs6000_expand_vector_extract (rtx target } } +/* Helper function to return an address mask based on a physical register. */ + +static addr_mask_type +hard_reg_and_mode_to_addr_mask (rtx reg, machine_mode mode) +{ + unsigned int r = reg_or_subregno (reg); + addr_mask_type addr_mask; + + gcc_assert (HARD_REGISTER_NUM_P (r)); + if (INT_REGNO_P (r)) + addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR]; + + else if (FP_REGNO_P (r)) + addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR]; + + else if (ALTIVEC_REGNO_P (r)) + addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX]; + + else + gcc_unreachable (); + + return addr_mask; +} + /* Adjust a memory address (MEM) of a vector type to point to a scalar field within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register temporary (BASE_TMP) to fixup the address. Return the new memory address @@ -6865,21 +6889,8 @@ rs6000_adjust_vec_address (rtx scalar_re if (GET_CODE (new_addr) == PLUS) { rtx op1 = XEXP (new_addr, 1); - addr_mask_type addr_mask; - unsigned int scalar_regno = reg_or_subregno (scalar_reg); - - gcc_assert (HARD_REGISTER_NUM_P (scalar_regno)); - if (INT_REGNO_P (scalar_regno)) - addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR]; - - else if (FP_REGNO_P (scalar_regno)) - addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR]; - - else if (ALTIVEC_REGNO_P (scalar_regno)) - addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX]; - - else - gcc_unreachable (); + addr_mask_type addr_mask + = hard_reg_and_mode_to_addr_mask (scalar_reg, scalar_mode); if (REG_P (op1) || SUBREG_P (op1)) valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0; From-SVN: r279941
2020-01-07Update 'Q' constraint documentation.Michael Meissner1-2/+1
2020-01-06 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/constraints.md (Q constraint): Update documentation. * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint documentation. From-SVN: r279939
2020-01-07Fix bad code of vector extract of PC-relative address with variable element #.Michael Meissner1-4/+4
2020-01-06 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator): Use 'Q' for doing vector extract from memory. (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from memory. (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for doing vector extract from memory. (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector extract from memory. From-SVN: r279938
2020-01-07Add support for large prefixed address in adjusting a vector address.Michael Meissner1-1/+15
2020-01-06 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support for the offset being 34-bits when -mcpu=future is used. From-SVN: r279937
2020-01-06pa.md: Revert change to use ordered_comparison_operator instead of...John David Anglin2-2/+8
* config/pa/pa.md: Revert change to use ordered_comparison_operator instead of cmpib_comparison_operator in cmpib patterns. * config/pa/predicates.md (cmpib_comparison_operator): Revert removal of cmpib_comparison_operator. Revise comment. From-SVN: r279927
2020-01-06Fix amdgcn issue with '0' constraintsAndrew Stubbs1-13/+13
2020-01-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for '0' matching inputs. (subv64di3_exec): Likewise. From-SVN: r279906
2020-01-06mips.c (vr4130_align_insns): Fix typo.Bryan Stenson1-1/+1
2020-01-06 Bryan Stenson <bryan@siliconvortex.com> * config/mips/mips.c (vr4130_align_insns): Fix typo. * doc/md.texi (movstr): Likewise. From-SVN: r279905
2020-01-06Fix early-clobber in amdgcn vec_extractAndrew Stubbs1-3/+3
2020-01-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early clobber. From-SVN: r279904
2020-01-06[AArch64] Use move-if-change for aarch64-tune.mdRichard Sandiford1-1/+5
If aarch64-tune.md was older than gentune.sh or aarch64-cores.def, we'd try to overwrite it even if the current contents were correct. This could cause problems with read-only source directories and could cause spurious copying for rsync --archive. 2020-01-06 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md): Depend on... (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents to a temporary file and use move-if-change to update the real file where necessary. From-SVN: r279900
2020-01-06[AArch64] Fix constraints for CPY /MRichard Sandiford1-1/+1
The constraints for CPY /M allowed p0-p15 instead of the intended p0-p7. This looks like a pasto from the preceding constant pattern, where p0-p15 is allowed. 2020-01-06 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl rather than Upa for CPY /M. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general/cpy_1.c: New test. From-SVN: r279899
2020-01-06Fix amdgcn inline immediate rangeAndrew Stubbs1-1/+1
2020-01-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline immediate. From-SVN: r279898
2020-01-05re PR target/93141 (Missed optimization : Use of adc when checking overflow)Jakub Jelinek1-19/+276
PR target/93141 * config/i386/i386.md (SWIDWI): New mode iterator. (DWI, dwi): Add TImode variants. (addv<mode>4): Use SWIDWI iterator instead of SWI. Use <general_hilo_operand> instead of <general_operand>. Use CONST_SCALAR_INT_P instead of CONST_INT_P. (*addv<mode>4_1): Rename to ... (addv<mode>4_1): ... this. (QWI): New mode attribute. (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New define_insn_and_split patterns. (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn patterns. (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use <general_hilo_operand> instead of <general_operand>. (*addcarry<mode>_1): New define_insn. (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split. * gcc.target/i386/pr93141-1.c: New test. * gcc.dg/pr67089-6.c: Expect 16 ADD_OVERFLOW calls even on ia32. From-SVN: r279887
2020-01-03re PR target/93089 (Force mprefer-vector-width=512 in 'e' simd clones)Jakub Jelinek1-3/+24
PR target/93089 * config/i386/i386-options.c (ix86_simd_clone_adjust): If TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd' simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512 for 'e' simd clones. * gcc.target/i386/pr93089-2.c: New test. * gcc.target/i386/pr93089-3.c: New test. From-SVN: r279857
2020-01-03re PR target/93089 (Force mprefer-vector-width=512 in 'e' simd clones)Jakub Jelinek4-13/+45
PR target/93089 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave entry. (mprefer-vector-width=): Add Save. * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment. (ix86_debug_options, ix86_function_specific_print): Adjust ix86_target_string callers. (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=. (ix86_valid_target_attribute_tree): Likewise. * config/i386/i386-options.h (ix86_target_string): Add PVW argument. * config/i386/i386-expand.c (ix86_expand_builtin): Adjust ix86_target_string caller. * gcc.target/i386/pr93089-1.c: New test. From-SVN: r279856
2020-01-03re PR target/93110 (grub-2.04/grub-core/lib/division.c:28:1: internal ↵Jakub Jelinek1-24/+10
compiler error: in extract_insn, at recog.c:2294) PR target/93110 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode instead of gen_int_shift_amount + convert_modes. * gcc.dg/torture/pr93110.c: New test. From-SVN: r279855
2020-01-02[Arm] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16.Dennis Zhang8-12/+95
2020-01-02 Dennis Zhang <dennis.zhang@arm.com> * config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC, __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and __ARM_BF16_FORMAT_ALTERNATIVE when enabled. * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features. * config/arm/arm-tables.opt: Regenerated. * config/arm/arm.c (arm_option_reconfigure_globals): Initialize arm_arch_i8mm and arm_arch_bf16 when enabled. * config/arm/arm.h (TARGET_I8MM): New macro. (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a. * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a. * config/arm/t-multilib: Add matching rules for -march=armv8.6-a. (v8_6_a_simd_variants): New. (v8_*_a_simd_variants): Add i8mm and bf16. * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. 2020-01-02 Dennis Zhang <dennis.zhang@arm.com> * gcc.target/arm/multilib.exp: Add combination tests for armv8.6-a. From-SVN: r279839
2020-01-01re PR target/67834 (Local references inside comdat groups)John David Anglin2-0/+26
PR target/67834 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to COMDAT group function labels in .data.rel.ro.local section. * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define. From-SVN: r279823
2020-01-01re PR target/93111 (FAIL: gfortran.fortran-torture/compile/pr32663.f, -O3 ↵John David Anglin2-31/+25
-g (internal compiler error)) PR target/93111 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of comparison_operator in B and S integer comparisons. Likewise, use ordered_comparison_operator instead of cmpib_comparison_operator in cmpib patterns. * config/pa/predicates.md (cmpib_comparison_operator): Remove. From-SVN: r279818
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