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AgeCommit message (Expand)AuthorFilesLines
2017-08-31[AArch64] Remove use of wider vector modesRichard Sandiford4-277/+34
2017-08-30rs6000.c (rs6000_emit_prologue_move_from_cr): Rename from rs6000_emit_move_fr...Pat Haugen2-11/+17
2017-08-30rs6000.c (rs6000_expand_binop_builtin): Revert back to if statements, includi...David Edelsohn1-32/+31
2017-08-30[73/77] Pass scalar_mode to scalar_mode_supported_pRichard Sandiford12-15/+15
2017-08-30[72/77] Pass scalar_mode to scalar_mode_supported_pRichard Sandiford17-21/+21
2017-08-30[67/77] Use scalar_mode in fixed-value.*Richard Sandiford1-1/+1
2017-08-30[62/77] Big machine_mode to scalar_int_mode replacementRichard Sandiford15-36/+36
2017-08-30[37/77] Use scalar_int_mode when emitting cstoresRichard Sandiford1-2/+2
2017-08-30[20/77] Replace MODE_INT checks with is_int_modeRichard Sandiford1-8/+12
2017-08-30[19/77] Add a smallest_int_mode_for_size helper functionRichard Sandiford6-12/+11
2017-08-30[18/77] Make int_mode_for_mode return an opt_scalar_int_modeRichard Sandiford7-28/+26
2017-08-30[15/77] Add scalar_int_modeRichard Sandiford7-17/+16
2017-08-30[14/77] Make libgcc_floating_mode_supported_p take a scalar_float_modeRichard Sandiford1-1/+1
2017-08-30[13/77] Make floatn_mode return an opt_scalar_float_modeRichard Sandiford3-13/+17
2017-08-30[10/77] Make assemble_real take a scalar_float_modeRichard Sandiford4-31/+22
2017-08-30[7/77] Add scalar_float_modeRichard Sandiford1-2/+6
2017-08-30[6/77] Make GET_MODE_WIDER return an opt_modeRichard Sandiford5-11/+13
2017-08-30[4/77] Add FOR_EACH iterators for modesRichard Sandiford1-1/+1
2017-08-30[3/77] Allow machine modes to be classesRichard Sandiford1-2/+2
2017-08-30[2/77] Add an E_ prefix to case statementsRichard Sandiford61-2614/+2623
2017-08-30[1/77] Add an E_ prefix to mode namesRichard Sandiford15-154/+156
2017-08-30msp430.h: Pass -mcode/data-region to the linker and -mdata-region to the asse...Jozef Lawrynowicz1-2/+4
2017-08-30[rs6000] int->machine_mode in rs6000-c.cRichard Sandiford1-1/+1
2017-08-29re PR target/82015 (PowerPC should check if 2nd argument to __builtin_unpackv...Michael Meissner2-27/+43
2017-08-29i386.opt (flag_fentry): Do not init to -1.Uros Bizjak2-18/+9
2017-08-29re PR target/80993 ([msp430] __attribute__((interrupt)) should imply __attrib...Jozef Lawrynowicz1-0/+4
2017-08-27re PR target/81995 (gcc/reg-stack.c:2073:1: error: unrecognizable insn:)Uros Bizjak1-8/+8
2017-08-25Part 2/3 for contributing PPC64LE support for X86 SSE instrisics.Steven Munroe2-0/+1823
2017-08-25re PR target/81504 (gcc-7 regression: vec_st in loop misoptimized)William Schmidt1-8/+39
2017-08-24rs6000.opt (-mpower9-dform-scalar): Delete undocumented switches.Michael Meissner7-131/+22
2017-08-24Adds the powerpc equivalent mm_malloc.h header which is needed by xmmintrin.h...Steven Munroe1-0/+62
2017-08-24re PR target/81921 (Fails to always-inline intrinsics with -flto)Richard Biener1-53/+37
2017-08-24i386.c: Include symbol-summary.h, ipa-prop.h and ipa-fnsummary.h.Richard Biener1-1/+11
2017-08-23PR target/80969 - Fix ICE with -mabi=ms -mavx512f, reduce wasted space when r...Daniel Santos2-83/+154
2017-08-23i386.opt: Remove unneeded Init(0) initializations.Uros Bizjak2-8/+8
2017-08-22PR target/71958: Error on -mx32 with -mabi=msDaniel Santos1-2/+10
2017-08-22[PowerPC/RTEMS] Enable -mcmodel optionSebastian Huber1-0/+60
2017-08-22[AArch64] Fix label modeRichard Sandiford1-1/+1
2017-08-22re PR target/81910 ([avr] ICE with "address" attribute on type)Georg-Johann Lay1-11/+15
2017-08-21rs6000-cpus.def (-mvsx-scalar-float): Delete undocumented debugging options.Michael Meissner2-28/+4
2017-08-21re PR target/46091 (missed optimization: x86 bt/btc/bts instructions)Uros Bizjak1-13/+99
2017-08-21Remove the frame size argument from function_prologue/epilogueRichard Sandiford18-72/+48
2017-08-21re PR target/79883 (avr i18n: untranslated "interrupt" or "signal")Georg-Johann Lay1-1/+1
2017-08-21re PR go/78628 (GO fails to build a translation unit decl)Richard Biener3-20/+57
2017-08-19i386.h (OPTION_MASK_ISA_ROUND): Remove.Uros Bizjak5-50/+46
2017-08-18re PR target/80210 (ICE in in extract_insn, at recog.c:2311 on ppc64 for with...Peter Bergner1-45/+54
2017-08-17altivec.md (UNSPEC_VMRGOW_DIRECT): New constant.Bill Schmidt2-6/+20
2017-08-17altivec.md (VParity): Remove TARGET_VSX_TIMODE.Peter Bergner8-51/+31
2017-08-17re PR target/72804 (Poor code gen with -mvsx-timode)Peter Bergner1-15/+47
2017-08-17[AArch64] Improve SIMD store of zero.Jackson Woodruff1-22/+28
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