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2008-10-01rs6000-c.c (altivec_overloaded_builtins): Add Cell Altivec intrinsics.Andrew Pinski5-11/+449
2008-10-01 Andrew Pinski <andrew_pinski@playstation.sony.com> Yukishige Shibata <shibata@rd.scei.sony.co.jp> Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add Cell Altivec intrinsics. * config/rs6000/rs6000.c (altivec_expand_lv_builtin): Delete prototype. Add new parameter, blk. Use BLKmode for the MEM if blk is true. (altivec_expand_builtin): Handle ALTIVEC_BUILTIN_STVLX, ALTIVEC_BUILTIN_STVLXL, ALTIVEC_BUILTIN_STVRX, and ALTIVEC_BUILTIN_STVRXL. Update usage of altivec_expand_lv_builtin. Handle ALTIVEC_BUILTIN_LVLX, ALTIVEC_BUILTIN_LVLXL, ALTIVEC_BUILTIN_LVRX, and ALTIVEC_BUILTIN_LVRXL. (altivec_init_builtins): If compiling for the Cell, also define the cell VMX builtins. * config/rs6000/rs6000.h (rs6000_builtins): Define ALTIVEC_BUILTIN_LVLX, ALTIVEC_BUILTIN_LVLXL, ALTIVEC_BUILTIN_LVRX, ALTIVEC_BUILTIN_LVRXL, ALTIVEC_BUILTIN_STVLX, ALTIVEC_BUILTIN_STVLXL, ALTIVEC_BUILTIN_STVRX, ALTIVEC_BUILTIN_STVRXL, ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_VEC_STVRX, and ALTIVEC_BUILTIN_VEC_STVRXL. * config/rs6000/altivec.md (define_constants): Define UNSPEC_LVLX, UNSPEC_LVLXL, UNSPEC_LVRX, UNSPEC_LVRXL, UNSPEC_STVLX, UNSPEC_STVLXL, UNSPEC_STVRX, and UNSPEC_STVRXL. (altivec_lvlx): New pattern. (altivec_lvlxl): New pattern. (altivec_lvrx): New pattern. (altivec_lvrxl): New pattern. (altivec_stvlx): New pattern. (altivec_stvlxl): New pattern. (altivec_stvrx): New pattern. (altivec_stvrxl): New pattern. * config/rs6000/altivec.h (vec_lvlx): Define if PPU is defined. (vec_lvlxl): Likewise. (vec_lvrx): Define if PPU is defined. (vec_lvrxl): Likewise. (vec_stvlx): Define if PPU is defined. (vec_stvlxl): Likewise. (vec_stvrx): Define if PPU is defined. (vec_stvrxl): Likewise. 2008-10-01 Andrew Pinski <andrew_pinski@playstation.sony.com> * gcc.target/powerpc/altivec_check.h (altivec_cell_check): New function. * gcc.target/powerpc/altivec-cell-6.c: New test. * gcc.target/powerpc/altivec-cell-7.c: New test. * gcc.target/powerpc/altivec-cell-8.c: New test. From-SVN: r140820
2008-09-30rs6000.md (fnmadds combiner): Revert typo.Andrew Pinski1-1/+1
2008-09-30 Andrew Pinski <andrew_pinski@playstation.sony.com> * config/rs6000/rs6000.md (fnmadds combiner): Revert typo. From-SVN: r140785
2008-09-29i386.opt: Add msse2avx.H.J. Lu3-0/+14
2008-09-29 H.J. Lu <hongjiu.lu@intel.com> * config/i386/i386.opt: Add msse2avx. * config/i386/linux.h (ASM_SPEC): New. Support -msse2avx. * config/i386/linux64.h (ASM_SPEC): Likewise. * doc/invoke.texi: Document -msse2avx. From-SVN: r140774
2008-09-29predicates.md (easy_fp_constant): Single FP consts are easy.Michael J. Eager6-157/+291
* config/rs6000/predicates.md (easy_fp_constant): Single FP consts are easy. * config/rs6000/rs6000.c (rs6000_override_options): Move rs6000_init_hard_regno_mode_ok after all options changed. Set rs6000_single_float, rs6000_double_float if TARGET_HARD_FLOAT. (rs6000_handle_option): Process -msingle-float, -mdouble-float, -msimple-fpu flags. Add warning messages if single FP not configured. (rs6000_file_start): Output gnu_attribute for single-float. (legitimate_lo_sum_address_p): Condition on TARGET_DOUBLE_FLOAT. (rs6000_legitimize_address): Likewise. (rs6000_legitimize_reload_address): Likewise. (rs6000_emit_move): Condition on TARGET_DOUBLE_FLOAT, TARGET_SINGLE_FLOAT. (function_arg_advance): Likewise (partial conversion). (setup_incoming_varargs): Condition on TARGET_DOUBLE_FLOAT. (rs6000_gimplify_va_arg): Condition on TARGET_DOUBLE_FLOAT, TARGET_SINGLE_FLOAT. (rs6000_split_multireg_move): Condition on TARGET_DOUBLE_FLOAT. (rs6000_emit_prologue): Likewise. (rs6000_function_value): Condition on TARGET_DOUBLE_FLOAT, TARGET_SINGLE_FLOAT. (rs6000_libcall_value): Likewise. * config/rs6000/rs6000.h (TARGET_SINGLE_FLOAT): New default to 1. (TARGET_DOUBLE_FLOAT): New default to 1 (TARGET_SIMPLE_FPU): New default to 0 (TARGET_SINGLE_FPU): New default to 0 (TARGET_SINGLE_FLOAT_MODE): New. (TARGET_DOUBLE_FLOAT_MODE): New. * config/rs6000/singlefp.h: New; redefine TARGET_SINGLE_FLOAT, TARGET_DOUBLE_FLOAT, TARGET_SIMPLE_FPU, TARGET_SINGLE_FPU, UNITS_PER_FP_WORD * config/rs6000/rs6000.md (define_mode_iterator): Condition on TARGET_DOUBLE_FLOAT, TARGET_SINGLE_FLOAT. (extendsfdf2, extendsfdf2_fpr, truncdfsf2, truncdfsf2_fpr, copysigndf3,fseldfsf4, negdf2, negdf2_fpr, absdf2, absdf2_fpr, nabsdf2_fpr, adddf3, adddf3_fpr, subdf3, subdf3_fpr, muldf3, muldf3_fpr, divdf3, divdf3_fpr, sqrtdf2, smaxdf3, smindf3, movdfcc, *fseldfdf4, floatsidf2, *floatsidf2_internal, floatunssidf2, *floatunssidf2_internal, fix_truncdfsi2, *fix_truncdfsi2_internal, fix_truncdfsi2_internal_gfxopt, fix_truncdfsi2_mfpgpr, fctiwz, btruncdf2, ceildf2, floordf2, rounddf2, floatdidf2, floatsidf_ppc64_mfpgpr, floatsidf_ppc64, floatunssidf_ppc64, fix_truncdfdi2, movdf_hardfloat32, movdf_hardfloat64_mfpgpr, movdf_hardfloat64, extenddftf2_fprs, extenddftf2_internal, trunctfdf2_internal2, fix_trunc_helper, abstf2_internal, movdf_update1, movdf_update2, cmpdf_internal1, cmptf_internal1, *cmptf_internal2): Condition on TARGET_DOUBLE_FLOAT. (aux_truncdfsf2, negsf2, *negsf2, abssf2, *abssf2, addsf3, subsf3, mulsf3, divsf3, sqrtsf2, copysignsf3, smaxsf3, sminsf3, movsfcc, *fselsfsf4, fixuns_truncsfsi2, fix_truncsfsi2, floatunssisf2, btruncsf2, ceilsf2, floorsf2, roundsf2, floatdisf2_internal1, floatdisf2_internal2, *movsf_hardfloat, trunctfsf2_fprs, *movsf_update1, *movsf_update2, *cmpsf_internal1): Condition on TARGET_SINGLE_FLOAT. (divsf3, sqrtsf2, divdf3, divdf3_fpr): Condition on TARGET_SIMPLE_FPU. * config/rs6000/rs6000.opt (-msingle-float): New. (-mdouble-float): New. (-msimple-fpu): New. * doc/invoke.texi (RS/6000 and PowerPC Options): Add -msingle-float, -mdouble-float, -msimple-fpu options. * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Set _SOFT_DOUBLE for -msingle-float. * config.gcc: New config for target=powerpc-xilinx-eabi. From-SVN: r140757
2008-09-29* config/cris/cris.h (IRA_COVER_CLASSES): Define.Hans-Peter Nilsson1-0/+2
From-SVN: r140745
2008-09-28re PR target/37640 (__sync_lock_test_and_set on PPC64 causes ICE)Andrew Pinski1-1/+2
2008-09-28 Andrew Pinski <andrew_pinski@playstation.sony.com> PR target/37640 * config/rs6000/rs6000.c (rs6000_expand_compare_and_swapqhi): Force address to a register before taking the lower part. 2008-09-28 Andrew Pinski <andrew_pinski@playstation.sony.com> PR target/37640 * gcc.c-torture/compile/sync-3.c: New testcase to check that addresses of non zero offset works. From-SVN: r140740
2008-09-28sh.h (OVERRIDE_OPTIONS): Unset flag_dwarf2_cfi_asm for SHmedia.Kaz Kojima1-0/+2
* config/sh/sh.h (OVERRIDE_OPTIONS): Unset flag_dwarf2_cfi_asm for SHmedia. From-SVN: r140739
2008-09-27sh.c (sh_gimplify_va_arg_expr): Use VIEW_CONVERT_EXPR if needed.Kaz Kojima1-1/+3
* config/sh/sh.c (sh_gimplify_va_arg_expr): Use VIEW_CONVERT_EXPR if needed. From-SVN: r140724
2008-09-26mips.h (ISA_HAS_DMUL3, [...]): Change them to yield false with MIPS16.Adam Nemet1-7/+9
* config/mips/mips.h (ISA_HAS_DMUL3, ISA_HAS_BADDU, ISA_HAS_BBIT, ISA_HAS_CINS, ISA_HAS_EXTS, ISA_HAS_SEQ_SNE, ISA_HAS_POP): Change them to yield false with MIPS16. From-SVN: r140714
2008-09-26rs6000.c (rs6000_emit_allocate_stack): Use correct alias set on MEM when ↵Pat Haugen2-4/+36
saving stack pointer. 2008-09-26 Pat Haugen <pthaugen@us.ibm.com> * config/rs6000/rs6000.c (rs6000_emit_allocate_stack): Use correct alias set on MEM when saving stack pointer. * config/rs6000/rs6000.md (allocate_stack): Likewise From-SVN: r140693
2008-09-25i386.md: Check cmp/branch fuse for cmp peephole optimization.H.J. Lu1-4/+5
2008-09-25 H.J. Lu <hongjiu.lu@intel.com> * config/i386/i386.md: Check cmp/branch fuse for cmp peephole optimization. From-SVN: r140673
2008-09-24* config/freebsd.h (HANDLE_PRAGMA_PACK_PUSH_POP): Define.Gerald Pfeifer1-0/+2
From-SVN: r140650
2008-09-24Revert rs6000 change.David Edelsohn6-299/+161
From-SVN: r140646
2008-09-24predicates.md (easy_fp_constant): Single FP consts are easy.Michael J. Eager7-161/+339
2008-09-24 Michael J. Eager <eager@eagercon.com> * config/rs6000/predicates.md (easy_fp_constant): Single FP consts are easy. * config/rs6000/rs6000.c (rs6000_override_options): Move rs6000_init_hard_regno_mode_ok after all options changed. Set rs6000_single_float, rs6000_double_float if TARGET_HARD_FLOAT. (rs6000_handle_option): Process -msingle-float, -mdouble-float, -msimple-fpu flags. Add warning messages if single FP not configured. (rs6000_file_start): Output gnu_attribute for single-float. (legitimate_lo_sum_address_p): Condition on TARGET_DOUBLE_FLOAT. (rs6000_legitimize_address): Likewise. (rs6000_legitimize_reload_address): Likewise. (rs6000_emit_move): Condition on TARGET_DOUBLE_FLOAT, TARGET_SINGLE_FLOAT. (function_arg_advance): Likewise. (function_arg): Likewise. (setup_incoming_varargs): Condition on TARGET_DOUBLE_FLOAT. (rs6000_gimplify_va_arg): Condition on TARGET_DOUBLE_FLOAT, TARGET_SINGLE_FLOAT. (rs6000_split_multireg_move): Condition on TARGET_DOUBLE_FLOAT. (rs6000_emit_prologue): Likewise. (rs6000_function_value): Condition on TARGET_DOUBLE_FLOAT, TARGET_SINGLE_FLOAT. (rs6000_libcall_value): Likewise. * config/rs6000/rs6000.h (TARGET_SINGLE_FLOAT): New default to 1. (TARGET_DOUBLE_FLOAT): New default to 1 (TARGET_SIMPLE_FPU): New default to 0 (TARGET_SINGLE_FPU): New default to 0 (TARGET_SINGLE_FLOAT_MODE): New. (TARGET_DOUBLE_FLOAT_MODE): New. * config/rs6000/singlefp.h: New; redefine TARGET_SINGLE_FLOAT, TARGET_DOUBLE_FLOAT, TARGET_SIMPLE_FPU, TARGET_SINGLE_FPU, UNITS_PER_FP_WORD * config/rs6000/rs6000.md (define_mode_iterator): Condition on TARGET_DOUBLE_FLOAT, TARGET_SINGLE_FLOAT. (extendsfdf2, extendsfdf2_fpr, truncdfsf2, truncdfsf2_fpr, copysigndf3,fseldfsf4, negdf2, negdf2_fpr, absdf2, absdf2_fpr, nabsdf2_fpr, adddf3, adddf3_fpr, subdf3, subdf3_fpr, muldf3, muldf3_fpr, divdf3, divdf3_fpr, sqrtdf2, smaxdf3, smindf3, movdfcc, *fseldfdf4, floatsidf2, *floatsidf2_internal, floatunssidf2, *floatunssidf2_internal, fix_truncdfsi2, *fix_truncdfsi2_internal, fix_truncdfsi2_internal_gfxopt, fix_truncdfsi2_mfpgpr, fctiwz, btruncdf2, ceildf2, floordf2, rounddf2, floatdidf2, floatsidf_ppc64_mfpgpr, floatsidf_ppc64, floatunssidf_ppc64, fix_truncdfdi2, movdf_hardfloat32, movdf_hardfloat64_mfpgpr, movdf_hardfloat64, extenddftf2_fprs, extenddftf2_internal, trunctfdf2_internal2, fix_trunc_helper, abstf2_internal, movdf_update1, movdf_update2, cmpdf_internal1, cmptf_internal1, *cmptf_internal2): Condition on TARGET_DOUBLE_FLOAT. (aux_truncdfsf2, negsf2, *negsf2, abssf2, *abssf2, addsf3, subsf3, mulsf3, divsf3, sqrtsf2, copysignsf3, smaxsf3, sminsf3, movsfcc, *fselsfsf4, fixuns_truncsfsi2, fix_truncsfsi2, floatunssisf2, btruncsf2, ceilsf2, floorsf2, roundsf2, floatdisf2_internal1, floatdisf2_internal2, *movsf_hardfloat, trunctfsf2_fprs, *movsf_update1, *movsf_update2, *cmpsf_internal1): Condition on TARGET_SINGLE_FLOAT. (divsf3, sqrtsf2, divdf3, divdf3_fpr): Condition on TARGET_SIMPLE_FPU. * config/rs6000/rs6000.opt (-msingle-float): New. (-mdouble-float): New. (-msimple-fpu): New. * doc/invoke.texi (RS/6000 and PowerPC Options): Add -msingle-float, -mdouble-float, -msimple-fpu options. * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Set _SOFT_DOUBLE for -msingle-float. * config.gcc: New config for target=powerpc-xilinx-eabi. From-SVN: r140632
2008-09-23constraints.md: New file.Eric Botcazou5-157/+179
* config/sparc/constraints.md: New file. * config/sparc/sparc.md: Include it. * config/sparc/sparc-protos.h (memory_ok_for_ldd): Declare. (sparc_extra_constraint_check): Delete. * config/sparc/sparc.c (register_ok_for_ldd): Minor tweaks. (memory_ok_for_ldd): New predicate. (sparc_extra_constraint_check): Delete. * config/sparc/sparc.h (REG_CLASS_FROM_LETTER): Likewise. (CONST_OK_FOR_LETTER_P): Likewise. (CONST_DOUBLE_OK_FOR_LETTER_P): Likewise. (EXTRA_CONSTRAINT): Likewise. From-SVN: r140619
2008-09-23i386.c: Include cselib.h.Richard Sandiford1-6/+18
gcc/ * config/i386/i386.c: Include cselib.h. (ix86_pic_register_p): New function. (ix86_delegitimize_address): Use it to check for the PIC register. From-SVN: r140611
2008-09-23tm.texi (FIND_BASE_TERM): Expand documentation.Richard Sandiford1-14/+2
gcc/ * doc/tm.texi (FIND_BASE_TERM): Expand documentation. * config/i386/i386.c (ix86_find_base_term): Don't check for SYMBOL_REF and LABEL_REF. From-SVN: r140610
2008-09-23i386.c (ix86_delegitimize_address): Wrap the constant PLUS in a CONST.Richard Sandiford1-1/+1
gcc/ * config/i386/i386.c (ix86_delegitimize_address): Wrap the constant PLUS in a CONST. From-SVN: r140609
2008-09-23i386.c (ix86_function_ok_for_sibcall): Correct check for sibcall support for ↵Kai Tietz1-0/+1
w64. 2008-09-23 Kai Tietz <kai.tietz@onevision.com> *config/i386/i386.c (ix86_function_ok_for_sibcall): Correct check for sibcall support for w64. From-SVN: r140606
2008-09-22re PR target/37593 (-mlong-calls doesn't affect calls to _mcount generated ↵David Daney1-1/+12
with -pg) 2008-09-22 David Daney <ddaney@avtrex.com> PR target/37593 * config/mips/mips.h (FUNCTION_PROFILER): Call _mcount via a register if TARGET_LONG_CALLS. 2008-09-22 David Daney <ddaney@avtrex.com> PR target/37593 * gcc.target/mips/long-calls-pg.c: New test. From-SVN: r140563
2008-09-22mips.h (ISA_HAS_BADDU): New macro.Adam Nemet2-0/+35
* config/mips/mips.h (ISA_HAS_BADDU): New macro. * config/mips/mips.md (*baddu_si_eb, *baddu_si_el, *baddu_di<mode>): New patterns. testsuite/ * gcc.target/mips/octeon-baddu-1.c: New test. From-SVN: r140556
2008-09-22re PR target/37528 (boostrap failure due to configure problems)Danny Smith2-4/+1
PR target/37528 * config/i386/t-cygming (SHLIB_LC): Remove. (SHLIB_LINK): Don't add static objects to SHLIB_IMPLIB * config/i386/t-cygwin (SHLIB_LC): Specify all required libraries. From-SVN: r140541
2008-09-22re PR target/37170 (gcc.dg/weak/weak-1.c)Hans-Peter Nilsson1-0/+24
PR middle-end/37170 PR middle-end/37280 * final.c (mark_symbol_ref_as_used): New helper function. (output_operand): Instead of just looking inside MEMs for SYMBOL_REFs, use new helper function and for_each_rtx. * varasm.c (assemble_external): Move #ifndef ASM_OUTPUT_EXTERNAL to after weak-handling. Don't mark decls with TREE_STATIC as weak. Make head comment more general. * config/darwin.c (machopic_output_indirection): Handle weak references here, like in assemble_external. From-SVN: r140539
2008-09-21sparc-protos.h (gen_compare_operator): Declare.Eric Botcazou3-384/+215
* config/sparc/sparc-protos.h (gen_compare_operator): Declare. (sparc_emit_float_lib_cmp): Change return type. * config/sparc/sparc.c (gen_compare_reg): Add comment about TFmode. (gen_compare_operator): New function. (sparc_emit_float_lib_cmp): Return the new operator to be used in the comparison sequence. Minor tweaks. * config/sparc/sparc.md (seq, sne, sgt, slt, sge, sle): Assert that the final operator and the result of sparc_emit_float_lib_cmp match for software TFmode; use emit_insn in lieu of emit_jump_insn. (beq, bne, bgt, blt, bge, ble, bunordered, bordered, bungt, bunlt, buneq, bunge, bunle, bltgt): Assert that the final operator and the result of sparc_emit_float_lib_cmp match for software TFmode. (movqicc, movhicc, movsicc, movdicc): Merge into... (mov<I:mode>cc): ...this. (movsfcc, movdfcc, movtfcc): Merge into... (mov<F:mode>cc): ...this. (movqi_cc_sp64, movhi_cc_sp64, movsi_cc_sp64, movdi_cc_sp64): Merge into... (mov<I:mode>_cc_v9): ...this. (movdi_cc_sp64_trunc): Delete. (movqi_cc_reg_sp64, movhi_cc_reg_sp64, movsi_cc_reg_sp64, movdi_cc_reg_sp64): Merge into... (mov<I:mode>_cc_reg_sp64): ...this. (movsf_cc_sp64): Rename into... (movsf_cc_v9): ...this. (movdf_cc_sp64): Rename into... (movdf_cc_v9): ...this. (movtf_cc_hq_sp64): Rename into... (movtf_cc_hq_v9): ...this. (movtf_cc_sp64): Rename into... (movtf_cc_v9): ...this. Adjust for renaming of movdf_cc_sp64. From-SVN: r140530
2008-09-21mips.h (TUNE_OCTEON): New macro.Adam Nemet4-1/+95
* config/mips/mips.h (TUNE_OCTEON): New macro. * config/mips/mips.c (mips_issue_rate): Return 2 for Octeon. (mips_multipass_dfa_lookahead): Return 2 for Octeon. * config/mips/octeon.md: New file. * config/mips/mips.md: Include octeon.md. Restore semi-alphabetical order of include files. From-SVN: r140521
2008-09-20re PR target/37571 (Performance regression due to compare/branch fuse ↵H.J. Lu1-70/+0
optimization) 2008-09-20 H.J. Lu <hongjiu.lu@intel.com> PR target/37571 * config/i386/i386.md (*jcc_fused_1): Removed. (*jcc_fused_2): Likewise. (*jcc_fused_3): Likewise. (*jcc_fused_4): Likewise. From-SVN: r140514
2008-09-20* config/xtensa/xtensa.md (reload<mode>_literal): Handle MEM operands.Bob Wilson1-5/+14
From-SVN: r140509
2008-09-19configure.ac: Add HAVE_AS_TLS check for Xtensa.Bob Wilson5-29/+338
* configure.ac: Add HAVE_AS_TLS check for Xtensa. * config/xtensa/predicates.md (tls_symbol_operand): New. * config/xtensa/xtensa.c (TARGET_HAVE_TLS): Define. (TARGET_CANNOT_FORCE_MEM): Define. (xtensa_tls_symbol_p): New. (xtensa_emit_move_sequence): Check for and legitimize TLS addresses. (xtensa_legitimate_address_p): Disallow constant pool TLS references. (xtensa_tls_module_base): New. (xtensa_call_tls_desc): New. (xtensa_legitimize_tls_address): New. (xtensa_legitimize_address): Handle TLS symbols. (xtensa_tls_referenced_p_1): New. (xtensa_tls_referenced_p): New. (xtensa_output_addr_const_extra): Handle UNSPEC_TPOFF and UNSPEC_DTPOFF. (XTENSA_BUILTIN_THREAD_POINTER): New. (XTENSA_BUILTIN_SET_THREAD_POINTER): New. (xtensa_init_builtins): Set NOTHROW and READONLY for umulsidi3 builtin. Add declarations for __builtin_thread_pointer and __builtin_set_thread_pointer. (xtensa_fold_builtin): Recognize new builtins. (xtensa_expand_builtin): Expand new builtins. * config/xtensa/xtensa.h (XCHAL_HAVE_THREADPTR): Define default value. (TARGET_THREADPTR): Define. (HAVE_AS_TLS): Define default value. (LEGITIMATE_CONSTANT_P): Disallow TLS references. * config/xtensa/xtensa.md (UNSPEC_TPOFF, UNSPEC_DTPOFF): New. (UNSPEC_TLS_FUNC, UNSPEC_TLS_ARG, UNSPEC_TLS_CALL, UNSPEC_TP): New. (UNSPECV_SET_TP): New. (sym_TPOFF, sym_DTPOFF): New. (load_tp, set_tp, tls_func, tls_arg, tls_call): New. * config/xtensa/xtensa-protos.h (xtensa_tls_referenced_p): Declare. * configure: Regenerated. From-SVN: r140482
2008-09-18re PR target/37394 (Segfault in ia64_variable_issue with -O -fschedule-insns2)H.J. Lu1-7/+3
gcc/ 2008-09-18 H.J. Lu <hongjiu.lu@intel.com> PR target/37394 * config/ia64/ia64.c (ia64_optimization_options): Move checking and setting flag_schedule_insns_after_reload and ia64_flag_schedule_insns2 back to ... (ia64_override_options): Here. gcc/testsuite/ 2008-09-18 H.J. Lu <hongjiu.lu@intel.com> PR target/37394 * g++.dg/other/pr37394.C: New. From-SVN: r140475
2008-09-18sol2.h (WIDEST_HARDWARE_FP_SIZE): Move to...Eric Botcazou2-3/+4
* config/sparc/sol2.h (WIDEST_HARDWARE_FP_SIZE): Move to... * config/sparc/sparc.h (WIDEST_HARDWARE_FP_SIZE): ...here. From-SVN: r140458
2008-09-18frv.h (IRA_COVER_CLASSES): Define.Nick Clifton4-12/+79
* config/frv/frv.h (IRA_COVER_CLASSES): Define. (SECONDARY_INPUT_RELOAD_CLASS): Omit unused argument in call to frv_secondary_reload_class. (SECONDARY_OUTPUT_RELOAD_CLASS): Likewise. * config/frv/frv.c (TARGET_SECONDARY_RELOAD): Define. (frv_secondary_reload_class): Omit unused parameter. (frv_secondary_reload): New function. Handle the case when secondary_reload_class() is called before the reload_(in|out) _optabs have been initialised. * config/frv/frv-protos.h (frv_secondary_reload_class): Omit unused parameter. * config/frv/frv.md: Define an exclusion set between fr550_m0 and fr550_f0. From-SVN: r140452
2008-09-15sh.md (movsf_ie): Fix length for TARGET_SH2A.Kaz Kojima1-3/+6
* config/sh/sh.md (movsf_ie): Fix length for TARGET_SH2A. From-SVN: r140382
2008-09-15rs6000.md (floatsidf2): Rewrite PowerPC64 case to use gen_floatdidf2 directly.Andrew Pinski1-56/+4
2008-09-15 Andrew Pinski <andrew_pinski@playstation.sony.com> * config/rs6000/rs6000.md (floatsidf2): Rewrite PowerPC64 case to use gen_floatdidf2 directly. (floatunssidf2): Likewise. (floatsidf_ppc64_mfpgpr): Remove. (floatsidf_ppc64): Remove. (floatunssidf_ppc64): Remove. From-SVN: r140381
2008-09-14config.host: Add x-aix to host_xmake_file.David Edelsohn2-3/+3
* config.host: Add x-aix to host_xmake_file. * config/rs6000/t-aix52: Do not override LDFLAGS. * config/rs6000/x-aix: New file. From-SVN: r140361
2008-09-14re PR target/19636 (Can't compile large switch statement)Andy Hutchinson2-4/+3
PR target/19636 PR target/24894 PR target/31644 PR target/31786 * config/avr/avr.c (legitimate_address_p): Fix problem where subreg is not recognized as a valid register usage. Allow REG_X to be used as a base pointer. * config/avr/avr.h (LEGITIMIZE_RELOAD_ADDRESS): Remove code that forces a reload when using a base register. From-SVN: r140360
2008-09-13cygming-crtend.c (register_frame_ctor): If DEFAULT_USE_CXA_ATEXIT, register ↵Danny Smith1-3/+10
__gcc_deregister_frame directly with atexit. * config/i386/cygming-crtend.c (register_frame_ctor): If DEFAULT_USE_CXA_ATEXIT, register __gcc_deregister_frame directly with atexit. (deregister_frame_ctor): Rename to ... (deregister_frame_dtor): Use to call __gcc_deregister_frame if !DEFAULT_USE_CXA_ATEXIT. From-SVN: r140351
2008-09-13i386.c (ix86_expand_movmem, [...]): Avoid processing too many bytes on ↵Jan Hubicka1-0/+38
misalligned blocks. * i386.c (ix86_expand_movmem, ix86_expand_movstr): Avoid processing too many bytes on misalligned blocks. From-SVN: r140348
2008-09-12re PR target/37466 ([AVR] avr-gcc generating incorrect assembly for ↵Anatoly Sokolov1-2/+3
expression with the long constant operands) PR target/37466 * config/avr/avr.md (movsi_lreg_const peephole2): Add match_dup for scratch register after 'set' pattern. From-SVN: r140321
2008-09-12spu.c (spu_override_options): Default to -mno-safe-hints when building for ↵Ulrich Weigand1-0/+10
the celledp architecture. * config/spu/spu.c (spu_override_options): Default to -mno-safe-hints when building for the celledp architecture. From-SVN: r140316
2008-09-11i386.h: Fix whitespace issues.Uros Bizjak1-17/+18
* config/i386/i386.h: Fix whitespace issues. From-SVN: r140294
2008-09-11* config/m68k/m68k.h (IRA_COVER_CLASSES): Define.Andreas Schwab1-0/+5
From-SVN: r140275
2008-09-10re PR target/36904 (vector context sensitive keyword vs macros)Jakub Jelinek1-14/+25
PR target/36904 * config/rs6000/rs6000-c.c (rs6000_macro_to_expand): Return NULL instead of tok->val.node if not expanding to something else. Handle intervening CPP_PADDING tokens. (altivec_categorize_keyword): Remove unneeded comparisons. * gcc.target/powerpc/altivec-27.c: New test. From-SVN: r140247
2008-09-10re PR target/37434 (ICE in extract_insn, at recog.c:2027)H.J. Lu1-2/+11
gcc/ 2008-09-10 H.J. Lu <hongjiu.lu@intel.com> PR target/37434: * config/i386/i386.c (ix86_expand_vector_init_interleave): Force the even element into register. (ix86_expand_vector_init_general): Don't use ix86_expand_vector_init_interleave on V16QImode and V8HImode if we can't move from GPR to SSE register directly. gcc/testsuite/ 2008-09-10 H.J. Lu <hongjiu.lu@intel.com> PR target/37434: * gcc.target/i386/pr37434-1.c: New. * gcc.target/i386/pr37434-2.c: Likewise. * gcc.target/i386/pr37434-3.c: Likewise. * gcc.target/i386/pr37434-4.c: Likewise. * gcc.target/i386/sse2-set-v8hi-1a.c: Likewise. * gcc.target/i386/sse2-set-v8hi-2a.c: Likewise. * gcc.target/i386/sse4_1-set-v16qi-1a.c: Likewise. * gcc.target/i386/sse4_1-set-v16qi-2a.c: Likewise. * gcc.target/i386/sse4_1-set-v16qi-3a.c: Likewise. From-SVN: r140231
2008-09-10bfin.c (workaround_speculation): Correct algorithm to not lose track of the ↵Bernd Schmidt2-30/+50
number of NOPs needed. * config/bfin/bfin.c (workaround_speculation): Correct algorithm to not lose track of the number of NOPs needed. Number of NOPs needed for sync vs. loads workaround was switched; corrected. Run second pass for all workarounds. No NOPs needed after call insns. Change second pass to use find_next_insn_start and find_load helpers in order to properly detect parallel insns. * config/bfin/bfin.md (cbranch_with_nops): Increase length. From-SVN: r140230
2008-09-10i386.md (SWI32): New mode iterator.Jakub Jelinek1-8/+11
* config/i386/i386.md (SWI32): New mode iterator. (jcc_fused_1, jcc_fused_2, jcc_fused_3, jcc_fused_4): Use it instead of SWI. From-SVN: r140189
2008-09-09re PR target/37438 (ICE in extract_insn, at recog.c:2027 for i{4,5}86)Jakub Jelinek1-1/+1
PR target/37438 * config/i386/i386.md (zero_extendqihi2_movzbl): Enable when optimizing for size, not speed. * gcc.dg/pr37438.c: New test. From-SVN: r140167
2008-09-09sol2.h (REGISTER_TARGET_PRAGMAS): Move ...Rainer Orth3-6/+9
* config/sol2.h (REGISTER_TARGET_PRAGMAS): Move ... * config/i386/sol2.h (REGISTER_SUBTARGET_PRAGMAS): ... here. * config/sparc/sol2.h (REGISTER_TARGET_PRAGMAS): ... and here. From-SVN: r140157
2008-09-09bfin.c (n_regs_to_save): New static variable.Bernd Schmidt1-49/+138
* config/bfin/bfin.c (n_regs_to_save): New static variable. (push_multiple_operation, pop_multiple_operation): Set it. (workaround_rts_anomaly): New function. (workaround_speculation): New function, broken out of bfin_reorg. (bfin_reorg): Call the new functions. From-SVN: r140146
2008-09-09* config/v850/v850.md (return): Restore frame size restriction.Nick Clifton1-1/+1
From-SVN: r140139
2008-09-08re PR target/36609 (AVR wrong code using incorrect RTL for test reversal ↵Andy Hutchinson2-7/+26
pattern) PR target/36609 * config/avr/avr.c (avr_reorg): Create RTL for reversed compare with zero. * config/avr/avr.md (QISI) : Define mode iterator. (negated_tst<mode>) : Redefine as split using mode macro. (reversed_tstqi): Define insn as reversed compare with zero. (reversed_tsthi): Ditto. (reversed_tstsi): Ditto. From-SVN: r140124
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