| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-09-30 | rs6000: Adjust altivec dot-product backend patterns | Victor Do Nascimento | 1 | -2/+2 |
| 2024-09-17 | PR 89213: Add better support for shifting vectors with 64-bit elements | Michael Meissner | 2 | -0/+114 |
| 2024-09-10 | Pass host specific ABI opts from mkoffload. | Prathamesh Kulkarni | 1 | -2/+2 |
| 2024-09-06 | rs6000,extend and document built-ins vec_test_lsbb_all_ones and vec_test_lsbb... | Carl Love | 1 | -2/+10 |
| 2024-08-29 | Use std::unique_ptr for optinfo_item | David Malcolm | 1 | -0/+1 |
| 2024-08-23 | rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415] | Peter Bergner | 2 | -4/+6 |
| 2024-08-23 | optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495]. | Robin Dapp | 2 | -2/+2 |
| 2024-08-21 | rs6000: Remove "+" constraint modifier from *vsx_le_perm_store_* insns | Kewen Lin | 1 | -5/+5 |
| 2024-08-21 | rs6000: Fix vsx_le_perm_store_* splitters for !reload_completed | Kewen Lin | 1 | -11/+10 |
| 2024-08-15 | rs6000: Add TARGET_FLOAT128_HW guard for quad-precision insns | Haochen Gui | 2 | -13/+16 |
| 2024-08-15 | rs6000: Implement optab_isnormal for SFDF and IEEE128 | Haochen Gui | 1 | -0/+18 |
| 2024-08-15 | rs6000: Implement optab_isfinite for SFDF and IEEE128 | Haochen Gui | 1 | -0/+15 |
| 2024-08-15 | rs6000: Implement optab_isinf for SFDF and IEEE128 | Haochen Gui | 4 | -45/+58 |
| 2024-08-12 | rs6000: ROP - Do not disable shrink-wrapping for leaf functions [PR114759] | Peter Bergner | 2 | -4/+5 |
| 2024-08-07 | rs6000, Add new overloaded vector shift builtin int128 variants | Carl Love | 3 | -3/+55 |
| 2024-08-06 | rs6000: Add const_vector into any_operand predicate | Haochen Gui | 1 | -1/+1 |
| 2024-07-30 | rs6000: Relax some FLOAT128 expander condition for FLOAT128_IEEE_P [PR105359] | Kewen Lin | 1 | -6/+12 |
| 2024-07-30 | rs6000: Use standard name uabd for absdu insns | Kewen Lin | 2 | -18/+13 |
| 2024-07-29 | rs6000, add comment to VEC_IC definition | Carl Love | 1 | -1/+2 |
| 2024-07-25 | rs6000, remove built-ins __builtin_vsx_set_1ti, __builtin_vsx_set_2df, __buil... | Carl Love | 3 | -81/+10 |
| 2024-07-25 | rs6000, Remove __builtin_vec_set_v1ti, __builtin_vec_set_v2df, __builtin_vec_... | Carl Love | 2 | -53/+0 |
| 2024-07-25 | rs6000, remove __builtin_vsx_xvcmp* built-ins | Carl Love | 1 | -9/+0 |
| 2024-07-24 | optabs/rs6000: Rename iorc and andc to iorn and andn | Andrew Pinski | 3 | -25/+25 |
| 2024-07-23 | report message for operator %a on unaddressible operand | Jiufu Guo | 1 | -1/+6 |
| 2024-07-23 | rs6000: Update option set in rs6000_inner_target_options [PR115713] | Kewen Lin | 1 | -1/+2 |
| 2024-07-23 | rs6000: Consider explicitly set options in target option parsing [PR115713] | Kewen Lin | 1 | -2/+5 |
| 2024-07-23 | rs6000: Escalate warning to error for VSX with explicit no-altivec etc. | Kewen Lin | 1 | -18/+23 |
| 2024-07-22 | Add -mcpu=power11 support. | Michael Meissner | 16 | -87/+127 |
| 2024-07-18 | rs6000: Fix .machine cpu selection w/ altivec [PR97367] | René Rebe | 1 | -1/+4 |
| 2024-07-17 | rs6000: Remove redundant guard for float128 mode pattern | Haochen Gui | 1 | -58/+57 |
| 2024-07-17 | rs6000: Change optab for ibm128 and ieee128 conversion | Kewen Lin | 1 | -6/+6 |
| 2024-07-17 | rs6000: Make all 128 bit scalar FP modes have 128 bit precision [PR112993] | Kewen Lin | 6 | -108/+41 |
| 2024-07-16 | rs6000: Error on CPUs and ABIs that don't support the ROP protection insns [P... | Peter Bergner | 3 | -18/+20 |
| 2024-07-16 | rs6000: ROP - Emit hashst and hashchk insns on Power8 and later [PR114759] | Peter Bergner | 2 | -6/+6 |
| 2024-07-12 | rs6000: Remove vcond{,u} expanders | Kewen Lin | 3 | -162/+1 |
| 2024-07-09 | rs6000, remove vector set and vector init built-ins. | Carl Love | 3 | -100/+14 |
| 2024-07-09 | rs6000, remove __builtin_vsx_xvcmpeqsp_p built-in | Carl Love | 1 | -3/+0 |
| 2024-07-09 | rs6000, extend vec_xxpermdi built-in for __int128 args | Carl Love | 1 | -0/+4 |
| 2024-07-09 | rs6000, remove __builtin_vsx_xvnegdp and __builtin_vsx_xvnegsp built-ins | Carl Love | 1 | -6/+0 |
| 2024-07-09 | rs6000, remove __builtin_vsx_vperm_* built-ins | Carl Love | 1 | -33/+0 |
| 2024-07-09 | rs6000, remove the vec_xxsel built-ins, they are duplicates | Carl Love | 1 | -30/+0 |
| 2024-07-09 | rs6000, add overloaded vec_sel with int128 arguments | Carl Love | 2 | -6/+12 |
| 2024-07-09 | rs6000, remove duplicated built-ins of vecmergl and vec_mergeh | Carl Love | 3 | -61/+0 |
| 2024-07-09 | rs6000, Remove redundant vector float/double type conversions | Carl Love | 1 | -12/+0 |
| 2024-07-09 | rs6000, extend the current vec_{un,}signed{e,o} built-ins | Carl Love | 3 | -4/+102 |
| 2024-07-09 | rs6000, fix error in unsigned vector float to unsigned int built-in definitions | Carl Love | 1 | -6/+6 |
| 2024-07-09 | rs6000, Remove __builtin_vsx_xvcv{sp{sx,u}ws,dpuxds_uns} | Carl Love | 1 | -15/+0 |
| 2024-07-09 | rs6000, Remove __builtin_vsx_cmple* builtins | Carl Love | 2 | -43/+0 |
| 2024-07-08 | rs6000: load high and low part of 128bit vector independently [PR110040] | Jeevitha | 1 | -0/+17 |
| 2024-07-08 | rs6000: Replace orc with iorc [PR115659] | Kewen Lin | 3 | -14/+14 |
