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2018-03-15rs6000: Fix for the previous abi_v4_pass_in_fpr changeSegher Boessenkool1-2/+2
I was a bit over-enthusiastic, we still support xilinxfp. * config/rs6000/rs6000.c (abi_v4_pass_in_fpr): Add back the TARGET_DOUBLE_FLOAT and TARGET_SINGLE_FLOAT conditions on the DFmode resp. SFmode cases. From-SVN: r258557
2018-03-14re PR target/84422 (ICE on various builtin test functions when compiled with ↵Carl Love3-18/+18
-mcpu=power7) gcc/ChangeLog: 2018-03-14 Carl Love <cel@us.ibm.com> PR target/84422 * config/rs6000/rs6000-builtin.def: Change expansion for VMULESW to BU_P8V_AV_2. Change expansion for VMULEUW to BU_P8V_AV_2. * config/rs6000/rs6000.c: Change ALTIVEC_BUILTIN_VMULESW to P8V_BUILTIN_VMULESW. Change ALTIVEC_BUILTIN_VMULEUW to P8V_BUILTIN_VMULEUW. Change ALTIVEC_BUILTIN_VMULOSW to P8V_BUILTIN_VMULOSW. Change ALTIVEC_BUILTIN_VMULOUW to P8V_BUILTIN_VMULOUW. * config/rs6000/rs6000-c.c: Change ALTIVEC_BUILTIN_VMULESW to P8V_BUILTIN_VMULESW. Change ALTIVEC_BUILTIN_VMULEUW to P8V_BUILTIN_VMULEUW. Change ALTIVEC_BUILTIN_VMULOSW to P8V_BUILTIN_VMULOSW. Change ALTIVEC_BUILTIN_VMULOUW to P8V_BUILTIN_VMULOUW. From-SVN: r258539
2018-03-14rs6000-c.c: Add macro definitions for ALTIVEC_BUILTIN_VEC_PERMXOR.Carl Love5-0/+38
gcc/ChangeLog: 2018-03-14 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-c.c: Add macro definitions for ALTIVEC_BUILTIN_VEC_PERMXOR. * config/rs6000/rs6000.h: Add #define for vec_permxor builtin. * config/rs6000/rs6000-builtin.def: Add macro expansions for VPERMXOR. * config/rs6000/altivec.md (altivec_vpermxor): New define expand. * config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p): Add case UNSPEC_VPERMXOR. * config/doc/extend.texi: Add prototypes for vec_permxor. gcc/testsuite/ChangeLog: 2018-03-14 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-7-runnable.c: New test file. From-SVN: r258530
2018-03-13re PR target/84743 (default widths for parallel reassociation now hurt ↵Aaron Sawdey1-1/+1
rather than help) 2018-03-13 Aaron Sawdey <acsawdey@linux.vnet.ibm.com> PR target/84743 * config/rs6000/rs6000.c (rs6000_reassociation_width): Disable parallel reassociation for int modes. From-SVN: r258495
2018-03-12rs6000: sysv: Don't pass SFmode in varargs in FPRsSegher Boessenkool1-6/+6
This makes the float32-basic.c testcase work on sysv (32-bit Linux). "float" is promoted to "double" for varargs. The ABI also only defines the use of double precision in varargs. But _Float32 is not promoted. Since there is no way of passing single-precision float in FPRs we should pass SFmode in GPRs (or memory) instead. This is similar to the 64-bit ABI. From-SVN: r258454
2018-03-09re PR target/83969 (ICE in final_scan_insn, at final.c:2997 (error: could ↵Peter Bergner2-12/+11
not split insn) for powerpc targets) gcc/ PR target/83969 * config/rs6000/rs6000.c (rs6000_offsettable_memref_p): New prototype. Add strict argument and use it. (rs6000_split_multireg_move): Update for new strict argument. (mem_operand_gpr): Disallow all non-offsettable addresses. * config/rs6000/rs6000.md (*movdi_internal64): Use YZ constraint. gcc/testsuite/ PR target/83969 * gcc.target/powerpc/pr83969.c: New test. From-SVN: r258400
2018-03-09re PR target/84772 (powerpc-spe: Spurious "is used uninitialized" warning, ↵Jakub Jelinek1-0/+1
or possibly incorrect codegen for va_arg(long double)) PR target/84772 * config/rs6000/rs6000.c (rs6000_gimplify_va_arg): Mark va_arg_tmp temporary TREE_ADDRESSABLE before gimplification of BUILT_IN_MEMCPY. * config/powerpcspe/powerpcspe.c (rs6000_gimplify_va_arg): Likewise. * gcc.dg/pr84772.c: New test. From-SVN: r258399
2018-03-07rs6000: -mreadonly-in-sdata (PR82411)Segher Boessenkool2-0/+9
This adds a new option -mreadonly-in-sdata (on by default) that controls whether readonly data can be put in sdata. (For EABI this does nothing, readonly data is put in sdata2 as usual). PR target/82411 * config/rs6000/rs6000.c (rs6000_elf_in_small_data_p): Don't put readonly data in sdata, if that is disabled. * config/rs6000/sysv4.opt (mreadonly-in-sdata): New option. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mreadonly-in-sdata option. gcc/testsuite/ PR target/82411 * gcc.target/powerpc/ppc-sdata-2.c: Skip if -mno-readonly-in-sdata. From-SVN: r258340
2018-03-06rs6000-builtin.def (rs6000_speculation_barrier): Rename to ↵Bill Schmidt2-2/+2
ppc_speculation_barrier. [gcc] 2018-03-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000-builtin.def (rs6000_speculation_barrier): Rename to ppc_speculation_barrier. * config/rs6000/rs6000.c (rs6000_init_builtins): Rename builtin to __builtin_ppc_speculation_barrier. [gcc/testsuite] 2018-03-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/spec-barr-1.c: Change called function name to __builtin_ppc_speculation_barrier. From-SVN: r258268
2018-03-05rs6000: Don't align tiny loops to 32 bytes for POWER9Segher Boessenkool1-2/+1
For POWER4..POWER8 we align loops of 5..8 instructions to 32 bytes (instead of to 16 bytes) because that executes faster. This is no longer the case on POWER9, so we can just as well only align to 16 bytes. * config/rs6000/rs6000.c (rs6000_loop_align): Don't align tiny loops to 32 bytes when compiling for POWER9. From-SVN: r258260
2018-03-05re PR target/84264 (ICE in rs6000_emit_le_vsx_store, at ↵Peter Bergner1-2/+9
config/rs6000/rs6000.c:10367 starting with r256656) gcc/ PR target/84264 * config/rs6000/vector.md (mov<mode>): Disallow altivec memory operands. gcc/testsuite/ PR target/84264 * g++.dg/pr84264.C: New test. From-SVN: r258251
2018-02-28config.gcc (powerpc-ibm-aix7.1.*): New stanza.David Edelsohn2-1/+236
* config.gcc (powerpc-ibm-aix7.1.*): New stanza. (powerpc-ibm-aix[789]*): Default to AIX 7.2. * config/rs6000/aix71.h (TARGET_DEFAULT): Revert to Power4 ISA. * config/rs6000/aix72.h: New file. From-SVN: r258082
2018-02-25rs6000: Warn for deprecated optionsSegher Boessenkool1-4/+4
Some command-line options have been deprecated for a long time. This patch adds a warning for them, so that we can remove them in GCC 9 without surprising any users. * config/rs6000/rs6000.opt (mvrsave=no, mvrsave=yes, isel=no, isel=yes): Warn for these deprecated options. From-SVN: r257975
2018-02-23* config/rs6000/aix71.h (TARGET_DEFAULT): Change to ISA_2_5_MASKS_EMBEDDED.David Edelsohn1-1/+5
From-SVN: r257944
2018-02-23rs6000-builtin.def: Change VSIGNED2 and VUNSIGNED2 macro expansions from ↵Carl Love2-7/+7
BU_VSX_2 to BU_P8V_VSX_2... gcc/ChangeLog: 2018-02-23 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def: Change VSIGNED2 and VUNSIGNED2 macro expansions from BU_VSX_2 to BU_P8V_VSX_2 and BU_VSX_OVERLOAD_2 to BU_P8V_OVERLOAD_2. * config/rs6000/rs6000-c.c: Change VSX_BUILTIN_VEC_VSIGNED2 to P8V_BUILTIN_VEC_VSIGNED2. Change VSX_BUILTIN_VEC_VUNSIGNED2 to P8V_BUILTIN_VEC_VUNSIGNED2. gcc/testsuite/ChangeLog: 2018-02-23 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-3-runnable.c: Move tests for vec_float2, vec_signed2 and vec_unsigned2 to new Power 8 test file. * gcc.target/powerpc/builtins-3-runnable-p8.c: New test file for Power 8 tests. From-SVN: r257937
2018-02-22rs6000: Delete meaningless arguments to define_{expand,split,peephole2}Segher Boessenkool7-834/+834
This removes the (usually empty) constraint arguments to define_expand, define_split, and define_peephole2: this argument is meaningless and just noise. * config/rs6000/altivec.md: Delete contraint arguments to define_expand, define_split, and define_peephole2, and in define_insn_and_split if always unused. * config/rs6000/darwin.md: Ditto. * config/rs6000/dfp.md: Ditto. * config/rs6000/rs6000.md: Ditto. * config/rs6000/sync.md: Ditto. * config/rs6000/vector.md: Ditto. * config/rs6000/vsx.md: Ditto. From-SVN: r257890
2018-02-22rs6000: Use brace blocks in define_insnSegher Boessenkool5-388/+249
This patch changes the remaining cases in our machine description files to use brace blocks instead of double-quoted strings as the output control string. This increases readability by making the blocks look more like normal C code, mostly because backslash quoting is no longer needed. It also removes such quoting where it was still there (usually harmless but always confusing). and it writes "\n\t" as "\;" in one place where we didn't already. * config/rs6000/altivec.md: Write output control strings as braced blocks instead of double-quoted strings. * config/rs6000/darwin.md: Ditto. * config/rs6000/rs6000.md: Ditto. * config/rs6000/vector.md: Ditto. * config/rs6000/vsx.md: Ditto. From-SVN: r257889
2018-02-19rs6000-builtin.def: Change NEG macro expansions from BU_ALTIVEC_A to ↵Carl Love2-22/+23
BU_P8V_AV_1 and... gcc/ChangeLog: 2018-02-19 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def: Change NEG macro expansions from BU_ALTIVEC_A to BU_P8V_AV_1 and BU_ALTIVEC_OVERLOAD_1 to BU_P8V_OVERLOAD_1. * config/rs6000/rs6000-c.c: Change ALTIVEC_BUILTIN_VEC_NEG to P8V_BUILTIN_VEC_NEG. gcc/testsuite/ChangeLog: 2018-02-19 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/fold-vec-neg-int.p7.c: Remove test file. From-SVN: r257812
2018-02-18Do not mess with rs6000_{single,double}_float (PR68028)Segher Boessenkool1-19/+0
For e500 family cores we do some questionable things with those flags, which does not work with LTO. So don't. * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't handle rs6000_single_float and rs6000_double_float specially for e500 family CPUs. From-SVN: r257790
2018-02-16rs6000-builtin.def: Add BU_P8V_VSX_2 macro definition.Carl Love2-8/+18
gcc/ChangeLog: 2018-02-16 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def: Add BU_P8V_VSX_2 macro definition. Change FLOAT2 expansions from BU_VSX_2 to BU_P8V_VSX_2 and from BU_VSX_OVERLOAD_2 to BU_P8V_OVERLOAD_2. * config/rs6000/rs6000-c.c: Changed macro VSX_BUILTIN_VEC_FLOAT2 expansion to P8V_BUILTIN_VEC_FLOAT2. From-SVN: r257752
2018-02-16altivec.h: Remove vec_vextract4b and vec_vinsert4b.Carl Love5-124/+0
gcc/ChangeLog: 2018-02-16 Carl Love <cel@us.ibm.com> * config/rs6000/altivec.h: Remove vec_vextract4b and vec_vinsert4b. * config/rs6000/rs6000-builtin.def: Remove macro expansion for VEXTRACT4B, VINSERT4B, VINSERT4B_DI and VEXTRACT4B. * config/rs6000/rs6000.c: Remove case statements for P9V_BUILTIN_VEXTRACT4B, P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, and P9V_BUILTIN_VEC_VINSERT4B. * config/rs6000/rs6000-c.c (altivec_expand_builtin): Remove entries for P9V_BUILTIN_VEC_VEXTRACT4B and P9V_BUILTIN_VEC_VINSERT4B. * config/rs6000/vsx.md: * doc/extend.texi: Remove vec_vextract4b, non ABI definitions for vec_insert4b. gcc/testsuite/ChangeLog: 2018-02-16 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/p9-vinsert4b-1.c: Remove test file for non-ABI tests. * gcc.target/powerpc/p9-vinsert4b-2.c: Remove test file for non-ABI tests. From-SVN: r257748
2018-02-16altivec.h: Add builtin names vec_extract4b vec_insert4b.Carl Love5-0/+57
gcc/ChangeLog: 2018-02-16 Carl Love <cel@us.ibm.com> * config/rs6000/altivec.h: Add builtin names vec_extract4b vec_insert4b. * config/rs6000/rs6000-builtin.def: Add INSERT4B and EXTRACT4B definitions. * config/rs6000/rs6000-c.c: Add the definitions for P9V_BUILTIN_VEC_EXTRACT4B and P9V_BUILTIN_VEC_INSERT4B. * config/rs6000/rs6000.c (altivec_expand_builtin): Add P9V_BUILTIN_EXTRACT4B and P9V_BUILTIN_INSERT4B case statements. * config/rs6000/vsx.md: Add define_insn extract4b. Add define_expand definition for insert4b and define insn *insert3b_internal. * doc/extend.texi: Add documentation for vec_extract4b. gcc/testsuite/ChangeLog: 2018-02-16 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-7-p9-runnable.c: New runnable test file for the ABI definitions for vec_extract4b and vec_insert4b. From-SVN: r257747
2018-02-14rs6000.c (rs6000_option_override_internal): Issue warning message if user ↵Kelvin Nilsen1-0/+7
requests -maltivec=be. gcc/ChangeLog: 2018-02-14 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/rs6000.c (rs6000_option_override_internal): Issue warning message if user requests -maltivec=be. * doc/invoke.texi: Document deprecation of -maltivec=be. gcc/testsuite/ChangeLog: 2018-02-14 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.dg/vmx/extract-be-order.c: Disable -maltivec=be warning so this test case still works ok. * gcc.dg/vmx/extract-vsx-be-order.c: Likewise. * gcc.dg/vmx/insert-be-order.c: Likewise. * gcc.dg/vmx/insert-vsx-be-order.c: Likewise. * gcc.dg/vmx/ld-be-order.c: Likewise. * gcc.dg/vmx/ld-vsx-be-order.c: Likewise. * gcc.dg/vmx/lde-be-order.c: Likewise. * gcc.dg/vmx/ldl-be-order.c: Likewise. * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise. * gcc.dg/vmx/merge-be-order.c: Likewise. * gcc.dg/vmx/merge-vsx-be-order.c: Likewise. * gcc.dg/vmx/mult-even-odd-be-order.c: Likewise. * gcc.dg/vmx/pack-be-order.c: Likewise. * gcc.dg/vmx/perm-be-order.c: Likewise. * gcc.dg/vmx/splat-be-order.c: Likewise. * gcc.dg/vmx/splat-vsx-be-order.c: Likewise. * gcc.dg/vmx/st-be-order.c: Likewise. * gcc.dg/vmx/st-vsx-be-order.c: Likewise. * gcc.dg/vmx/ste-be-order.c: Likewise. * gcc.dg/vmx/stl-be-order.c: Likewise. * gcc.dg/vmx/stl-vsx-be-order.c: Likewise. * gcc.dg/vmx/sum2s-be-order.c: Likewise. * gcc.dg/vmx/unpack-be-order.c: Likewise. * gcc.dg/vmx/vsums-be-order.c: Likewise. * gcc.target/powerpc/vec-setup-be-long.c: Likewise. From-SVN: r257668
2018-02-14re PR target/84220 (rs6000 builtin __builtin_vec_sld() ICEs on invalid 3rd ↵Will Schmidt1-43/+45
argument) [gcc] 2018-02-14 Will Schmidt <will_schmidt@vnet.ibm.com> PR target/84220 * config/rs6000/rs6000-c.c: Update definitions for ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SLDW, ALTIVEC_BUILTIN_VEC_XXPERMDI builtins. [testsuite] 2018-02-14 Will Schmidt <will_schmidt@vnet.ibm.com> PR target/84220 * gcc.target/powerpc/pr84220-sld.c: New test. * gcc.target/powerpc/pr84220-sld2.c: New test. * gcc.target/powerpc/pr84220-sldw.c: New test. * gcc.target/powerpc/pr84220-xxperm.c: New test. * gcc.target/powerpc/pr84220-xxsld.c: New test. From-SVN: r257662
2018-02-13re PR target/84279 (powerpc64le ICE on cvc4)Peter Bergner1-0/+6
gcc/ PR target/84279 * config/rs6000/rs6000.c (mem_operand_gpr): Disallow altivec addresses. gcc/testsuite/ PR target/84279 * g++.dg/pr84279.C: New test. From-SVN: r257647
2018-02-11re PR target/84266 (mmintrin.h intrinsic headers for PowerPC code fails on ↵Steven Munroe1-2/+2
power9) Fix PR 84266 From-SVN: r257571
2018-02-10PR84300, ICE in dwarf2cfi on ppc64le with -fsplit-stack -fno-omit-frame-pointerAlan Modra1-1/+1
PR target/84300 gcc/ * config/rs6000/rs6000.md (split_stack_return): Remove (use ..). Specify LR as an input. gcc/testsuite/ * gcc.dg/pr84300.c: New. From-SVN: r257549
2018-02-09re PR target/84226 (ICE in simplify_const_unary_operation, at ↵Jakub Jelinek1-10/+35
simplify-rtx.c:1974 on ppc64le) PR target/84226 * config/rs6000/vsx.md (p9_xxbrq_v16qi): Change input operand constraint from =wa to wa. Avoid a subreg on the output operand, instead use a pseudo and subreg it in a move. (p9_xxbrd_<mode>): Changed to ... (p9_xxbrd_v2di): ... this insn, without VSX_D iterator. (p9_xxbrd_v2df): New expander. (p9_xxbrw_<mode>): Changed to ... (p9_xxbrw_v4si): ... this insn, without VSX_W iterator. (p9_xxbrw_v4sf): New expander. * gcc.target/powerpc/pr84226.c: New test. From-SVN: r257536
2018-02-09re PR target/83926 (ICE during RTL pass: ira, in elimination_costs_in_insn, ↵Peter Bergner1-6/+58
at reload1.c:3633) gcc/ PR target/83926 * config/rs6000/vsx.md (vsx_mul_v2di): Handle generating a 64-bit multiply in 32-bit mode. (vsx_div_v2di): Handle generating a 64-bit signed divide in 32-bit mode. (vsx_udiv_v2di): Handle generating a 64-bit unsigned divide in 32-bit mode. gcc/testsuite/ PR target/83926 * gcc.target/powerpc/pr83926.c: New test. * gcc.target/powerpc/builtins-1-be.c: Filter out gimple folding disabled message. Fix test for running in 32-bit mode. From-SVN: r257531
2018-02-09[LVU] set ppc64 blockage's length to zeroAlexandre Oliva1-1/+2
LVU requires the zero-length (pseudo) insns's length to reflect reality. If they don't, it may assume there's a PC change where there isn't any, and then a view-aware assembler will detect the problem and complain about out-of-sync views. ppc blockage pseudo-insns did not have the length attribute explicitly set in them, so they inherited the attribute's default value, and that was nonzero. for gcc/ChangeLog * config/rs6000/rs6000.md (blockage): Set length to zero. From-SVN: r257520
2018-02-07altivec.md (*restore_world): Remove LR use.Iain Sandoe2-3/+1
2018-02-07 Iain Sandoe <iain@codesourcery.com> * config/rs6000/altivec.md (*restore_world): Remove LR use. * config/rs6000/predicates.md (restore_world_operation): Adjust op count, remove one USE. From-SVN: r257472
2018-02-07re PR target/84154 (PowerPC GCC 7 and 8 have regression in converting fp to ↵Michael Meissner1-129/+76
short/char and returning it) [gcc] 2018-02-07 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/84154 * config/rs6000/rs6000.md (fix_trunc<SFDF:mode><QHI:mode>2): Convert from define_expand to be define_insn_and_split. Rework float/double/_Float128 conversions to QI/HI/SImode to work with both ISA 2.07 (power8) or ISA 3.0 (power9). Fix regression where conversions to QI/HImode types did a store and then a load to truncate the value. For conversions to VSX registers, don't split the insn, instead emit the code directly. Use the code iterator any_fix to combine signed and unsigned conversions. (fix<uns>_trunc<SFDF:mode>si2_p8): Likewise. (fixuns_trunc<SFDF:mode><QHI:mode>2): Likewise. (fix_trunc<IEEE128:mode><QHI:mode>2): Likewise. (fix<uns>_trunc<SFDF:mode><QHI:mode>2): Likewise. (fix_<mode>di2_hw): Likewise. (fixuns_<mode>di2_hw): Likewise. (fix_<mode>si2_hw): Likewise. (fixuns_<mode>si2_hw): Likewise. (fix<uns>_<IEEE128:mode><SDI:mode>2_hw): Likewise. (fix<uns>_trunc<IEEE128:mode><QHI:mode>2): Likewise. (fctiw<u>z_<mode>_smallint): Rename fctiw<u>z_<mode>_smallint to fix<uns>_trunc<SFDF:mode>si2_p8. (fix_trunc<SFDF:mode><QHI:mode>2_internal): Delete, no longer used. (fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise. (fix<uns>_<mode>_mem): Likewise. (fctiw<u>z_<mode>_mem): Likewise. (fix<uns>_<mode>_mem): Likewise. (fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem): On ISA 3.0, prevent the register allocator from doing a direct move to the GPRs to do a store, and instead use the ISA 3.0 store byte/half-word from vector register instruction. For IEEE 128-bit floating point, also optimize stores of 32-bit ints. (fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem): Likewise. [gcc/testsuite] 2018-02-07 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/84154 * gcc.target/powerpc/pr84154-1.c: New tests. * gcc.target/powerpc/pr84154-2.c: Likewise. * gcc.target/powerpc/pr84154-3.c: Likewise. From-SVN: r257470
2018-02-06re PR target/84154 (PowerPC GCC 7 and 8 have regression in converting fp to ↵Michael Meissner1-1/+1
short/char and returning it) 2018-02-06 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/84154 * config/rs6000/rs6000.md (su code attribute): Use "u" for unsigned_fix, not "s". From-SVN: r257429
2018-02-06rs6000.c (rs6000_option_override_internal): Display warning message for ↵Bill Schmidt1-0/+5
-mno-speculate-indirect-jumps. [gcc] 2018-02-06 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_option_override_internal): Display warning message for -mno-speculate-indirect-jumps. [gcc/testsuite] 2018-02-06 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/safe-indirect-jump-1.c: Detect deprecation warning for -mno-speculate-indirect-jumps. * gcc.target/powerpc/safe-indirect-jump-2.c: Likewise. * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise. * gcc.target/powerpc/safe-indirect-jump-4.c: Likewise. * gcc.target/powerpc/safe-indirect-jump-5.c: Likewise. * gcc.target/powerpc/safe-indirect-jump-6.c: Likewise. * gcc.target/powerpc/safe-indirect-jump-7.c: Likewise. From-SVN: r257419
2018-02-01re PR target/56010 (Powerpc, -mcpu=native and -mtune=native use the wrong ↵Peter Bergner1-8/+89
name for target 7450) PR target/56010 PR target/83743 * config/rs6000/driver-rs6000.c: #include "diagnostic.h". #include "opts.h". (rs6000_supported_cpu_names): New static variable. (linux_cpu_translation_table): Likewise. (elf_platform) <cpu>: Define new static variable and use it. Translate kernel AT_PLATFORM name to canonical name if needed. Error if platform name is unknown. From-SVN: r257305
2018-01-30rs6000.c (rs6000_internal_arg_pointer): Only return a reg rtx.Aaron Sawdey1-2/+3
2018-01-30 Aaron Sawdey <acsawdey@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_internal_arg_pointer): Only return a reg rtx. From-SVN: r257193
2018-01-29re PR target/81550 (gcc.target/powerpc/loop_align.c fails starting with r250482)Michael Meissner1-1/+11
2018-01-29 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/81550 * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): If DFmode and SFmode can go in Altivec registers (-mcpu=power7 for DFmode, -mcpu=power8 for SFmode) don't set the PRE_INCDEC or PRE_MODIFY flags. This restores the settings used before the 2017-07-24. Turning off pre increment/decrement/modify allows IVOPTS to optimize DF/SF loops where the index is an int. From-SVN: r257166
2018-01-26PR84033, powerpc64le -moptimize-swaps bad code with vec_vbpermqAlan Modra1-6/+7
vbpermq produces its output in bits 48..63 of the target vector reg, so the output cannot be lane swapped. gcc/ PR target/84033 * config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p): Exclude UNSPEC_VBPERMQ. Sort other unspecs. gcc/testsuite/ PR target/84033 * gcc.target/powerpc/swaps-p8-46.c: New. From-SVN: r257070
2018-01-24rs6000.md (*call_indirect_nonlocal_sysv<mode>): Simplify the clause that ↵Bill Schmidt1-50/+24
sets the length attribute. 2018-01-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000.md (*call_indirect_nonlocal_sysv<mode>): Simplify the clause that sets the length attribute. (*call_value_indirect_nonlocal_sysv<mode>): Likewise. (*sibcall_nonlocal_sysv<mode>): Clean up code block; simplify the clause that sets the length attribute. (*sibcall_value_nonlocal_sysv<mode>): Likewise. From-SVN: r257019
2018-01-22re PR target/83862 (powerpc: ICE in signbit testcase)Michael Meissner3-94/+69
[gcc] 2018-01-22 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/83862 * config/rs6000/rs6000-protos.h (rs6000_split_signbit): Delete, no longer used. * config/rs6000/rs6000.c (rs6000_split_signbit): Likewise. * config/rs6000/rs6000.md (signbit<mode>2): Change code for IEEE 128-bit to produce an UNSPEC move to get the double word with the signbit and then a shift directly to do signbit. (signbit<mode>2_dm): Replace old IEEE 128-bit signbit implementation with a new version that just does either a direct move or a regular move. Move memory interface to separate insns. Move insns so they are next to the expander. (signbit<mode>2_dm_mem_be): New combiner insns to combine load with signbit move. Split big and little endian case. (signbit<mode>2_dm_mem_le): Likewise. (signbit<mode>2_dm_<su>ext): Delete, no longer used. (signbit<mode>2_dm2): Likewise. [gcc/testsuite] 2018-01-22 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/83862 * gcc.target/powerpc/pr83862.c: New test. From-SVN: r256959
2018-01-22rs6000-builtin.def (ST_ELEMREV_V1TI, [...]): Add macro expansion.Carl Love5-6/+103
gcc/ChangeLog: 2018-01-22 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def (ST_ELEMREV_V1TI, LD_ELEMREV_V1TI, LVX_V1TI): Add macro expansion. * config/rs6000/rs6000-c.c (altivec_builtin_types): Add argument definitions for VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_VEC_ST, VSX_BUILTIN_VEC_XL, LD_ELEMREV_V1TI builtins. * config/rs6000/rs6000-p8swap.c (insn_is_swappable_p); Change check to determine if the instruction is a byte reversing entry. Fix typo in comment. * config/rs6000/rs6000.c (altivec_expand_builtin): Add case entry for VSX_BUILTIN_ST_ELEMREV_V1TI and VSX_BUILTIN_LD_ELEMREV_V1TI. Add def_builtin calls for new builtins. * config/rs6000/vsx.md (vsx_st_elemrev_v1ti, vsx_ld_elemrev_v1ti): Add define_insn expansion. gcc/testsuite/ChangeLog: 2018-01-22 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/powerpc.exp: Add torture tests for builtins-4-runnable.c, builtins-6-runnable.c, builtins-5-p9-runnable.c, builtins-6-p9-runnable.c. * gcc.target/powerpc/builtins-6-runnable.c: New test file. * gcc.target/powerpc/builtins-4-runnable.c: Add additional tests for signed/unsigned 128-bit and long long int loads. From-SVN: r256952
2018-01-21re PR target/83946 (Safe Indirect Jumps broken on AIX)Bill Schmidt1-10/+10
[gcc] 2018-01-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com> David Edelsohn <dje.gcc@gmail.com> PR target/83946 * config/rs6000/rs6000.md (*call_indirect_nonlocal_sysv<mode>): Change "crset eq" to "crset 2". (*call_value_indirect_nonlocal_sysv<mode>): Likewise. (*call_indirect_aix<mode>_nospec): Likewise. (*call_value_indirect_aix<mode>_nospec): Likewise. (*call_indirect_elfv2<mode>_nospec): Likewise. (*call_value_indirect_elfv2<mode>_nospec): Likewise. (*sibcall_nonlocal_sysv<mode>): Change "crset eq" to "crset 2"; change assembly output from . to $. (*sibcall_value_nonlocal_sysv<mode>): Likewise. (indirect_jump<mode>_nospec): Change assembly output from . to $. (*tablejump<mode>_internal1_nospec): Likewise. [gcc/testsuite] 2018-01-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com> David Edelsohn <dje.gcc@gmail.com> PR target/83946 * gcc.target/powerpc/safe-indirect-jump-1.c: Change expected assembly output from "crset eq" to "crset 2". * gcc.target/powerpc/safe-indirect-jump-2.c: Change expected assembly output from . to $. * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise. * gcc.target/powerpc/safe-indirect-jump-1.c: Change expected assembly output from "crset eq" to "crset 2". * gcc.target/powerpc/safe-indirect-jump-8.c: Change expected assembly output from "crset eq" to "crset 2", and from . to $. Co-Authored-By: David Edelsohn <dje.gcc@gmail.com> From-SVN: r256931
2018-01-18rs6000.md (*call_indirect_nonlocal_sysv<mode>): Generate different code for ↵Bill Schmidt1-10/+137
-mno-speculate-indirect-jumps. [gcc] 2018-01-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000.md (*call_indirect_nonlocal_sysv<mode>): Generate different code for -mno-speculate-indirect-jumps. (*call_value_indirect_nonlocal_sysv<mode>): Likewise. (*call_indirect_aix<mode>): Disable for -mno-speculate-indirect-jumps. (*call_indirect_aix<mode>_nospec): New define_insn. (*call_value_indirect_aix<mode>): Disable for -mno-speculate-indirect-jumps. (*call_value_indirect_aix<mode>_nospec): New define_insn. (*sibcall_nonlocal_sysv<mode>): Generate different code for -mno-speculate-indirect-jumps. (*sibcall_value_nonlocal_sysv<mode>): Likewise. [gcc/testsuite] 2018-01-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/safe-indirect-jump-1.c: Remove endian restriction, but still restrict to 64-bit. * gcc.target/powerpc/safe-indirect-jump-7.c: New file. * gcc.target/powerpc/safe-indirect-jump-8.c: New file. From-SVN: r256831
2018-01-17rs6000.c (rs6000_emit_move): If we load or store a long double type...Michael Meissner1-0/+17
[gcc] 2018-01-17 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_emit_move): If we load or store a long double type, set the flags for noting the default long double type, even if we don't pass or return a long double type. [gcc/testsuite] 2018-01-17 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/gnuattr1.c: New test to make sure we set the appropriate .gnu_attribute for the long double type, if we use the long double type, but do not generate any calls. * gcc.target/powerpc/gnuattr2.c: Likewise. * gcc.target/powerpc/gnuattr3.c: Likewise. From-SVN: r256822
2018-01-17rs6000.c (rs6000_gimple_builtin): Add gimple folding support for merge[hl].Will Schmidt2-16/+77
[gcc] 2018-01-17 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_gimple_builtin): Add gimple folding support for merge[hl]. (fold_mergehl_helper): New helper function. (tree-vector-builder.h): New #include for tree_vector_builder usage. * config/rs6000/altivec.md (altivec_vmrghw_direct): Add xxmrghw insn. (altivec_vmrglw_direct): Add xxmrglw insn. [testsuite] 2018-01-17 Will Schmidt <will_schmidt@vnet.ibm.com> * gcc.target/powerpc/fold-vec-mergehl-char.c: New. * gcc.target/powerpc/fold-vec-mergehl-double.c: New. * gcc.target/powerpc/fold-vec-mergehl-float.c: New. * gcc.target/powerpc/fold-vec-mergehl-int.c: New. * gcc.target/powerpc/fold-vec-mergehl-longlong.c: New. * gcc.target/powerpc/fold-vec-mergehl-pixel.c: New. * gcc.target/powerpc/fold-vec-mergehl-short.c: New. * gcc.target/powerpc/builtins-1-be.c: Disable gimple-folding. * gcc.target/powerpc/builtins-1-le.c: Disable gimple-folding. * gcc.target/powerpc/builtins-1-be-folded.c: New. * gcc.target/powerpc/builtins-1-le-folded.c: New. * gcc.target/powerpc/builtins-1.fold.h: New. From-SVN: r256814
2018-01-17vsx.md (define_expand xl_len_r, [...]): Add match_dup argument.Carl Love2-12/+18
gcc/ChangeLog: 2018-01-17 Carl Love <cel@us.ibm.com> * config/rs6000/vsx.md (define_expand xl_len_r, define_expand stxvl, define_expand *stxvl): Add match_dup argument. (define_insn): Add, match_dup 1 argument to define_insn stxvll and lxvll. (define_expand, define_insn): Move the shift left from the define_insn to the define_expand for lxvl and stxvl instructions. * config/rs6000/rs6000-builtin.def (BU_P9V_64BIT_VSX_2): Change LXVL and XL_LEN_R definitions to PURE. gcc/testsuite/ChangeLog: 2018-01-17 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-6-p9-runnable.c: Add additional tests. Add debug print statements. * gcc.target/powerpc/builtins-5-p9-runnable.c: Add test to do 16 byte vector load followed by a partial vector load. From-SVN: r256798
2018-01-17config.gcc (powerpc*-linux*-*): Add support for 64-bit little endian Linux ↵Michael Meissner5-5/+74
systems to optionally enable... 2018-01-16 Michael Meissner <meissner@linux.vnet.ibm.com> * config.gcc (powerpc*-linux*-*): Add support for 64-bit little endian Linux systems to optionally enable multilibs for selecting the long double type if the user configured an explicit type. * config/rs6000/rs6000.h (TARGET_IEEEQUAD_MULTILIB): Indicate we have no long double multilibs if not defined. * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not warn if the user used -mabi={ieee,ibm}longdouble and we built multilibs for long double. * config/rs6000/linux64.h (MULTILIB_DEFAULTS_IEEE): Define as the appropriate multilib option. (MULTILIB_DEFAULTS): Add MULTILIB_DEFAULTS_IEEE to the default multilib options. * config/rs6000/t-ldouble-linux64le-ibm: New configuration files for building long double multilibs. * config/rs6000/t-ldouble-linux64le-ieee: Likewise. From-SVN: r256775
2018-01-16rs6000-p8swap.c (rs6000_gen_stvx): Generate different rtl trees depending on ↵Kelvin Nilsen1-32/+96
TARGET_64BIT. gcc/ChangeLog: 2018-01-16 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/rs6000-p8swap.c (rs6000_gen_stvx): Generate different rtl trees depending on TARGET_64BIT. (rs6000_gen_lvx): Likewise. From-SVN: r256762
2018-01-16rs6000.c (rs6000_opt_vars): Add entry for -mspeculate-indirect-jumps.Bill Schmidt3-10/+114
[gcc] 2018-01-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_opt_vars): Add entry for -mspeculate-indirect-jumps. * config/rs6000/rs6000.md (*call_indirect_elfv2<mode>): Disable for -mno-speculate-indirect-jumps. (*call_indirect_elfv2<mode>_nospec): New define_insn. (*call_value_indirect_elfv2<mode>): Disable for -mno-speculate-indirect-jumps. (*call_value_indirect_elfv2<mode>_nospec): New define_insn. (indirect_jump): Emit different RTL for -mno-speculate-indirect-jumps. (*indirect_jump<mode>): Disable for -mno-speculate-indirect-jumps. (*indirect_jump<mode>_nospec): New define_insn. (tablejump): Emit different RTL for -mno-speculate-indirect-jumps. (tablejumpsi): Disable for -mno-speculate-indirect-jumps. (tablejumpsi_nospec): New define_expand. (tablejumpdi): Disable for -mno-speculate-indirect-jumps. (tablejumpdi_nospec): New define_expand. (*tablejump<mode>_internal1): Disable for -mno-speculate-indirect-jumps. (*tablejump<mode>_internal1_nospec): New define_insn. * config/rs6000/rs6000.opt (mspeculate-indirect-jumps): New option. [gcc/testsuite] 2018-01-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/safe-indirect-jump-1.c: New file. * gcc.target/powerpc/safe-indirect-jump-2.c: New file. * gcc.target/powerpc/safe-indirect-jump-3.c: New file. * gcc.target/powerpc/safe-indirect-jump-4.c: New file. * gcc.target/powerpc/safe-indirect-jump-5.c: New file. * gcc.target/powerpc/safe-indirect-jump-6.c: New file. From-SVN: r256753
2018-01-16rs6000: Delete "delayed_cr" insn typeSegher Boessenkool26-42/+40
"delayed_cr" is just "cr_logical" with the second source operand not equal to the destination operand. This patch changes it to be expressed as type "cr_logical", with a new boolean attribute "cr_logical_3op" added. This simplifies code. * config/rs6000/rs6000.md (define_attr "type"): Remove delayed_cr. (define_attr "cr_logical_3op"): New. (cceq_ior_compare): Adjust. (cceq_ior_compare_complement): Adjust. (*cceq_rev_compare): Adjust. * config/rs6000/rs6000.c (rs6000_adjust_cost): Adjust. (is_cracked_insn): Adjust. (insn_must_be_first_in_group): Adjust. * config/rs6000/40x.md: Adjust. * config/rs6000/440.md: Adjust. * config/rs6000/476.md: Adjust. * config/rs6000/601.md: Adjust. * config/rs6000/603.md: Adjust. * config/rs6000/6xx.md: Adjust. * config/rs6000/7450.md: Adjust. * config/rs6000/7xx.md: Adjust. * config/rs6000/8540.md: Adjust. * config/rs6000/cell.md: Adjust. * config/rs6000/e300c2c3.md: Adjust. * config/rs6000/e500mc.md: Adjust. * config/rs6000/e500mc64.md: Adjust. * config/rs6000/e5500.md: Adjust. * config/rs6000/e6500.md: Adjust. * config/rs6000/mpc.md: Adjust. * config/rs6000/power4.md: Adjust. * config/rs6000/power5.md: Adjust. * config/rs6000/power6.md: Adjust. * config/rs6000/power7.md: Adjust. * config/rs6000/power8.md: Adjust. * config/rs6000/power9.md: Adjust. * config/rs6000/rs64.md: Adjust. * config/rs6000/titan.md: Adjust. From-SVN: r256716
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