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2013-08-30Merge ubsan into trunk.Marek Polacek1-1/+2
From-SVN: r202113
2013-08-20re PR target/57865 (Broken _save64gpr and _rest64gpr usage)Alan Modra1-4/+2
PR target/57865 * config/rs6000/rs6000.c (rs6000_emit_prologue): Correct ool_adjust. (rs6000_emit_epilogue): Likewise. From-SVN: r201860
2013-08-19builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin.Peter Bergner1-12/+21
gcc/ * builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin. (BUILT_IN_FABSD64): Likewise. (BUILT_IN_FABSD128): Likewise. * builtins.c (expand_builtin): Add support for new DFP ABS builtins. (fold_builtin_1): Likewise. * config/rs6000/dfp.md (*negtd2_fpr): Handle non-overlapping destination and source operands. (*abstd2_fpr): Likewise. (*nabstd2_fpr): Likewise. gcc/testsuite/ * gcc.target/powerpc/dfp-dd-2.c: New test. * gcc.target/powerpc/dfp-td-2.c: Likewise. * gcc.target/powerpc/dfp-td-3.c: Likewise. Co-Authored-By: Jakub Jelinek <jakub@redhat.com> From-SVN: r201849
2013-08-19target.def (TARGET_LIBC_HAS_FUNCTION): New target hook.Alexander Ivchenko8-30/+16
* target.def (TARGET_LIBC_HAS_FUNCTION): New target hook. * builtins.c (default_libc_has_function): New. (gnu_libc_has_function): Ditto. (no_c99_libc_has_function): Ditto. (expand_builtin_cexpi): Using new target hook TARGET_LIBC_HAS_FUNCTION instead of TARGET_HAS_SINCOS and TARGET_C99_FUNCTIONS. (fold_builtin_sincos): Likewise. (fold_builtin_cexp): Likewise. * builtins.def (DEF_C94_BUILTIN): Likewise. (DEF_C99_BUILTIN): Likewise. (DEF_C99_C90RES_BUILTIN): Likewise. (DEF_C99_COMPL_BUILTIN): New define. Change all complex c99 builtin definitions to using this define. * config/darwin-protos.h (darwin_libc_has_function): New. * config/darwin.c: (darwin_libc_has_function: Ditto. * config/alpha/linux.h: Remove TARGET_C99_FUNCTIONS and TARGET_HAS_SINCOS. Redefine TARGET_LIBC_HAS_FUNCTION. * config/darwin.h: Ditto. * config/elfos.h: Ditto. * config/freebsd.h: Ditto. * config/i386/cygming.h: Ditto. * config/i386/djgpp.h: Ditto. * config/i386/i386-interix.h: Ditto. * config/microblaze/microblaze.h: Ditto. * config/mmix/mmix.h: Ditto. * config/gnu-user.h: Ditto. * config/ia64/hpux.h: Ditto. * config/pa/pa-hpux.h: Ditto. * config/pdp11/pdp11.h: Ditto. * config/picochip/picochip.h: Ditto. * config/linux.h: Ditto. * config/netbsd.h: Ditto. * config/openbsd.h: Ditto. * config/rs6000/aix43.h: Ditto. * config/rs6000/aix51.h: Ditto. * config/rs6000/aix52.h: Ditto. * config/rs6000/aix53.h: Ditto. * config/rs6000/aix61.h: Ditto. * config/rs6000/darwin.h: Ditto. * config/rs6000/linux.h: Ditto. * config/rs6000/linux64.h: Ditto. * config/s390/tpf.h: Ditto. * config/sol2-10.h: Ditto. * config/sol2.h: Ditto. * config/vms/vms.h: Ditto. * config/vxworks.h: Ditto. * config/linux-android.c (linux_android_libc_has_function): New linux-specific implementation of TARGET_LIBC_HAS_FUNCTION. * config/linux-protos.h (linux_android_libc_has_function): New declaration. * config/i386/i386.c (ix86_libc_has_function): New. * config/i386/i386-protos.h (ix86_libc_has_function): New declaration. * config/i386/i386.md ("isinfxf2"): Change condition for TARGET_LIBC_HAS_FUNCTION. ("isinf<mode>2): Likewise. * convert.c (convert_to_integer): Using new target hook TARGET_LIBC_HAS_FUNCTION istead of TARGET_HAS_SINCOS and TARGET_C99_FUNCTIONS. * fortran/f95-lang.c (gfc_init_builtin_functions): Ditto. * tree-ssa-math-opts.c (execute_cse_sincos): Ditto. * coretypes.h (function_class): New enum for different classes of functions. * defaults.h: Remove TARGET_C99_FUNCTIONS and TARGET_HAS_SINCOS. * doc/tm.texi.in (TARGET_C99_FUNCTIONS): Remove documentation. (TARGET_HAS_SINCOS): Likewise. (TARGET_LIBC_HAS_FUNCTION): New. * doc/tm.texi: Regenerated. * targhooks.h (default_libc_has_function): New declaration. (no_c99_libc_has_function): Ditto. (gnu_libc_has_function): Ditto. * system.h: Add the poisoning of TARGET_C99_FUNCTIONS and TARGET_HAS_SINCOS. From-SVN: r201838
2013-08-16rs6000.md (rs6000_get_timebase_ppc32): Add length attribute.David Edelsohn1-1/+2
* config/rs6000/rs6000.md (rs6000_get_timebase_ppc32): Add length attribute. From-SVN: r201812
2013-08-16re PR target/58160 (Power8 fusion support has a bug that shows up in running ↵Michael Meissner4-143/+193
spec 2006) 2013-08-14 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/58160 * config/rs6000/predicates.md (fusion_gpr_mem_load): Allow the memory rtx to contain ZERO_EXTEND and SIGN_EXTEND. * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Pass operands array instead of each individual operand as a separate argument. (emit_fusion_gpr_load): Likewise. (expand_fusion_gpr_load): Add new function declaration. * config/rs6000/rs6000.c (fusion_gpr_load_p): Change the calling signature to have the operands passed as an array, instead of as separate arguments. Allow ZERO_EXTEND to be in the memory address, and also SIGN_EXTEND if -mpower8-fusion-sign. Do not depend on the register live/dead flags when peepholes are run. (expand_fusion_gpr_load): New function to be called from the peephole2 pass, to change the register that addis sets to be the target register. (emit_fusion_gpr_load): Change the calling signature to have the operands passed as an array, instead of as separate arguments. Allow ZERO_EXTEND to be in the memory address, and also SIGN_EXTEND if -mpower8-fusion-sign. * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): Delete unused unspec enumeration. (power8 fusion peephole/peephole2): Rework the fusion peepholes to adjust the register addis loads up in the peephole2 pass. Do not depend on the register live/dead state when the peephole pass is done. From-SVN: r201792
2013-08-14re PR target/57949 ([powerpc64] Structure parameter alignment issue with ↵Bill Schmidt2-4/+9
vector extensions) gcc: 2013-08-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com> PR target/57949 * doc/invoke.texi: Add documentation of mcompat-align-parm option. * config/rs6000/rs6000.opt: Add mcompat-align-parm option. * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX and Linux, correct BLKmode alignment when 128-bit alignment is required and compatibility flag is not set. (rs6000_gimplify_va_arg): For AIX and Linux, honor specified alignment for zero-size arguments when compatibility flag is not set. gcc/testsuite: 2013-08-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com> PR target/57949 * gcc.target/powerpc/pr57949-1.c: New. * gcc.target/powerpc/pr57949-2.c: New. From-SVN: r201750
2013-08-13rs6000.c (rs6000_legitimize_reload_address): Don't perform invalid ↵Julian Brown1-3/+1
legitimization on greater-than-word-size modes for... * config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Don't perform invalid legitimization on greater-than-word-size modes for TARGET_E500_DOUBLE. From-SVN: r201701
2013-08-07re PR other/12081 (Gcc can't be compiled with -mregparm=3)Oleg Endo1-5/+2
PR other/12081 config/rs6000/rs6000.c (gen_2arg_fn_t): Remove typedef. (rs6000_emit_swdiv, rs6000_emit_swrsqrt): Don't cast result of GEN_FCN to gen_2arg_fn_t. From-SVN: r201580
2013-08-07* config/rs6000/rs6000.c (htm_expand_builtin) <case 0>: Remove.Peter Bergner1-3/+0
From-SVN: r201565
2013-07-31predicates.md (fusion_gpr_addis): New predicates to support power8 load fusion.Michael Meissner6-1/+511
[gcc] 2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/predicates.md (fusion_gpr_addis): New predicates to support power8 load fusion. (fusion_gpr_mem_load): Likewise. * config/rs6000/rs6000-modes.def (PTImode): Update a comment. * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New declarations for power8 load fusion. (emit_fusion_gpr_load): Likewise. * config/rs6000/rs6000.c (rs6000_option_override_internal): If tuning for power8, turn on fusion mode by default. Turn on sign extending fusion mode if normal fusion mode is on, and we are at -O2 or -O3. (fusion_gpr_load_p): New function, return true if we can fuse an addis instruction with a dependent load to a GPR. (emit_fusion_gpr_load): Emit the instructions for power8 load fusion to GPRs. * config/rs6000/vsx.md (VSX_M2): New iterator for fusion peepholes. (VSX load fusion peepholes): New peepholes to fuse together an addi instruction with a VSX load instruction. * config/rs6000/rs6000.md (GPR load fusion peepholes): New peepholes to fuse an addis instruction with a load to a GPR base register. If we are supporting sign extending fusions, convert sign extending loads to zero extending loads and add an explicit sign extension. [gcc/testsuite] 2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/fusion.c: New file, test power8 fusion support. From-SVN: r201385
2013-07-31config.gcc (*-*-rtems*): Use __cxa_atexit by default.Sebastian Huber1-0/+3
2013-07-31 Sebastian Huber <sebastian.huber@embedded-brains.de> * config.gcc (*-*-rtems*): Use __cxa_atexit by default. * config/rs6000/rtems.h (TARGET_LIBGCC_SDATA_SECTION): Define. From-SVN: r201370
2013-07-25altivec.md (altivec_vpkpx): Handle little endian.Bill Schmidt1-5/+35
2013-07-24 Bill Schmidt <wschmidt@linux.ibm.com> Anton Blanchard <anton@au1.ibm.com> * config/rs6000/altivec.md (altivec_vpkpx): Handle little endian. (altivec_vpks<VI_char>ss): Likewise. (altivec_vpks<VI_char>us): Likewise. (altivec_vpku<VI_char>us): Likewise. (altivec_vpku<VI_char>um): Likewise. Co-Authored-By: Anton Blanchard <anton@au1.ibm.com> From-SVN: r201235
2013-07-24vector.md (vec_realign_load_<mode>): Reorder input operands to vperm for ↵Bill Schmidt2-3/+8
little endian. 2013-07-24 Bill Schmidt <wschmidt@vnet.linux.ibm.com> Anton Blanchard <anton@au1.ibm.com> * vector.md (vec_realign_load_<mode>): Reorder input operands to vperm for little endian. * rs6000.c (rs6000_expand_builtin): Use lvsr instead of lvsl to create the control mask for a vperm for little endian. Co-Authored-By: Anton Blanchard <anton@au1.ibm.com> From-SVN: r201208
2013-07-23rs6000.c (altivec_expand_vec_perm_const): Reverse two operands for ↵Bill Schmidt1-1/+4
little-endian. 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Anton Blanchard <anton@au1.ibm.com> * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Reverse two operands for little-endian. Co-Authored-By: Anton Blanchard <anton@au1.ibm.com> From-SVN: r201195
2013-07-23rs6000.c (altivec_expand_vec_perm_const): Correct selection of field for ↵Bill Schmidt1-2/+4
vector splat in little endian mode. 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Anton Blanchard <anton@au1.ibm.com> * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Correct selection of field for vector splat in little endian mode. Co-Authored-By: Anton Blanchard <anton@au1.ibm.com> From-SVN: r201193
2013-07-23vector.md (xor<mode>3): Move 128-bit boolean expanders to rs6000.md.Michael Meissner7-522/+763
[gcc] 2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vector.md (xor<mode>3): Move 128-bit boolean expanders to rs6000.md. (ior<mode>3): Likewise. (and<mode>3): Likewise. (one_cmpl<mode>2): Likewise. (nor<mode>3): Likewise. (andc<mode>3): Likewise. (eqv<mode>3): Likewise. (nand<mode>3): Likewise. (orc<mode>3): Likewise. * config/rs6000/rs6000-protos.h (rs6000_split_logical): New declaration. * config/rs6000/rs6000.c (rs6000_split_logical_inner): Add support to split multi-word logical operations. (rs6000_split_logical_di): Likewise. (rs6000_split_logical): Likewise. * config/rs6000/vsx.md (VSX_L2): Delete, no longer used. (vsx_and<mode>3_32bit): Move 128-bit logical insns to rs6000.md, and allow TImode operations in 32-bit. (vsx_and<mode>3_64bit): Likewise. (vsx_ior<mode>3_32bit): Likewise. (vsx_ior<mode>3_64bit): Likewise. (vsx_xor<mode>3_32bit): Likewise. (vsx_xor<mode>3_64bit): Likewise. (vsx_one_cmpl<mode>2_32bit): Likewise. (vsx_one_cmpl<mode>2_64bit): Likewise. (vsx_nor<mode>3_32bit): Likewise. (vsx_nor<mode>3_64bit): Likewise. (vsx_andc<mode>3_32bit): Likewise. (vsx_andc<mode>3_64bit): Likewise. (vsx_eqv<mode>3_32bit): Likewise. (vsx_eqv<mode>3_64bit): Likewise. (vsx_nand<mode>3_32bit): Likewise. (vsx_nand<mode>3_64bit): Likewise. (vsx_orc<mode>3_32bit): Likewise. (vsx_orc<mode>3_64bit): Likewise. * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Always allow vector logical types in GPRs. * config/rs6000/altivec.md (altivec_and<mode>3): Move 128-bit logical insns to rs6000.md, and allow TImode operations in 32-bit. (altivec_ior<mode>3): Likewise. (altivec_xor<mode>3): Likewise. (altivec_one_cmpl<mode>2): Likewise. (altivec_nor<mode>3): Likewise. (altivec_andc<mode>3): Likewise. * config/rs6000/rs6000.md (BOOL_128): New mode iterators and mode attributes for moving the 128-bit logical operations into rs6000.md. (BOOL_REGS_OUTPUT): Likewise. (BOOL_REGS_OP1): Likewise. (BOOL_REGS_OP2): Likewise. (BOOL_REGS_UNARY): Likewise. (BOOL_REGS_AND_CR0): Likewise. (one_cmpl<mode>2): Add support for DI logical operations on 32-bit, splitting the operations to 32-bit. (anddi3): Likewise. (iordi3): Likewise. (xordi3): Likewise. (and<mode>3, 128-bit types): Rewrite 2013-06-06 logical operator changes to combine the 32/64-bit code, allow logical operations on TI mode in 32-bit, and to use similar match_operator patterns like scalar mode uses. Combine the Altivec and VSX code for logical operations, and move it here. (ior<mode>3, 128-bit types): Likewise. (xor<mode>3, 128-bit types): Likewise. (one_cmpl<mode>3, 128-bit types): Likewise. (nor<mode>3, 128-bit types): Likewise. (andc<mode>3, 128-bit types): Likewise. (eqv<mode>3, 128-bit types): Likewise. (nand<mode>3, 128-bit types): Likewise. (orc<mode>3, 128-bit types): Likewise. (and<mode>3_internal): Likewise. (bool<mode>3_internal): Likewise. (boolc<mode>3_internal1): Likewise. (boolc<mode>3_internal2): Likewise. (boolcc<mode>3_internal1): Likewise. (boolcc<mode>3_internal2): Likewise. (eqv<mode>3_internal1): Likewise. (eqv<mode>3_internal2): Likewise. (one_cmpl1<mode>3_internal): Likewise. [gcc/testsuite] 2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/bool2.h: New file, test the code generation of logical operations for power5, altivec, power7, and power8 systems. * gcc.target/powerpc/bool2-p5.c: Likewise. * gcc.target/powerpc/bool2-av.c: Likewise. * gcc.target/powerpc/bool2-p7.c: Likewise. * gcc.target/powerpc/bool2-p8.c: Likewise. * gcc.target/powerpc/bool3.h: Likewise. * gcc.target/powerpc/bool3-av.c: Likewise. * gcc.target/powerpc/bool2-p7.c: Likewise. * gcc.target/powerpc/bool2-p8.c: Likewise. From-SVN: r201187
2013-07-22rs6000.c (rs6000_expand_vector_init): Fix endianness when selecting field to ↵Bill Schmidt1-1/+4
splat. 2013-07-22 Bill Schmidt <wschmidt@vnet.linux.ibm.com> Anton Blanchard <anton@au1.ibm.com> * config/rs6000/rs6000.c (rs6000_expand_vector_init): Fix endianness when selecting field to splat. Co-Authored-By: Anton Blanchard <anton@au1.ibm.com> From-SVN: r201149
2013-07-21Fix typos.Mike Stump1-1/+1
From-SVN: r201105
2013-07-18rs6000.c (rs6000_option_override_internal): Adjust flag interaction for new ↵Pat Haugen1-1/+14
Power8 flags and VSX. * config/rs6000/rs6000.c (rs6000_option_override_internal): Adjust flag interaction for new Power8 flags and VSX. From-SVN: r201041
2013-07-17darwin.h (REGISTER_NAMES): Add HTM registers.Iain Sandoe1-1/+2
gcc/ * config/rs6000/darwin.h (REGISTER_NAMES): Add HTM registers. line, and those below, will be ignored-- M ChangeLog M config/rs6000/darwin.h From-SVN: r201011
2013-07-16rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM registers in the comment.Peter Bergner1-3/+5
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM registers in the comment. (DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers. (DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS rather than FIRST_PSEUDO_REGISTERS. From-SVN: r200988
2013-07-16rs6000.c (rs6000_option_override_internal): Do not enable extra ISA flags ↵Peter Bergner1-1/+1
with TARGET_HTM. * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not enable extra ISA flags with TARGET_HTM. From-SVN: r200985
2013-07-15acinclude.m4 (LIBITM_CHECK_AS_HTM): New.Peter Bergner12-17/+1220
libitm/ * acinclude.m4 (LIBITM_CHECK_AS_HTM): New. * configure.ac: Use it. (AC_CHECK_HEADERS): Check for sys/auxv.h. (AC_CHECK_FUNCS): Check for getauxval. * config.h.in, configure: Rebuild. * configure.tgt (target_cpu): Add -mhtm to XCFLAGS. * config/powerpc/target.h: Include sys/auxv.h and htmintrin.h. (USE_HTM_FASTPATH): Define. (_TBEGIN_STARTED, _TBEGIN_INDETERMINATE, _TBEGIN_PERSISTENT, _HTM_RETRIES) New macros. (htm_abort, htm_abort_should_retry, htm_available, htm_begin, htm_init, htm_begin_success, htm_commit, htm_transaction_active): New functions. gcc/ * config.gcc (powerpc*-*-*): Install htmintrin.h and htmxlintrin.h. * config/rs6000/t-rs6000 (MD_INCLUDES): Add htm.md. * config/rs6000/rs6000.opt: Add -mhtm option. * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_HTM. (ISA_2_7_MASKS_SERVER): Add OPTION_MASK_HTM. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define __HTM__ if the HTM instructions are available. * config/rs6000/predicates.md (u3bit_cint_operand, u10bit_cint_operand, htm_spr_reg_operand): New define_predicates. * config/rs6000/rs6000.md (define_attr "type"): Add htm. (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO): New define_constants. Include htm.md. * config/rs6000/rs6000-builtin.def (BU_HTM_0, BU_HTM_1, BU_HTM_2, BU_HTM_3, BU_HTM_SPR0, BU_HTM_SPR1): Add support macros for defining HTM builtin functions. * config/rs6000/rs6000.c (RS6000_BUILTIN_H): New macro. (rs6000_reg_names, alt_reg_names): Add HTM SPR register names. (rs6000_init_hard_regno_mode_ok): Add support for HTM instructions. (rs6000_builtin_mask_calculate): Likewise. (rs6000_option_override_internal): Likewise. (bdesc_htm): Add new HTM builtin support. (htm_spr_num): New function. (htm_spr_regno): Likewise. (rs6000_htm_spr_icode): Likewise. (htm_expand_builtin): Likewise. (htm_init_builtins): Likewise. (rs6000_expand_builtin): Add support for HTM builtin functions. (rs6000_init_builtins): Likewise. (rs6000_invalid_builtin, rs6000_opt_mask): Add support for -mhtm option. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mhtm. (TARGET_HTM, MASK_HTM): Define macros. (FIRST_PSEUDO_REGISTER): Adjust for new HTM SPR registers. (FIXED_REGISTERS): Likewise. (CALL_USED_REGISTERS): Likewise. (CALL_REALLY_USED_REGISTERS): Likewise. (REG_ALLOC_ORDER): Likewise. (enum reg_class): Likewise. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Likewise. (REGISTER_NAMES): Likewise. (ADDITIONAL_REGISTER_NAMES): Likewise. (RS6000_BTC_SPR, RS6000_BTC_VOID, RS6000_BTC_32BIT, RS6000_BTC_64BIT, RS6000_BTC_MISC_MASK, RS6000_BTM_HTM): New macros. (RS6000_BTM_COMMON): Add RS6000_BTM_HTM. * config/rs6000/htm.md: New file. * config/rs6000/htmintrin.h: New file. * config/rs6000/htmxlintrin.h: New file. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_powerpc_htm_ok): New function to test if HTM is available. * gcc.target/powerpc/htm-xl-intrin-1.c: New test. * gcc.target/powerpc/htm-builtin-1.c: New test. From-SVN: r200960
2013-07-11rs6000.md (""*tls_gd_low<TLSmode:tls_abi_suffix>"): Require GOT register as ↵Ulrich Weigand1-8/+13
additional operand in UNSPEC. * config/rs6000/rs6000.md (""*tls_gd_low<TLSmode:tls_abi_suffix>"): Require GOT register as additional operand in UNSPEC. ("*tls_ld_low<TLSmode:tls_abi_suffix>"): Likewise. ("*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"): Likewise. ("*tls_got_tprel_low<TLSmode:tls_abi_suffix>"): Likewise. ("*tls_gd<TLSmode:tls_abi_suffix>"): Update splitter. ("*tls_ld<TLSmode:tls_abi_suffix>"): Likewise. ("tls_got_dtprel_<TLSmode:tls_abi_suffix>"): Likewise. ("tls_got_tprel_<TLSmode:tls_abi_suffix>"): Likewise. From-SVN: r200904
2013-07-09rs6000.c (rs6000_init_hard_regno_mode_ok): Only adjust register size for ↵Joseph Myers1-1/+2
TDmode and TFmode for VSX registers. * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Only adjust register size for TDmode and TFmode for VSX registers. From-SVN: r200853
2013-06-28re PR target/57744 (Power8 support has problems with quad word atomic ↵Michael Meissner1-10/+14
instructions) [gcc] 2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/57744 * config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode to tie with any other modes. Eliminate Altivec vector mode tests, since these are a subset of ALTIVEC or VSX vector modes. Simplify code, to return 0 if testing MODE2 for a condition, if we've already tested MODE1 for the same condition. [gcc/testsuite] 2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/57744 * gcc.target/powerpc/pr57744.c: New test to make sure lqarx and stqcx. get even registers. From-SVN: r200538
2013-06-26power8.md: New.Michael Meissner5-6/+433
* config/rs6000/power8.md: New. * config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor setting for power8 entry. * config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md. * config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust test for Power4/Power5 only. (insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8 support. (force_new_group): Adjust comment. * config/rs6000/rs6000.md: Include power8.md. Co-Authored-By: Pat Haugen <pthaugen@us.ibm.com> Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com> From-SVN: r200423
2013-06-24rs6000.c (vspltis_constant): Correct for little-endian.Alan Modra2-8/+12
gcc/ * config/rs6000/rs6000.c (vspltis_constant): Correct for little-endian. (gen_easy_altivec_constant): Likewise. * config/rs6000/predicates.md (easy_vector_constant_add_self, easy_vector_constant_msb): Likewise. gcc/testsuite/ * gcc.target/powerpc/altivec-consts.c: Correct for little-endian. Add scan-assembler-not "lvx". * gcc.target/powerpc/le-altivec-consts.c: New. From-SVN: r200357
2013-06-18rs6000.h (enum data_align): New.Alan Modra3-22/+59
* config/rs6000/rs6000.h (enum data_align): New. (LOCAL_ALIGNMENT, DATA_ALIGNMENT): Use rs6000_data_alignment. (DATA_ABI_ALIGNMENT): Define. (CONSTANT_ALIGNMENT): Correct comment. * config/rs6000/rs6000-protos.h (rs6000_data_alignment): Declare. * config/rs6000/rs6000.c (rs6000_data_alignment): New function. From-SVN: r200159
2013-06-14re PR target/57615 (power8 support does not deal with -mquad-memory -mno-vsx)Michael Meissner1-2/+5
2013-06-14 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/57615 * config/rs6000/rs6000.md (mov<mode>_ppc64): Call rs6000_output_move_128bit to handle emitting quad memory operations. Set attribute length to 8 bytes. From-SVN: r200107
2013-06-13rs6000.c (rs6000_option_override_internal): Move test for clearing quad ↵Michael Meissner1-10/+10
memory on 32-bit later. 2013-06-13 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_option_override_internal): Move test for clearing quad memory on 32-bit later. From-SVN: r200074
2013-06-13rs6000.h (LONG_DOUBLE_LARGE_FIRST): Define.Alan Modra3-10/+50
* config/rs6000/rs6000.h (LONG_DOUBLE_LARGE_FIRST): Define. * config/rs6000/rs6000.md (signbittf2): New insn. (extenddftf2_internal): Use LONG_DOUBLE_LARGE_FIRST. (abstf2_internal, cmptf_internal2): Likewise. * config/rs6000/spe.md (spe_abstf2_cmp, spe_abstf2_tst): Likewise. From-SVN: r200055
2013-06-12rs6000.c (emit_load_locked): Add support for power8 byte, half-word, and ↵Michael Meissner3-98/+259
quad-word atomic instructions. [gcc] 2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * config/rs6000/rs6000.c (emit_load_locked): Add support for power8 byte, half-word, and quad-word atomic instructions. (emit_store_conditional): Likewise. (rs6000_expand_atomic_compare_and_swap): Likewise. (rs6000_expand_atomic_op): Likewise. * config/rs6000/sync.md (larx): Add new modes for power8. (stcx): Likewise. (AINT): New mode iterator to include TImode as well as normal integer modes on power8. (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so that VSX registers are not considered. Use AINT mode iterator instead of INT1 to allow inclusion of quad word atomic operations on power8. (load_locked<mode>): Likewise. (store_conditional<mode>): Likewise. (atomic_compare_and_swap<mode>): Likewise. (atomic_exchange<mode>): Likewise. (atomic_nand<mode>): Likewise. (atomic_fetch_<fetchop_name><mode>): Likewise. (atomic_nand_fetch<mode>): Likewise. (mem_thread_fence): Use gen_loadsync_<mode> instead of enumerating each type. (ATOMIC): On power8, add QImode, HImode modes. (load_locked<QHI:mode>_si): Varients of load_locked for QI/HI modes that promote to SImode. (load_lockedti): Convert TImode arguments to PTImode, so that we get a guaranteed even/odd register pair. (load_lockedpti): Likewise. (store_conditionalti): Likewise. (store_conditionalpti): Likewise. * config/rs6000/rs6000.md (QHI): New mode iterator for power8 atomic load/store instructions. (HSI): Likewise. [gcc/testsuite] 2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic load/store instructions on power7, power8. * gcc.target/powerpc/atomic-p8.c: Likewise. Co-Authored-By: Pat Haugen <pthaugen@us.ibm.com> Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com> From-SVN: r200044
2013-06-12re PR target/57578 (SPE detection broken on Linux (bits/predefs.h: No such ↵Roland Stigge1-1/+1
file or directory)) 2013-06-12 Roland Stigge <stigge@antcom.de> PR target/57578 * config/rs6000/t-linux (MULTIARCH_DIRNAME): Fix SPE version detection. From-SVN: r200012
2013-06-11re PR target/57589 (Linux powerpc -mcpu=native returns pointer to variable ↵Michael Meissner1-1/+1
on stack in driver-rs6000.c) 2013-06-11 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/57589 * config/rs6000/driver-rs6000.c (elf_platform): Make buffer static to allow returning address to AT_PLATFORM name. From-SVN: r199972
2013-06-11rs6000.c (rs6000_adjust_atomic_subword): Calculate correct shift value in ↵Anton Blanchard1-2/+3
little-endian mode. * config/rs6000/rs6000.c (rs6000_adjust_atomic_subword): Calculate correct shift value in little-endian mode. From-SVN: r199935
2013-06-10vector.md (GPR move splitter): Do not split moves of vectors in GPRS if they ↵Michael Meissner5-207/+1011
are direct moves or quad word... [gcc] 2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * config/rs6000/vector.md (GPR move splitter): Do not split moves of vectors in GPRS if they are direct moves or quad word load or store moves. * config/rs6000/rs6000-protos.h (rs6000_output_move_128bit): Add declaration. (direct_move_p): Likewise. (quad_load_store_p): Likewise. * config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register classes into bins based on the physical register type. (reg_class_to_reg_type): Likewise. (IS_STD_REG_TYPE): Likewise. (IS_FP_VECT_REG_TYPE): Likewise. (reload_fpr_gpr): Arrays to determine what insn to use if we can use direct move instructions. (reload_gpr_vsx): Likewise. (reload_vsx_gpr): Likewise. (rs6000_init_hard_regno_mode_ok): Precalculate the register type information that is a simplification of register classes. Also precalculate direct move reload helpers. (direct_move_p): New function to return true if the operation can be done as a direct move instruciton. (quad_load_store_p): New function to return true if the operation is a quad memory operation. (rs6000_legitimize_address): If quad memory, only allow register indirect for TImode addresses. (rs6000_legitimate_address_p): Likewise. (enum reload_reg_type): Delete, replace with rs6000_reg_type. (rs6000_reload_register_type): Likewise. (register_to_reg_type): Return register type. (rs6000_secondary_reload_simple_move): New helper function for secondary reload and secondary memory needed to identify anything that is a simple move, and does not need reloading. (rs6000_secondary_reload_direct_move): New helper function for secondary reload to identify cases that can be done with several instructions via the direct move instructions. (rs6000_secondary_reload_move): New helper function for secondary reload to identify moves between register types that can be done. (rs6000_secondary_reload): Add support for quad memory operations and for direct move. (rs6000_secondary_memory_needed): Likewise. (rs6000_debug_secondary_memory_needed): Change argument names. (rs6000_output_move_128bit): New function to return the move to use for 128-bit moves, including knowing about the various limitations of quad memory operations. * config/rs6000/vsx.md (vsx_mov<mode>): Add support for quad memory operations. call rs6000_output_move_128bit for the actual instruciton(s) to generate. (vsx_movti_64bit): Likewise. * config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values. (UNSPEC_P8V_MTVSRWZ): Likewise. (UNSPEC_P8V_RELOAD_FROM_GPR): Likewise. (UNSPEC_P8V_MTVSRD): Likewise. (UNSPEC_P8V_XXPERMDI): Likewise. (UNSPEC_P8V_RELOAD_FROM_VSX): Likewise. (UNSPEC_FUSION_GPR): Likewise. (FMOVE128_GPR): New iterator for direct move. (f32_lv): New mode attribute for load/store of SFmode/SDmode values. (f32_sv): Likewise. (f32_dm): Likewise. (zero_extend<mode>di2_internal1): Add support for power8 32-bit loads and direct move instructions. (zero_extendsidi2_lfiwzx): Likewise. (extendsidi2_lfiwax): Likewise. (extendsidi2_nocell): Likewise. (floatsi<mode>2_lfiwax): Likewise. (lfiwax): Likewise. (floatunssi<mode>2_lfiwzx): Likewise. (lfiwzx): Likewise. (fix_trunc<mode>_stfiwx): Likewise. (fixuns_trunc<mode>_stfiwx): Likewise. (mov<mode>_hardfloat, 32-bit floating point): Likewise. (mov<move>_hardfloat64, 64-bit floating point): Likewise. (parity<mode>2_cmpb): Set length/type attr. (unnamed shift right patterns, mov<mode>_internal2): Change type attr for 'mr.' to fast_compare. (bpermd_<mode>): Change type attr to popcnt. (p8_fmrgow_<mode>): New insns for power8 direct move support. (p8_mtvsrwz_1): Likewise. (p8_mtvsrwz_2): Likewise. (reload_fpr_from_gpr<mode>): Likewise. (p8_mtvsrd_1): Likewise. (p8_mtvsrd_2): Likewise. (p8_xxpermdi_<mode>): Likewise. (reload_vsx_from_gpr<mode>): Likewise. (reload_vsx_from_gprsf): Likewise. (p8_mfvsrd_3_<mode>): LIkewise. (reload_gpr_from_vsx<mode>): Likewise. (reload_gpr_from_vsxsf): Likewise. (p8_mfvsrd_4_disf): Likewise. (multi-word GPR splits): Do not split direct moves or quad memory operations. [gcc/testsuite] 2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * gcc.target/powerpc/direct-move-vint1.c: New tests for power8 direct move instructions. * gcc.target/powerpc/direct-move-vint2.c: Likewise. * gcc.target/powerpc/direct-move.h: Likewise. * gcc.target/powerpc/direct-move-float1.c: Likewise. * gcc.target/powerpc/direct-move-float2.c: Likewise. * gcc.target/powerpc/direct-move-double1.c: Likewise. * gcc.target/powerpc/direct-move-double2.c: Likewise. * gcc.target/powerpc/direct-move-long1.c: Likewise. * gcc.target/powerpc/direct-move-long2.c: Likewise. Co-Authored-By: Pat Haugen <pthaugen@us.ibm.com> Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com> From-SVN: r199918
2013-06-08rs6000.c (print_operand, 'z'): Remove historical hack to mark symbols as used.David Edelsohn1-5/+0
2013-06-09 David Edelsohn <dje.gcc@gmail.com> Jan Hubicka <jh@suse.cz> * config/rs6000/rs6000.c (print_operand, 'z'): Remove historical hack to mark symbols as used. Co-Authored-By: Jan Hubicka <jh@suse.cz> From-SVN: r199865
2013-06-07rs6000.c (setup_incoming_varargs): Round up va_list_gpr_size.Alan Modra1-11/+8
* config/rs6000/rs6000.c (setup_incoming_varargs): Round up va_list_gpr_size. From-SVN: r199808
2013-06-07rs6000.c (rs6000_option_override_internal): Don't override user -mfp-in-toc.Alan Modra2-50/+64
* config/rs6000/rs6000.c (rs6000_option_override_internal): Don't override user -mfp-in-toc. (offsettable_ok_by_alignment): Consider just the current access rather than the whole object, unless BLKmode. Handle CONSTANT_POOL_ADDRESS_P constants that lack a decl too. (use_toc_relative_ref): Allow CONSTANT_POOL_ADDRESS_P constants for -mcmodel=medium. * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't override user -mfp-in-toc or -msum-in-toc. Default to -mno-fp-in-toc for -mcmodel=medium. From-SVN: r199781
2013-06-06extend.texi (PowerPC AltiVec/VSX Built-in Functions): Document new power8 ↵Michael Meissner10-75/+1047
builtins. [gcc] 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Document new power8 builtins. * config/rs6000/vector.md (and<mode>3): Add a clobber/scratch of a condition code register, to allow 128-bit logical operations to be done in the VSX or GPR registers. (nor<mode>3): Use the canonical form for nor. (eqv<mode>3): Add expanders for power8 xxleqv, xxlnand, xxlorc, vclz*, and vpopcnt* vector instructions. (nand<mode>3): Likewise. (orc<mode>3): Likewise. (clz<mode>2): LIkewise. (popcount<mode>2): Likewise. * config/rs6000/predicates.md (int_reg_operand): Rework tests so that only the GPRs are recognized. * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add support for new power8 builtins. * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8 builtin functions. (xscvdpspn): Likewise. (vclz): Likewise. (vclzb): Likewise. (vclzh): Likewise. (vclzw): Likewise. (vclzd): Likewise. (vpopcnt): Likewise. (vpopcntb): Likewise. (vpopcnth): Likewise. (vpopcntw): Likewise. (vpopcntd): Likewise. (vgbbd): Likewise. (vmrgew): Likewise. (vmrgow): Likewise. (eqv): Likewise. (eqv_v16qi3): Likewise. (eqv_v8hi3): Likewise. (eqv_v4si3): Likewise. (eqv_v2di3): Likewise. (eqv_v4sf3): Likewise. (eqv_v2df3): Likewise. (nand): Likewise. (nand_v16qi3): Likewise. (nand_v8hi3): Likewise. (nand_v4si3): Likewise. (nand_v2di3): Likewise. (nand_v4sf3): Likewise. (nand_v2df3): Likewise. (orc): Likewise. (orc_v16qi3): Likewise. (orc_v8hi3): Likewise. (orc_v4si3): Likewise. (orc_v2di3): Likewise. (orc_v4sf3): Likewise. (orc_v2df3): Likewise. * config/rs6000/rs6000.c (rs6000_option_override_internal): Only allow power8 quad mode in 64-bit. (rs6000_builtin_vectorized_function): Add support to vectorize ISA 2.07 count leading zeros, population count builtins. (rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form V4SF vectors instead of xscvdpsp to avoid IEEE related traps. (builtin_function_type): Add vgbbd builtin function which takes an unsigned argument. (altivec_expand_vec_perm_const): Add support for new power8 merge instructions. * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types, that does not include TImdoe for use with 32-bit. (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn instructions. (UNSPEC_VSX_CVDPSPN): Likewise. (vsx_xscvdpspn): Likewise. (vsx_xscvspdpn): Likewise. (vsx_xscvdpspn_scalar): Likewise. (vsx_xscvspdpn_directmove): Likewise. (vsx_and<mode>3): Split logical operations into 32-bit and 64-bit. Add support to do logical operations on TImode as well as VSX vector types. Allow logical operations to be done in either VSX registers or in general purpose registers in 64-bit mode. Add splitters if GPRs were used. For AND, add clobber of CCmode to allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL encoding. (vsx_and<mode>3_32bit): Likewise. (vsx_and<mode>3_64bit): Likewise. (vsx_ior<mode>3): Likewise. (vsx_ior<mode>3_32bit): Likewise. (vsx_ior<mode>3_64bit): Likewise. (vsx_xor<mode>3): Likewise. (vsx_xor<mode>3_32bit): Likewise. (vsx_xor<mode>3_64bit): Likewise. (vsx_one_cmpl<mode>2): Likewise. (vsx_one_cmpl<mode>2_32bit): Likewise. (vsx_one_cmpl<mode>2_64bit): Likewise. (vsx_nor<mode>3): Likewise. (vsx_nor<mode>3_32bit): Likewise. (vsx_nor<mode>3_64bit): Likewise. (vsx_andc<mode>3): Likewise. (vsx_andc<mode>3_32bit): Likewise. (vsx_andc<mode>3_64bit): Likewise. (vsx_eqv<mode>3_32bit): Add support for power8 xxleqv, xxlnand, and xxlorc instructions. (vsx_eqv<mode>3_64bit): Likewise. (vsx_nand<mode>3_32bit): Likewise. (vsx_nand<mode>3_64bit): Likewise. (vsx_orc<mode>3_32bit): Likewise. (vsx_orc<mode>3_64bit): Likewise. * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment. * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd instruction. (p8_vmrgew): Add power8 vmrgew and vmrgow instructions. (p8_vmrgow): Likewise. (altivec_and<mode>3): Add clobber of CCmode to allow AND using GPRs to be split under VSX. (p8v_clz<mode>2): Add power8 count leading zero support. (p8v_popcount<mode>2): Add power8 population count support. (p8v_vgbbd): Add power8 gather bits by bytes by doubleword support. * config/rs6000/rs6000.md (eqv<mode>3): Add support for powerp eqv instruction. * config/rs6000/altivec.h (vec_eqv): Add defines to export power8 builtin functions. (vec_nand): Likewise. (vec_vclz): Likewise. (vec_vclzb): Likewise. (vec_vclzd): Likewise. (vec_vclzh): Likewise. (vec_vclzw): Likewise. (vec_vgbbd): Likewise. (vec_vmrgew): Likewise. (vec_vmrgow): Likewise. (vec_vpopcnt): Likewise. (vec_vpopcntb): Likewise. (vec_vpopcntd): Likewise. (vec_vpopcnth): Likewise. (vec_vpopcntw): Likewise. [gcc/testsuite] 2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * gcc.target/powerpc/crypto-builtin-1.c: Use effective target powerpc_p8vector_ok instead of powerpc_vsx_ok. * gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests. * lib/target-supports.exp (check_p8vector_hw_available) Add power8 support. (check_effective_target_powerpc_p8vector_ok): Likewise. (is-effective-target): Likewise. (check_vect_support_and_set_flags): Likewise. Co-Authored-By: Pat Haugen <pthaugen@us.ibm.com> Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com> From-SVN: r199767
2013-06-05rs6000.c (print_operand, 'z'): Use DECL_PRESERVE_P instead of ↵David Edelsohn1-1/+1
mark_decl_referenced. * config/rs6000/rs6000.c (print_operand, 'z'): Use DECL_PRESERVE_P instead of mark_decl_referenced. From-SVN: r199698
2013-06-04rs6000.c (output_toc): Correct little-endian float constant output.Alan Modra1-1/+4
* config/rs6000/rs6000.c (output_toc): Correct little-endian float constant output. From-SVN: r199646
2013-06-03re PR c++/57415 (New PPC testsuite failure C++ compound literarl expr ↵Jason Merrill1-10/+28
unimplemented) PR c++/57415 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Use TARGET_EXPR for C++. From-SVN: r199616
2013-05-31predicates.md (rs6000_cbranch_operator): Accept some unordered comparison ↵Eric Botcazou2-23/+44
operators when... * config/rs6000/predicates.md (rs6000_cbranch_operator): Accept some unordered comparison operators when -fno-trapping-math is in effect on the e500. * config/rs6000/rs6000.c (rs6000_generate_compare): Remove dead code and implement unordered comparison operators properly on the e500. From-SVN: r199557
2013-05-31rs6000-opts.h (enum processor_type): Reorder.Segher Boessenkool2-11/+22
2013-05-31 Segher Boessenkool <segher@kernel.crashing.org> gcc/ * config/rs6000/rs6000-opts.h (enum processor_type): Reorder. * config/rs6000/rs6000.md (cpu): Reorder. Split long line. Fix comment. From-SVN: r199555
2013-05-29vector.md (VEC_I): Add support for new power8 V2DI instructions.Michael Meissner6-280/+395
2013-05-29 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI instructions. (VEC_A): Likewise. (VEC_C): Likewise. (vrotl<mode>3): Likewise. (vashl<mode>3): Likewise. (vlshr<mode>3): Likewise. (vashr<mode>3): Likewise. * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add support for power8 V2DI builtins. * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for power8 V2DI builtins. (vupkhsw): Likewise. (vupklsw): Likewise. (vaddudm): Likewise. (vminsd): Likewise. (vmaxsd): Likewise. (vminud): Likewise. (vmaxud): Likewise. (vpkudum): Likewise. (vpksdss): Likewise. (vpkudus): Likewise. (vpksdus): Likewise. (vrld): Likewise. (vsld): Likewise. (vsrd): Likewise. (vsrad): Likewise. (vsubudm): Likewise. (vcmpequd): Likewise. (vcmpgtsd): Likewise. (vcmpgtud): Likewise. (vcmpequd_p): Likewise. (vcmpgtsd_p): Likewise. (vcmpgtud_p): Likewise. (vupkhsw): Likewise. (vupklsw): Likewise. (vaddudm): Likewise. (vmaxsd): Likewise. (vmaxud): Likewise. (vminsd): Likewise. (vminud): Likewise. (vpksdss): Likewise. (vpksdus): Likewise. (vpkudum): Likewise. (vpkudus): Likewise. (vrld): Likewise. (vsld): Likewise. (vsrad): Likewise. (vsrd): Likewise. (vsubudm): Likewise. * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add support for power8 V2DI instructions. * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for power8 V2DI instructions. Combine pack and unpack insns to use an iterator for each mode. Check whether a particular mode supports Altivec instructions instead of just checking TARGET_ALTIVEC. (UNSPEC_VPKUWUM): Likewise. (UNSPEC_VPKSHSS): Likewise. (UNSPEC_VPKSWSS): Likewise. (UNSPEC_VPKUHUS): Likewise. (UNSPEC_VPKSHUS): Likewise. (UNSPEC_VPKUWUS): Likewise. (UNSPEC_VPKSWUS): Likewise. (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise. (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise. (UNSPEC_VPACK_UNS_UNS_SAT): Likewise. (UNSPEC_VPACK_UNS_UNS_MOD): Likewise. (UNSPEC_VUPKHSB): Likewise. (UNSPEC_VUNPACK_HI_SIGN): Likewise. (UNSPEC_VUNPACK_LO_SIGN): Likewise. (UNSPEC_VUPKHSH): Likewise. (UNSPEC_VUPKLSB): Likewise. (UNSPEC_VUPKLSH): Likewise. (VI2): Likewise. (VI_char): Likewise. (VI_scalar): Likewise. (VI_unit): Likewise. (VP): Likewise. (VP_small): Likewise. (VP_small_lc): Likewise. (VU_char): Likewise. (add<mode>3): Likewise. (altivec_vaddcuw): Likewise. (altivec_vaddu<VI_char>s): Likewise. (altivec_vadds<VI_char>s): Likewise. (sub<mode>3): Likewise. (altivec_vsubcuw): Likewise. (altivec_vsubu<VI_char>s): Likewise. (altivec_vsubs<VI_char>s): Likewise. (altivec_vavgs<VI_char>): Likewise. (altivec_vcmpbfp): Likewise. (altivec_eq<mode>): Likewise. (altivec_gt<mode>): Likewise. (altivec_gtu<mode>): Likewise. (umax<mode>3): Likewise. (smax<mode>3): Likewise. (umin<mode>3): Likewise. (smin<mode>3): Likewise. (altivec_vpkuhum): Likewise. (altivec_vpkuwum): Likewise. (altivec_vpkshss): Likewise. (altivec_vpkswss): Likewise. (altivec_vpkuhus): Likewise. (altivec_vpkshus): Likewise. (altivec_vpkuwus): Likewise. (altivec_vpkswus): Likewise. (altivec_vpks<VI_char>ss): Likewise. (altivec_vpks<VI_char>us): Likewise. (altivec_vpku<VI_char>us): Likewise. (altivec_vpku<VI_char>um): Likewise. (altivec_vrl<VI_char>): Likewise. (altivec_vsl<VI_char>): Likewise. (altivec_vsr<VI_char>): Likewise. (altivec_vsra<VI_char>): Likewise. (altivec_vsldoi_<mode>): Likewise. (altivec_vupkhsb): Likewise. (altivec_vupkhs<VU_char>): Likewise. (altivec_vupkls<VU_char>): Likewise. (altivec_vupkhsh): Likewise. (altivec_vupklsb): Likewise. (altivec_vupklsh): Likewise. (altivec_vcmpequ<VI_char>_p): Likewise. (altivec_vcmpgts<VI_char>_p): Likewise. (altivec_vcmpgtu<VI_char>_p): Likewise. (abs<mode>2): Likewise. (vec_unpacks_hi_v16qi): Likewise. (vec_unpacks_hi_v8hi): Likewise. (vec_unpacks_lo_v16qi): Likewise. (vec_unpacks_hi_<VP_small_lc>): Likewise. (vec_unpacks_lo_v8hi): Likewise. (vec_unpacks_lo_<VP_small_lc>): Likewise. (vec_pack_trunc_v8h): Likewise. (vec_pack_trunc_v4si): Likewise. (vec_pack_trunc_<mode>): Likewise. * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8 V2DI builtins. (vec_vmaxsd): Likewise. (vec_vmaxud): Likewise. (vec_vminsd): Likewise. (vec_vminud): Likewise. (vec_vpksdss): Likewise. (vec_vpksdus): Likewise. (vec_vpkudum): Likewise. (vec_vpkudus): Likewise. (vec_vrld): Likewise. (vec_vsld): Likewise. (vec_vsrad): Likewise. (vec_vsrd): Likewise. (vec_vsubudm): Likewise. (vec_vupkhsw): Likewise. (vec_vupklsw): Likewise. Co-Authored-By: Pat Haugen <pthaugen@us.ibm.com> Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com> From-SVN: r199423
2013-05-23add missing fileMichael Meissner1-0/+101
From-SVN: r199233
2013-05-22extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add documentation for ↵Michael Meissner11-49/+689
the power8 crypto builtins. [gcc] 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add documentation for the power8 crypto builtins. * config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md. * config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support macros for defining power8 builtin functions. (BU_P8V_AV_2): Likewise. (BU_P8V_AV_P): Likewise. (BU_P8V_VSX_1): Likewise. (BU_P8V_OVERLOAD_1): Likewise. (BU_P8V_OVERLOAD_2): Likewise. (BU_CRYPTO_1): Likewise. (BU_CRYPTO_2): Likewise. (BU_CRYPTO_3): Likewise. (BU_CRYPTO_OVERLOAD_1): Likewise. (BU_CRYPTO_OVERLOAD_2): Likewise. (XSCVSPDP): Fix typo, point to the correct instruction. (VCIPHER): Add power8 crypto builtins. (VCIPHERLAST): Likewise. (VNCIPHER): Likewise. (VNCIPHERLAST): Likewise. (VPMSUMB): Likewise. (VPMSUMH): Likewise. (VPMSUMW): Likewise. (VPERMXOR_V2DI): Likewise. (VPERMXOR_V4SI: Likewise. (VPERMXOR_V8HI: Likewise. (VPERMXOR_V16QI: Likewise. (VSHASIGMAW): Likewise. (VSHASIGMAD): Likewise. (VPMSUM): Likewise. (VPERMXOR): Likewise. (VSHASIGMA): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define __CRYPTO__ if the crypto instructions are available. (altivec_overloaded_builtins): Add support for overloaded power8 builtins. * config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add support for power8 crypto builtins. (builtin_function_type): Likewise. (altivec_init_builtins): Add support for builtins that take vector long long (V2DI) arguments. * config/rs6000/crypto.md: New file, define power8 crypto instructions. 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * doc/invoke.texi (Option Summary): Add power8 options. (RS/6000 and PowerPC Options): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use constraints.md instead of rs6000.h. Reorder w* constraints. Add wm, wn, wr documentation. * gcc/config/rs6000/constraints.md (wm): New constraint for VSX registers if direct move instructions are enabled. (wn): New constraint for no registers. (wq): New constraint for quad word even GPR registers. (wr): New constraint if 64-bit instructions are enabled. (wv): New constraint if power8 vector instructions are enabled. (wQ): New constraint for quad word memory locations. * gcc/config/rs6000/predicates.md (const_0_to_15_operand): New constraint for 0..15 for crypto instructions. (gpc_reg_operand): If VSX allow registers in VSX registers as well as GPR and floating point registers. (int_reg_operand): New predicate to match only GPR registers. (base_reg_operand): New predicate to match base registers. (quad_int_reg_operand): New predicate to match even GPR registers for quad memory operations. (vsx_reg_or_cint_operand): New predicate to allow vector logical operations in both GPR and VSX registers. (quad_memory_operand): New predicate for quad memory operations. (reg_or_indexed_operand): New predicate for direct move support. * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS. (ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8). (POWERPC_MASKS): Add power8 options. (power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the various options. * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8. * gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation. (-mpower8-fusion): New power8 options. (-mpower8-fusion-sign): Likewise. (-mpower8-vector): Likewise. (-mcrypto): Likewise. (-mdirect-move): Likewise. (-mquad-memory): Likewise. * gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for power8. (rs6000_hard_regno_mode_ok): Make PTImode only match even GPR registers. (rs6000_debug_reg_print): Print the base register class if -mdebug=reg. (rs6000_debug_vector_unit): Add p8_vector. (rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint definitions. Also print fusion state. (rs6000_init_hard_regno_mode_ok): Set up power8 constraints. (rs6000_builtin_mask_calculate): Add power8 builtin support. (rs6000_option_override_internal): Add support for power8. (rs6000_common_init_builtins): Add debugging for skipped builtins if -mdebug=builtin. (rs6000_adjust_cost): Add power8 support. (rs6000_issue_rate): Likewise. (insn_must_be_first_in_group): Likewise. (insn_must_be_last_in_group): Likewise. (force_new_group): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a power8 capable assembler, default to power7 options. (TARGET_DIRECT_MOVE): Likewise. (TARGET_CRYPTO): Likewise. (TARGET_P8_VECTOR): Likewise. (VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support. (VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise. (VECTOR_MEM_P8_VECTOR_P): Likewise. (VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise. (VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise. (TARGET_XSCVDPSPN): Likewise. (TARGET_XSCVSPDPN): Likewsie. (TARGET_SYNC_HI_QI): Likewise. (TARGET_SYNC_TI): Likewise. (MASK_CRYPTO): Likewise. (MASK_DIRECT_MOVE): Likewise. (MASK_P8_FUSION): Likewise. (MASK_P8_VECTOR): Likewise. (REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the TFmode temporary used by some of the direct move instructions to get two FP temporary registers does not force creation of a stack frame. (VLOGICAL_REGNO_P): Allow vector logical operations in GPRs. (MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so that any VSX registers are tieable, even if they are also an Altivec vector mode. (r6000_reg_class_enum): Add wm, wr, wv constraints. (RS6000_BTM_P8_VECTOR): Power8 builtin support. (RS6000_BTM_CRYPTO): Likewise. (RS6000_BTM_COMMON): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power8. * config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise. (enum rs6000_vector): Add power8 vector support. [gcc/testsuite] 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com> Pat Haugen <pthaugen@us.ibm.com> Peter Bergner <bergner@vnet.ibm.com> * gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8 crypto builtins. Co-Authored-By: Pat Haugen <pthaugen@us.ibm.com> Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com> From-SVN: r199217
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