diff options
| author | Peter Bergner <bergner@vnet.ibm.com> | 2013-08-19 12:49:33 -0500 |
|---|---|---|
| committer | Peter Bergner <bergner@gcc.gnu.org> | 2013-08-19 12:49:33 -0500 |
| commit | e2323f5b3335d70d4a1e04c3f251a977a400e5fa (patch) | |
| tree | 2160dd15d5baffff0f1a85c953a8333adee72fa8 /gcc/config/rs6000 | |
| parent | 7a3def9768c4ad790f4d5f14c1bf17d39b184987 (diff) | |
| download | gcc-e2323f5b3335d70d4a1e04c3f251a977a400e5fa.zip gcc-e2323f5b3335d70d4a1e04c3f251a977a400e5fa.tar.gz gcc-e2323f5b3335d70d4a1e04c3f251a977a400e5fa.tar.bz2 | |
builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin.
gcc/
* builtins.def (BUILT_IN_FABSD32): New DFP ABS builtin.
(BUILT_IN_FABSD64): Likewise.
(BUILT_IN_FABSD128): Likewise.
* builtins.c (expand_builtin): Add support for new DFP ABS builtins.
(fold_builtin_1): Likewise.
* config/rs6000/dfp.md (*negtd2_fpr): Handle non-overlapping destination
and source operands.
(*abstd2_fpr): Likewise.
(*nabstd2_fpr): Likewise.
gcc/testsuite/
* gcc.target/powerpc/dfp-dd-2.c: New test.
* gcc.target/powerpc/dfp-td-2.c: Likewise.
* gcc.target/powerpc/dfp-td-3.c: Likewise.
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r201849
Diffstat (limited to 'gcc/config/rs6000')
| -rw-r--r-- | gcc/config/rs6000/dfp.md | 33 |
1 files changed, 21 insertions, 12 deletions
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index 052ac48..9a84623 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -132,11 +132,14 @@ "") (define_insn "*negtd2_fpr" - [(set (match_operand:TD 0 "gpc_reg_operand" "=d") - (neg:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] + [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") + (neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" - "fneg %0,%1" - [(set_attr "type" "fp")]) + "@ + fneg %0,%1 + fneg %0,%1\;fmr %L0,%L1" + [(set_attr "type" "fp") + (set_attr "length" "4,8")]) (define_expand "abstd2" [(set (match_operand:TD 0 "gpc_reg_operand" "") @@ -145,18 +148,24 @@ "") (define_insn "*abstd2_fpr" - [(set (match_operand:TD 0 "gpc_reg_operand" "=d") - (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] + [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") + (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" - "fabs %0,%1" - [(set_attr "type" "fp")]) + "@ + fabs %0,%1 + fabs %0,%1\;fmr %L0,%L1" + [(set_attr "type" "fp") + (set_attr "length" "4,8")]) (define_insn "*nabstd2_fpr" - [(set (match_operand:TD 0 "gpc_reg_operand" "=d") - (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))] + [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d") + (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))] "TARGET_HARD_FLOAT && TARGET_FPRS" - "fnabs %0,%1" - [(set_attr "type" "fp")]) + "@ + fnabs %0,%1 + fnabs %0,%1\;fmr %L0,%L1" + [(set_attr "type" "fp") + (set_attr "length" "4,8")]) ;; Hardware support for decimal floating point operations. |