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path: root/gcc/config/rs6000/spe.md
AgeCommit message (Expand)AuthorFilesLines
2009-12-09vector.md (absv2sf2, [...]): New expanders.Nathan Froyd1-5/+5
2009-09-15re PR target/41175 (-Os generates significantly larger code)Nathan Froyd1-9/+9
2009-06-23Step 1 of VSX changes: Powerpc infrstructure changesMichael Meissner1-2/+2
2009-02-20Update Copyright years for files modified in 2008 and/or 2009.Jakub Jelinek1-1/+1
2008-12-18rs6000.c (rs6000_generate_compare): Condition choice of e500 comparison instr...Joseph Myers1-18/+30
2008-12-05rs6000.md (move_from_CR_gt_bit): Enable for TARGET_HARD_FLOAT && !TARGET_FPRS...Joseph Myers1-1/+1
2008-11-03Revert:Nathan Froyd1-9/+9
2008-11-01rs6000.c (no_global_regs_above): Fix precedence problem.Nathan Froyd1-9/+9
2008-06-26rs6000.c (emit_allocate_stack): Add copy_r11 parameter.Nathan Froyd1-0/+38
2007-08-31Support for PowerPC 750CL paired-single instructions David Edelsohn1-1/+1
2007-08-22md.texi (Iterators): Renamed from Macros.Hans-Peter Nilsson1-3/+3
2007-08-02host-hpux.c: Change copyright header to refer to version 3 of the GNU General...Nick Clifton1-4/+3
2007-07-13spe.md (SPE_ACC_REGNO): Delete definition.David Edelsohn1-4/+1
2007-06-25spe.md (*frob_ti_tf_2): Specify an input_operand as the source of the set.Nathan Froyd1-1/+1
2007-04-19spe.md (*frob_tf_ti, [...]): Add length attributes.Joseph Myers1-16/+32
2007-01-23rs6000-c.c (rs6000_cpu_cpp_builtins): Define _SOFT_DOUBLE if doubles use soft...Joseph Myers1-19/+333
2006-11-22spe.md (SPE64): New mode macro.Joseph Myers1-10/+35
2006-11-18spe.md (movv4hi_internal): Add alternative for easy vector constant loads.Joseph Myers1-3/+4
2006-11-16spe.md (frob_di_df_2): Handle non-offsettable memory operand.Joseph Myers1-0/+5
2006-09-11re PR target/27287 (returning constant double)Guenter Roeck1-7/+24
2006-07-14re PR target/27287 (returning constant double)Eliot Dresselhaus1-4/+6
2005-06-25Update FSF address.R. Kelley Cook1-2/+2
2005-04-24rs6000.c (rs6000_override_options): Use gcc_assert and gcc_unreachable as app...Nathan Sidwell1-2/+2
2005-03-08rs6000-protos.h: Rename output_e500_flip_eq_bit to output_e500_flip_gt_bit.Aldy Hernandez1-2/+13
2005-01-18darwin.c, [...]: Update copyright.Kazu Hirata1-1/+1
2005-01-14rs6000.c (rs6k_nonimmediate_operand): Rename to rs6000_nonimmediate_operand.David Edelsohn1-1/+1
2005-01-14rs6000.h (CLASS_MAX_NREGS): DF goes in 1 register on e500v2.Aldy Hernandez1-1/+38
2004-11-10rs6000.md (fix_truncdfsi2): Handle e500 doubles.Aldy Hernandez1-4/+0
2004-10-22spe.md (spe_extendsfdf2): New.Aldy Hernandez1-0/+116
2004-10-21config.gcc: Add support for --enable-e500_double.Aldy Hernandez1-1/+71
2004-07-28rs6000.md ("move_from_CR_gt_bit"): Rename to move_from_CR_eq_bit.Aldy Hernandez1-2/+2
2004-07-15rs6000.md ("*cceq_ior_compare"): Allow unconditionally.Aldy Hernandez1-18/+0
2004-05-11spe.md (spe_evneg): Rename to negv2si2.Aldy Hernandez1-1/+1
2004-05-09* config/rs6000/spe.md ("tstsflt_gpr"): Fix typo in unspec.Aldy Hernandez1-1/+1
2004-04-20rs6000.md (UNSPEC_MV_CR_GT): New constant.Aldy Hernandez1-13/+56
2004-02-27rs6000.md: Add fixuns_truncsfsi2 and fix_truncsfsi2.Aldy Hernandez1-17/+8
2004-02-24spe.md (spe_fix_truncsfsi2): Delete.Aldy Hernandez1-13/+15
2004-02-19spe.md (spe_fixunssfsi2): Rename to spe_fixuns_truncsfsi2.Aldy Hernandez1-2/+2
2004-02-18cfgloop.h, [...]: Update copyright.Kazu Hirata1-1/+1
2004-02-11spe.md ("*movv2si_internal"): Check for register operand.Aldy Hernandez1-4/+14
2003-08-18* config/rs6000/spe.md ("*nabssf2_gpr"): New.Aldy Hernandez1-0/+7
2003-06-19spe.md ("spe_evfscfsi"): Change operand types.Aldy Hernandez1-2/+2
2003-06-12spe.md: Change all clobbers of the accumulator to sets.Aldy Hernandez1-96/+96
2003-05-07spe.h: Reverse arguments for __ev_subfw.Aldy Hernandez1-1/+1
2003-04-13Replace "GNU CC" with "GCC"Nick Clifton1-12/+12
2003-04-01simd-3.c: New.Aldy Hernandez1-48/+37
2003-03-268540.md: New file.Vladimir Makarov1-22/+22
2003-02-10[multiple changes]Aldy Hernandez1-37/+59
2003-01-30aix43.h: Fix comment typos.Kazu Hirata1-2/+2
2002-12-03spe.md (*movv1di_const0): New pattern.Aldy Hernandez1-0/+7