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path: root/gcc/config/rs6000/rs6000.c
AgeCommit message (Expand)AuthorFilesLines
2022-01-11rs6000: powerpc suboptimal boolean test of contiguous bits [PR102239]Xionghu Luo1-0/+7
2022-01-10rs6000: Remove useless code related to -mno-power10Kewen Lin1-1/+0
2022-01-04ipa-inline: Add target info into fn summary [PR102059]Kewen Lin1-1/+77
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-15Generate XXSPLTIDP for vectors on power10.Michael Meissner1-0/+108
2021-12-15Generate XXSPLTIW on power10.Michael Meissner1-0/+83
2021-12-15Add LXVKQ support.Michael Meissner1-0/+62
2021-12-15Add new constant data structure.Michael Meissner1-0/+253
2021-12-14rs6000: Rename arrays to remove temporary _x suffixBill Schmidt1-29/+29
2021-12-14rs6000: Rename functions with "new" in their namesBill Schmidt1-25/+6
2021-12-14rs6000: Remove rs6000-builtin.def and associated data and functionsBill Schmidt1-3/+0
2021-12-14rs6000: Do not allow combining of multiple assemble quads [PR103548]Peter Bergner1-2/+4
2021-12-14rs6000: Remove new_builtins_are_live and dead code it was guardingBill Schmidt1-249/+7
2021-12-03rs6000: Fix up flag_shrink_wrap handling in presence of -mrop-protect [PR101324]Martin Liska1-4/+4
2021-12-03rs6000: Fix use of wrong enum for built-in function codeBill Schmidt1-2/+2
2021-12-03pch: Add support for PCH for relocatable executables [PR71934]Jakub Jelinek1-13/+17
2021-12-01rs6000: Mirror fix for PR102347 in new builtins supportBill Schmidt1-1/+0
2021-11-29rs6000: Modify the way for extra penalized costKewen Lin1-16/+19
2021-11-10vect: Pass scalar_costs to finish_costRichard Sandiford1-3/+3
2021-11-08rs6000: Miscellaneous uses of rs6000_builtins_decl_xBill Schmidt1-3/+14
2021-11-04vect: Convert cost hooks to classesRichard Sandiford1-118/+78
2021-10-28rs6000: Optimize __builtin_shuffle when it's used to zero the upper bits [PR1...Xionghu Luo1-3/+36
2021-10-28rs6000: Fix ICE of vect cost related to V1TI [PR102767]Kewen Lin1-31/+33
2021-10-27rs6000: Fix wrong code generation for vec_sel [PR94613]Xionghu Luo1-11/+8
2021-10-19aix: ensure reference to __tls_get_addr is in text section.Clément Chigot1-5/+5
2021-10-19rs6000: Remove unspecs for vec_mrghl[bhw]Xionghu Luo1-37/+38
2021-10-14rs6000: Fix memory leak in rs6000_density_testRichard Sandiford1-9/+8
2021-10-08Come up with OPTION_SET_P macro.Martin Liska1-35/+35
2021-09-21rs6000: Parameterize some const values for density testKewen Lin1-15/+7
2021-09-17rs6000: Support for vectorizing built-in functionsBill Schmidt1-0/+257
2021-09-15rs6000: fix xcoff section encodingDavid Edelsohn1-2/+2
2021-09-15rs6000: fix symtab_node::get == NULL issueMartin Liska1-0/+1
2021-09-14rs6000: Disable optimizing multiple xxsetaccz instructions into one xxsetacczPeter Bergner1-1/+1
2021-09-13rs6000: Add load density heuristicKewen Lin1-9/+116
2021-09-13rs6000: Remove typedef for struct rs6000_cost_dataKewen Lin1-3/+3
2021-08-30Enable store fusion on Power10.Pat Haugen1-0/+95
2021-08-26rs6000: Make some BIFs vectorized on P10Kewen Lin1-0/+53
2021-08-26aix: packed struct alignment [PR102068]David Edelsohn1-1/+1
2021-08-15aix: 64 bit AIX TLS libpthread dependency.Clément Chigot1-1/+13
2021-08-09Verify destination[source] of a load[store] instruction is a register.Pat Haugen1-2/+12
2021-08-06rs6000: Fix restored rs6000_long_double_type_sizeMartin Liska1-0/+2
2021-07-29Use preferred mode for doloop IV [PR61837]Jiufu Guo1-0/+11
2021-07-20rs6000: Fix up easy_vector_constant_msb handling [PR101384]Jakub Jelinek1-18/+41
2021-07-15pass location to md_asm_adjustTrevor Saunders1-1/+1
2021-07-14rs6000: Generate an lxvp instead of two adjacent lxv instructionsPeter Bergner1-18/+64
2021-07-14rs6000: Move rs6000_split_multireg_move to later in filePeter Bergner1-376/+375
2021-07-12Change rs6000_const_f32_to_i32 return type.Michael Meissner1-2/+4
2021-07-01Add IEEE 128-bit fp conditional move on PowerPC.Michael Meissner1-2/+30
2021-07-01Change the type of predicates to bool.Uros Bizjak1-1/+1
2021-06-29aix: align text CSECTs to at least 32 bytes.David Edelsohn1-1/+5
generated by cgit v1.1 at 2024-11-06 17:49:48 +0000