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2024-03-19RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]Edwin Lu1-1/+2
We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and there is nothing to advance, but that is not the case for (...) functions returning by hidden reference which have one such artificial argument. This causes gcc.dg/c23-stdarg-[68].c to fail Fix the issue by checking if arg.type is NULL as r14-9503-g218d1749612 explains Tested on linux rv64gcv. gcc/ChangeLog: PR target/114175 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions if arg.type is NULL
2024-03-18[PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett5-1/+50
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Create XCVbi extension support. * config/riscv/riscv.opt: Likewise. * config/riscv/corev.md: Implement cv_branch<mode> pattern for cv.beqimm and cv.bneimm. * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V branch instruction pattern. * config/riscv/constraints.md: Implement constraints cv_bi_s5 - signed 5-bit immediate. * config/riscv/predicates.md: Implement predicate const_int5s_operand - signed 5 bit immediate. * doc/sourcebuild.texi: Add XCVbi documentation. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test. * lib/target-supports.exp: Add proc for XCVbi.
2024-03-18[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.Chen Jiawei5-1/+174
This patch add XiangShan Nanhu cpu microarchitecture, Nanhu is a 6-issue, superscalar, out-of-order processor. More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): New def. (RISCV_CORE): Ditto. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New option. * config/riscv/riscv.cc: New def. * config/riscv/riscv.md: New include. * config/riscv/xiangshan.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test. Co-Authored by: Lin Jiawei <jiawei.lin@epfl.ch>
2024-03-15Regenerate opt.urlsYunQiang Su1-1/+1
Fixes: acc38ff59976 ("MIPS: Add -m(no-)strict-align option") gcc/ChangeLog: * config/riscv/riscv.opt.urls: Regenerated. * config/rs6000/sysv4.opt.urls: Likewise. * config/xtensa/xtensa.opt.urls: Likewise.
2024-03-12RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC]Pan Li1-5/+5
Notice some code style issue(s) when add __riscv_v_fixed_vlen, includes: * Meanless empty line. * Line greater than 80 chars. * Indent with 3 space(s). * Argument unalignment. gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix code style greater than 80 chars. (riscv_cpu_cpp_builtins): Fix useless empty line, indent with 3 space(s) and argument unalignment. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-03-08RISC-V: Fix ICE in riscv vector costsdemin.han1-0/+2
The following code can result in ICE: -march=rv64gcv --param riscv-autovec-lmul=dynamic -O3 char *jpeg_difference7_input_buf; void jpeg_difference7(int *diff_buf) { unsigned width; int samp, Rb; while (--width) { Rb = samp = *jpeg_difference7_input_buf; *diff_buf++ = -(int)(samp + (long)Rb >> 1); } } One biggest_mode update missed in one branch and trigger assertion fail. gcc_assert (biggest_size >= mode_size); Tested On RV64 and no regression. PR target/114264 gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc: Fix ICE gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr114264.c: New test. Signed-off-by: demin.han <demin.han@starfivetech.com>
2024-03-07RISC-V: Refactor expand_vec_cmp [NFC]demin.han2-31/+15
There are two expand_vec_cmp functions. They have same structure and similar code. We can use default arguments instead of overloading. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments (expand_vec_cmp_float): Adapt arguments Signed-off-by: demin.han <demin.han@starfivetech.com>
2024-03-06RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].Robin Dapp1-48/+48
Three-operand instructions like vmacc are modeled with an implicit output reload when the output does not match one of the operands. For this we use vmv.v.v which is subject to length masking. In a situation where the current vl is less than the full vlenb and the fma's result value is used as input for a vector reduction (which is never length masked) we effectively only reduce vl elements. The masked-out elements are relevant for the reduction, though, leading to a wrong result. This patch replaces the vmv reloads by full-register reloads. gcc/ChangeLog: PR target/114200 PR target/114202 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114200.c: New test. * gcc.target/riscv/rvv/autovec/pr114202.c: New test.
2024-03-06RISC-V: Adjust vec unit-stride load/store costs.Robin Dapp2-10/+86
Scalar loads provide offset addressing while unit-stride vector instructions cannot. The offset must be loaded into a general-purpose register before it can be used. In order to account for this, this patch adds an address arithmetic heuristic that keeps track of data reference operands. If we haven't seen the operand before we add the cost of a scalar statement. This helps to get rid of an lbm regression when vectorizing (roughly 0.5% fewer dynamic instructions). gcc5 improves by 0.2% and deepsjeng by 0.25%. wrf and nab degrade by 0.1%. This is because before we now adjust the cost of SLP as well as loop-vectorized instructions whereas we would only adjust loop-vectorized instructions before. Considering higher scalar_to_vec costs (3 vs 1) for all vectorization types causes some snippets not to get vectorized anymore. Given these costs the decision looks correct but appears worse when just counting dynamic instructions. In total SPECint 2017 has 4 bln dynamic instructions less and SPECfp 0.7 bln. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move... (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store offset handling. (costs::add_stmt_cost): Also adjust cost for statements without stmt_info. * config/riscv/riscv-vector-costs.h: Define zero constant. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c: New test.
2024-03-06[PR target/113001] Fix incorrect operand swapping in conditional moveJeff Law1-2/+0
This bug totally fell off my radar. Sorry about that. We have some special casing the conditional move expander to simplify a conditional move when comparing a register against zero and that same register is one of the arms. Specifically a (eq (reg) (const_int 0)) where reg is also the true arm or (ne (reg) (const_int 0)) where reg is the false arm need not use the fully generalized conditional move, thus saving an instruction for those cases. In the NE case we swapped the operands, but didn't swap the condition, which led to the ICE due to an unrecognized pattern. THe backend actually has distinct patterns for those two cases. So swapping the operands is neither needed nor advisable. Regression tested on rv64gc and verified the new tests pass. Pushing to the trunk. PR target/113001 PR target/112871 gcc/ * config/riscv/riscv.cc (expand_conditional_move): Do not swap operands when the comparison operand is the same as the false arm for a NE test. gcc/testsuite * gcc.target/riscv/zicond-ice-3.c: New test. * gcc.target/riscv/zicond-ice-4.c: New test.
2024-03-05RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC]Pan Li1-4/+0
Cleanup mode_size related code which is not used anymore. Below tests are passed for this patch. * The RVV fully regresssion test. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused mode_size related code. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-03-04Regenerate opt.urlsMark Wielaard1-1/+1
There were several commits that didn't regenerate the opt.urls files. Fixes: 438ef143679e ("rs6000: Neuter option -mpower{8,9}-vector") Fixes: 50c549ef3db6 ("gccrs: enable -Winfinite-recursion warnings by default") Fixes: 25bb8a40abd9 ("Move docs for -Wuse-after-free and -Wuseless-cast") Fixes: 48448055fb70 ("AVR: Support .rodata in Flash for AVR64* and AVR128*") Fixes: 42503cc257fb ("AVR: Document option -mskip-bug") Fixes: 7de5bb642c12 ("i386: [APX] Document inline asm behavior and new switch") Fixes: 49a14ee488b8 ("Add -mevex512 into invoke.texi") Fixes: 4666cbde5e6d ("Sort warning options in c-family/c.opt.") Fixes: cda383616183 ("AVR: target/114100 - Better indirect accesses for reduced Tiny") gcc/c-family/ChangeLog: * c.opt.urls: Regenerate. gcc/ChangeLog: * common.opt.urls: Regenerate. * config/avr/avr.opt.urls: Likewise. * config/i386/i386.opt.urls: Likewise. * config/pru/pru.opt.urls: Likewise. * config/riscv/riscv.opt.urls: Likewise. * config/rs6000/rs6000.opt.urls: Likewise. gcc/rust/ChangeLog: * lang.opt.urls: Regenerate.
2024-03-01[14 regression] Fix insn types in risc-v portJeff Law1-14/+14
So one of the broad goals we've had over the last few months has been to ensure that every insn has a scheduling type and that every insn is associated with an insn reservation in the scheduler. This avoids some amazingly bad behavior in the scheduler. I won't go through the gory details. I was recently analyzing a code quality regression with dhrystone (ugh!) and one of the issues was poor scheduling which lengthened the lifetime of a pseudo and ultimately resulted in needing an additional callee saved register save/restore. This was ultimately tracked down incorrect types on a few patterns. So I did an audit of all the patterns that had types added/changed as part of this effort and found a variety of problems, primarily in the various move patterns and extension patterns. This is a regression relative to gcc-13. Naturally the change in types affects scheduling, which in turn changes the precise code we generate and causes some testsuite fallout. I considered updating the regexps since the change in the resulting output is pretty consistent. But of course the test would still be sensitive to things like load latency. So instead I just turned off the 2nd phase scheduler in the affected tests. Bootstrapped and regression tested on rv64gc-linux-gnu. gcc * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix type attribute. (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise. (movdi_32bit, movdi_64bit, movsi_internal): Likewise. (movhi_internal, movqi_internal): Likewise. (movsf_softfloat, movsf_hardfloat): Likewise. (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise. (movdf_softfloat): Likewise. gcc/testsuite * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Turn off second phase scheduler. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
2024-03-01RISC-V: Add riscv_vector_cc function attributexuli1-8/+47
Standard vector calling convention variant will only enabled when function has vector argument or returning value by default, however user may also want to invoke function without that during a vectorized loop at some situation, but it will cause a huge performance penalty due to vector register store/restore. So user can declare function with this riscv_vector_cc attribute like below, that could enforce function will use standard vector calling convention variant. void foo() __attribute__((riscv_vector_cc)); [[riscv::vector_cc]] void foo(); // For C++11 and C23 For more details please reference the below link. https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 gcc/ChangeLog: * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc attribute to riscv_attribute_table. (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function. (riscv_fntype_abi): Add riscv_vector_cc attribute check. * doc/extend.texi: Add riscv_vector_cc attribute description. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New test. * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c: New test. * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New test.
2024-03-01RISC-V: Introduce gcc option mrvv-vector-bits for RVVPan Li6-42/+45
This patch would like to introduce one new gcc option for RVV. To appoint the bits size of one RVV vector register. Valid arguments to '-mrvv-vector-bits=' are: * scalable * zvl The scalable will pick up the zvl*b in the march as the minimal vlen. For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b and mrvv-vector-bits=scalable. The zvl will pick up the zvl*b in the march as exactly vlen. For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b and mrvv-vector-bits=zvl. The internal option --param=riscv-autovec-preference will be replaced by option -mrvv-vector-bits. Aka: * -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable * -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmax You can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none. The internal option --param=riscv-autovec-preference is unavailable after this patch. Given below sample for more details: void test_rvv_vector_bits () { vint32m1_t x; asm volatile ("def %0": "=vr"(x)); asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); asm volatile ("use %0": : "vr"(x)); } With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128) csrr t0,vlenb sub sp,sp,t0 def v1 vs1r.v v1,0(sp) vl1re32.v v1,0(sp) use v1 csrr t0,vlenb add sp,sp,t0 jr ra With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128) addi sp,sp,-16 def v1 vs1r.v v1,0(sp) vl1re32.v v1,0(sp) use v1 addi sp,sp,16 jr ra The below test are passed for this patch. * The riscv fully regression test. PR target/112817 gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL. * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove. (enum rvv_vector_bits_enum): New enum for different RVV vector bits. * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update comments for option replacement. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of riscv_autovec_preference to rvv_vector_bits. (vls_mode_valid_p): Ditto. (estimated_poly_value): Ditto. * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to vector chunks and honor new option mrvv-vector-bits. (riscv_override_options_internal): Update comments and rename the vector chunks. * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove internal option param=riscv-autovec-preference. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C: Replace param=riscv-autovec-preference to mrvv-vector-bits. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto. * gcc.target/riscv/rvv/autovec/align-1.c: Ditto. * gcc.target/riscv/rvv/autovec/align-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-1.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-2.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-3.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-4.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-5.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-6.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c: * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito. * gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito. * gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito. * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito. * gcc.target/riscv/rvv/autovec/pr110950.c: Diito. * gcc.target/riscv/rvv/autovec/pr110964.c: Diito. * gcc.target/riscv/rvv/autovec/pr110989.c: Diito. * gcc.target/riscv/rvv/autovec/pr111232.c: Diito. * gcc.target/riscv/rvv/autovec/pr111295.c: Diito. * gcc.target/riscv/rvv/autovec/pr111313.c: Diito. * gcc.target/riscv/rvv/autovec/pr112326.c: Diito. * gcc.target/riscv/rvv/autovec/pr112552.c: Diito. * gcc.target/riscv/rvv/autovec/pr112554.c: Diito. * gcc.target/riscv/rvv/autovec/pr112561.c: Diito. * gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito. * gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112854.c: Diito. * gcc.target/riscv/rvv/autovec/pr112872.c: Diito. * gcc.target/riscv/rvv/autovec/pr112999.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/scalable-1.c: Diito. * gcc.target/riscv/rvv/autovec/series-1.c: Diito. * gcc.target/riscv/rvv/autovec/series_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito. * gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito. * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/v-1.c: Diito. * gcc.target/riscv/rvv/autovec/v-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito. * gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito. * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito. * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito. * gcc.target/riscv/rvv/base/cpymem-1.c: Diito. * gcc.target/riscv/rvv/base/cpymem-2.c: Diito. * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito. * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito. * gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito. * gcc.target/riscv/rvv/base/pr110119-1.c: Diito. * gcc.target/riscv/rvv/base/pr110119-2.c: Diito. * gcc.target/riscv/rvv/base/pr111720-0.c: Diito. * gcc.target/riscv/rvv/base/pr111720-1.c: Diito. * gcc.target/riscv/rvv/base/pr111720-10.c: Diito. * gcc.target/riscv/rvv/base/pr111720-2.c: Diito. * gcc.target/riscv/rvv/base/pr111720-3.c: Diito. * gcc.target/riscv/rvv/base/pr111720-4.c: Diito. * gcc.target/riscv/rvv/base/pr111720-5.c: Diito. * gcc.target/riscv/rvv/base/pr111720-6.c: Diito. * gcc.target/riscv/rvv/base/pr111720-7.c: Diito. * gcc.target/riscv/rvv/base/pr111720-8.c: Diito. * gcc.target/riscv/rvv/base/pr111720-9.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-1.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-2.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-3.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-4.c: Diito. * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito. * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito. * gcc.target/riscv/rvv/rvv.exp: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito. * gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito. * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-02-29RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64Kito Cheng1-0/+9
atomic_compare_and_swapsi will use lr.w to do obtain the original value, which sign extends to DI. RV64 only has DI comparisons, so we also need to sign extend the expected value to DI as otherwise the comparison will fail when the expected value has the 32nd bit set. gcc/ChangeLog: PR target/114130 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign extend the expected value if needed. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr114130.c: New. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-02-23RISC-V: Fix vec_init for simple sequences [PR114028].Robin Dapp1-1/+24
For a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to construct a "superword" of two "_a"s. This only works for modes < Pmode when we can "shift and or" both halves into one Pmode register. This patch disallows the optimization for inner_mode == Pmode and emits a simple broadcast in such a case. gcc/ChangeLog: PR target/114028 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p): Return false if inner mode is already Pmode. (rvv_builder::is_all_same_sequence): New function. (expand_vec_init): Emit broadcast if sequence is all same. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114028.c: New test.
2024-02-23RISC-V: Point our Python scripts at python3Palmer Dabbelt2-2/+2
This builds for me, and I frequently have python-is-python3 type packages installed so I think I've been implicitly testing it for a while. Looks like Kito's tested similar configurations, and the bugzilla indicates we should be moving over. gcc/ChangeLog: PR other/109668 * config/riscv/arch-canonicalize: Move to python3 * config/riscv/multilib-generator: Likewise
2024-02-22RISC-V: Upgrade RVV intrinsic version to 0.12Pan Li1-1/+1
Upgrade the version of RVV intrinsic from 0.11 to 0.12. PR target/114017 gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade the version to 0.12. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-__riscv_v_intrinsic.c: Update the version to 0.12. * gcc.target/riscv/rvv/base/pr114017-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-02-21RISC-V: Enable assert for insn_has_dfa_reservationEdwin Lu1-2/+0
Enables assert that every typed instruction is associated with a dfa reservation gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-02-21RISC-V: Add vector related pipelinesEdwin Lu3-126/+145
Creates new generic vector pipeline file common to all cpu tunes. Moves all vector related pipelines from generic-ooo to generic-vector-ooo. Creates new vector crypto related insn reservations. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo): Move reservation (generic_ooo_vec_load): Ditto (generic_ooo_vec_store): Ditto (generic_ooo_vec_loadstore_seg): Ditto (generic_ooo_vec_alu): Ditto (generic_ooo_vec_fcmp): Ditto (generic_ooo_vec_imul): Ditto (generic_ooo_vec_fadd): Ditto (generic_ooo_vec_fmul): Ditto (generic_ooo_crypto): Ditto (generic_ooo_perm): Ditto (generic_ooo_vec_reduction): Ditto (generic_ooo_vec_ordered_reduction): Ditto (generic_ooo_vec_idiv): Ditto (generic_ooo_vec_float_divsqrt): Ditto (generic_ooo_vec_mask): Ditto (generic_ooo_vec_vesetvl): Ditto (generic_ooo_vec_setrm): Ditto (generic_ooo_vec_readlen): Ditto * config/riscv/riscv.md: Include generic-vector-ooo * config/riscv/generic-vector-ooo.md: New file. To here Signed-off-by: Edwin Lu <ewlu@rivosinc.com> Co-authored-by: Robin Dapp <rdapp.gcc@gmail.com>
2024-02-21RISC-V: Add non-vector types to dfa pipelinesEdwin Lu8-69/+117
This patch adds non-vector related insn reservations and updates/creates new insn reservations so all non-vector typed instructions have a reservation. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation (generic_ooo_branch): Ditto * config/riscv/generic.md (generic_sfb_alu): Ditto (generic_fmul_half): Ditto * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation (sifive_7_popcount): Ditto * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto * config/riscv/vector.md: Change rdfrm to fmove * config/riscv/zc.md: Change pushpop to load/store Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-02-19RISC-V: Suppress the vsetvl fusion for conflict successorsJuzhe-Zhong1-0/+25
Update in v2: Add dump information. This patch fixes the following ineffective vsetvl insertion: void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2) { for (size_t i = 0; i < n; i++) { if (i == cond) { vint8mf8_t v = *(vint8mf8_t*)(in + i + 100); *(vint8mf8_t*)(out + i + 100) = v; } else if (i == cond2) { vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 200); *(vfloat32mf2_t*)(out + i + 200) = v; } else if (i == (cond2 - 1)) { vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300); *(vuint16mf2_t*)(out + i + 300) = v; } else { vint8mf4_t v = *(vint8mf4_t*)(in + i + 400); *(vint8mf4_t*)(out + i + 400) = v; } } } Before this patch: f: .LFB0: .cfi_startproc beq a2,zero,.L12 addi a7,a0,400 addi a6,a1,400 addi a0,a0,1600 addi a1,a1,1600 li a5,0 addi t6,a4,-1 vsetvli t3,zero,e8,mf8,ta,ma ---> ineffective uplift .L7: beq a3,a5,.L15 beq a4,a5,.L16 beq t6,a5,.L17 vsetvli t1,zero,e8,mf4,ta,ma vle8.v v1,0(a0) vse8.v v1,0(a1) vsetvli t3,zero,e8,mf8,ta,ma .L4: addi a5,a5,1 addi a7,a7,4 addi a6,a6,4 addi a0,a0,4 addi a1,a1,4 bne a2,a5,.L7 .L12: ret .L15: vle8.v v1,0(a7) vse8.v v1,0(a6) j .L4 .L17: vsetvli t1,zero,e8,mf4,ta,ma addi t5,a0,-400 addi t4,a1,-400 vle16.v v1,0(t5) vse16.v v1,0(t4) vsetvli t3,zero,e8,mf8,ta,ma j .L4 .L16: addi t5,a0,-800 addi t4,a1,-800 vle32.v v1,0(t5) vse32.v v1,0(t4) j .L4 It's obvious that we are hoisting the e8mf8 vsetvl to the top. It's ineffective since e8mf8 comes from low probability block which is if (i == cond). For this case, we disable such fusion. After this patch: f: beq a2,zero,.L12 addi a7,a0,400 addi a6,a1,400 addi a0,a0,1600 addi a1,a1,1600 li a5,0 addi t6,a4,-1 .L7: beq a3,a5,.L15 beq a4,a5,.L16 beq t6,a5,.L17 vsetvli t1,zero,e8,mf4,ta,ma vle8.v v1,0(a0) vse8.v v1,0(a1) .L4: addi a5,a5,1 addi a7,a7,4 addi a6,a6,4 addi a0,a0,4 addi a1,a1,4 bne a2,a5,.L7 .L12: ret .L15: vsetvli t3,zero,e8,mf8,ta,ma vle8.v v1,0(a7) vse8.v v1,0(a6) j .L4 .L17: addi t5,a0,-400 addi t4,a1,-400 vsetvli t1,zero,e8,mf4,ta,ma vle16.v v1,0(t5) vse16.v v1,0(t4) j .L4 .L16: addi t5,a0,-800 addi t4,a1,-800 vsetvli t3,zero,e32,mf2,ta,ma vle32.v v1,0(t5) vse32.v v1,0(t4) j .L4 Tested on both RV32/RV64 no regression. Ok for trunk ? PR target/113696 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Suppress vsetvl fusion. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr113696.c: New test.
2024-02-16RISC-V: Fix *sge<u>_<X:mode><GPR:mode> patternKito Cheng1-1/+1
*sge<u>_<X:mode><GPR:mode> pattern has referenced operand[2] which is invalid...it should just use `slti<u>` rather than `slti%i2<u>`. gcc/ChangeLog: PR target/106543 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm pattern.
2024-02-16RISC-V: Add new option -march=help to print all supported extensionsKito Cheng4-2/+26
The output of -march=help is like below: ``` All available -march extensions for RISC-V: Name Version i 2.0, 2.1 e 2.0 m 2.0 a 2.0, 2.1 f 2.0, 2.2 d 2.0, 2.2 ... ``` Also support -print-supported-extensions and --print-supported-extensions for clang compatibility. gcc/ChangeLog: PR target/109349 * common/config/riscv/riscv-common.cc (riscv_arch_help): New. * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New. (RISCV_MINOR_VERSION_BASE): Ditto. (RISCV_REVISION_VERSION_BASE): Ditto. * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum rather than magic number. * config/riscv/riscv.h (riscv_arch_help): New. (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help. (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and --print-supported-extensions. * config/riscv/riscv.opt (march=help): New. (print-supported-extensions): New. (-print-supported-extensions): New. * doc/invoke.texi (RISC-V Options): Document -march=help. Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-02-13Re: [PATCH] RISC-V: Fix macro fusion for auipc+add, when identifying ↵Monk Chiang1-1/+1
UNSPEC_AUIPC. [PR113742] gcc/ChangeLog: PR target/113742 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr113742.c: New test.
2024-02-12RISC-V: Fix misspelled term args in error_at messagePan Li1-1/+2
When build with "-Werror=format-diag", there will be one misspelled term args as below. This patch would like fix it by taking the term arguments instead. ../../gcc/config/riscv/riscv-vector-builtins.cc: In function 'tree_node* riscv_vector::resolve_overloaded_builtin(location_t, unsigned int, tree, vec<tree_node*, va_gc>*)': ../../gcc/config/riscv/riscv-vector-builtins.cc:4633:65: error: misspelled term 'args' in format; use 'arguments' instead [-Werror=format-diag] 4633 | error_at (loc, "no matching function call to %qE with empty args", fndecl); gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Replace args to arguments for misspelled term. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr113766-1.c: Adjust the test cases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-02-08RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checkerPan Li1-4/+13
There is another corn case when similar as below example: void test (void) { __riscv_vaadd (); } We report error when overloaded function with empty args. For example: test.c: In function 'foo': test.c:8:3: error: no matching function call to '__riscv_vaadd' with empty args 8 | __riscv_vaadd (); | ^~~~~~~~~~~~~~~~~~~~ Unfortunately, it will meet another ICE similar to below after above message. The underlying build function checker will have zero args and break some assumption of the function checker. For example, the count of args is not less than 2. ice.c: In function ‘foo’: ice.c:8:3: internal compiler error: in require_immediate, at config/riscv/riscv-vector-builtins.cc:4252 8 | __riscv_vaadd (); | ^~~~~~~~~~~~~ 0x20b36ac riscv_vector::function_checker::require_immediate(unsigned int, long, long) const .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4252 0x20b890c riscv_vector::alu_def::check(riscv_vector::function_checker&) const .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins-shapes.cc:387 0x20b38d7 riscv_vector::function_checker::check() .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4315 0x20b4876 riscv_vector::check_builtin_call(unsigned int, vec<unsigned int, va_heap, vl_ptr>, .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4605 0x2069393 riscv_check_builtin_call .../__RISC-V_BUILD__/../gcc/config/riscv/riscv-c.cc:227 Below test are passed for this patch. * The riscv regression tests. PR target/113766 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make sure the c.arg_num is >= 2 before checking. (struct build_frm_base): Ditto. (struct narrow_alu_def): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr113766-1.c: Add new cases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-02-07RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty argsPan Li3-6/+22
There is one corn case when similar as below example: void test (void) { __riscv_vfredosum_tu (); } It will meet ICE because of the implement details of overloaded function in gcc. According to the rvv intrinisc doc, we have no such overloaded function with empty args. Unfortunately, we register the empty args function as overloaded for avoiding conflict. Thus, there will be actual one register function after return NULL_TREE back to the middle-end, and finally result in ICE when expanding. For example: 1. First we registered void __riscv_vfredmax () as the overloaded function. 2. Then resolve_overloaded_builtin (this func) return NULL_TREE. 3. The functions register in step 1 bypass the args check as empty args. 4. Finally, fall into expand_builtin with empty args and meet ICE. Here we report error when overloaded function with empty args. For example: test.c: In function 'foo': test.c:8:3: error: no matching function call to '__riscv_vfredosum_tu' with empty args 8 | __riscv_vfredosum_tu(); | ^~~~~~~~~~~~~~~~~~~~ Below test are passed for this patch. * The riscv regression tests. PR target/113766 gcc/ChangeLog: * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust the signature of func. * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto. * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make overloaded func with empty args error. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr113766-1.c: New test. * gcc.target/riscv/rvv/base/pr113766-2.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-02-06RISC-V: Fix infinite compilation of VSETVL PASSJuzhe-Zhong1-5/+4
This patch fixes issue reported by Jeff. Testing is running. Ok for trunk if I passed the testing with no regression ? gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation. (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
2024-02-06riscv: Fix compiler warning in thead.ccChristoph Müllner1-1/+2
A recent commit introduced a compiler warning in thead.cc: error: invalid suffix on literal; C++11 requires a space between literal and string macro [-Werror=literal-suffix] 1144 | fprintf (file, "(%s),"HOST_WIDE_INT_PRINT_DEC",%u", reg_names[REGNO (addr.reg)], | ^ This commit addresses this issue and breaks the line such that it won't exceed 80 characters. gcc/ChangeLog: * config/riscv/thead.cc (th_print_operand_address): Fix compiler warning. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-02-04RISC-V: Add sifive-p450, sifive-p67 to -mcpuMonk Chiang1-0/+9
gcc/ChangeLog: * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670. * doc/invoke.texi (RISC-V Options): Add sifive-p450, sifive-p670. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-sifive-p450.c: New test. * gcc.target/riscv/mcpu-sifive-p670.c: New test.
2024-02-04RISC-V: Support scheduling for sifive p400 seriesMonk Chiang6-1/+196
Add sifive p400 series scheduler module. For more information see https://www.sifive.com/cores/performance-p450-470. gcc/ChangeLog: * config/riscv/riscv.md: Include sifive-p400.md. * config/riscv/sifive-p400.md: New file. * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add sifive_p400. * config/riscv/riscv.cc (sifive_p400_tune_info): New. * config/riscv/riscv.h (TARGET_SFB_ALU): Update. * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
2024-02-04[committed] Reasonably handle SUBREGs in risc-v cost modelingJeff Law1-7/+11
This patch adjusts the costs so that we treat REG and SUBREG expressions the same for costing. This was motivated by bt_skip_func and bt_find_func in xz and results in nearly a 5% improvement in the dynamic instruction count for input #2 and smaller, but definitely visible improvements pretty much across the board. Exceptions would be perlbench input #1 and exchange2 which showed very small regressions. In the bt_find_func and bt_skip_func cases we have something like this: > (insn 10 7 11 2 (set (reg/v:DI 136 [ x ]) > (zero_extend:DI (subreg/s/u:SI (reg/v:DI 137 [ a ]) 0))) "zz.c":6:21 387 {*zero_extendsidi2_bitmanip} > (nil)) > (insn 11 10 12 2 (set (reg:DI 142 [ _1 ]) > (plus:DI (reg/v:DI 136 [ x ]) > (reg/v:DI 139 [ b ]))) "zz.c":7:23 5 {adddi3} > (nil)) [ ... ]> (insn 13 12 14 2 (set (reg:DI 143 [ _2 ]) > (plus:DI (reg/v:DI 136 [ x ]) > (reg/v:DI 141 [ c ]))) "zz.c":8:23 5 {adddi3} > (nil)) Note the two uses of (reg 136). The best way to handle that in combine might be a 3->2 split. But there's a much better approach if we look at fwprop... (set (reg:DI 142 [ _1 ]) (plus:DI (zero_extend:DI (subreg/s/u:SI (reg/v:DI 137 [ a ]) 0)) (reg/v:DI 139 [ b ]))) change not profitable (cost 4 -> cost 8) So that should be the same cost as a regular DImode addition when the ZBA extension is enabled. But it ends up costing more because the clause to cost this variant isn't prepared to handle a SUBREG. That results in the RTL above having too high a cost and fwprop gives up. One approach would be to replace the REG_P with REG_P || SUBREG_P in the costing code. I ultimately decided against that and instead check if the operand in question passes register_operand. By far the most important case to handle is the DImode PLUS. But for the sake of consistency, I changed the other instances in riscv_rtx_costs as well. For those other cases we're talking about improvements in the .000001% range. While we are into stage4, this just hits cost modeling which we've generally agreed is still appropriate (though we were mostly talking about vector). So I'm going to extend that general agreement ever so slightly and include scalar cost modeling :-) gcc/ * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG similarly. gcc/testsuite/ * gcc.target/riscv/reg_subreg_costs.c: New test. Co-authored-by: Jivan Hakobyan <jivanhakobyan9@gmail.com>
2024-02-03RISC-V: Expand VLMAX scalar move in reductionJuzhe-Zhong1-5/+7
This patch fixes the following: vsetvli a5,a1,e32,m1,tu,ma slli a4,a5,2 sub a1,a1,a5 vle32.v v2,0(a0) add a0,a0,a4 vadd.vv v1,v2,v1 bne a1,zero,.L3 vsetivli zero,1,e32,m1,ta,ma vmv.s.x v2,zero vsetvli a5,zero,e32,m1,ta,ma ---> Redundant vsetvl. vredsum.vs v1,v1,v2 vmv.x.s a0,v1 ret VSETVL PASS is able to fuse avl = 1 of scalar move and VLMAX avl of reduction. However, this following RTL blocks the fusion in dependence analysis in VSETVL PASS: (insn 49 24 50 5 (set (reg:RVVM1SI 98 v2 [148]) (if_then_else:RVVM1SI (unspec:RVVMF32BI [ (const_vector:RVVMF32BI [ (const_int 1 [0x1]) repeat [ (const_int 0 [0]) ] ]) (const_int 1 [0x1]) (const_int 2 [0x2]) repeated x2 (const_int 0 [0]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (const_vector:RVVM1SI repeat [ (const_int 0 [0]) ]) (unspec:RVVM1SI [ (reg:DI 0 zero) ] UNSPEC_VUNDEF))) 3813 {*pred_broadcastrvvm1si_zero} (nil)) (insn 50 49 51 5 (set (reg:DI 15 a5 [151]) ----> It set a5, blocks the following VLMAX into the scalar move above. (unspec:DI [ (const_int 32 [0x20]) ] UNSPEC_VLMAX)) 2566 {vlmax_avldi} (expr_list:REG_EQUIV (unspec:DI [ (const_int 32 [0x20]) ] UNSPEC_VLMAX) (nil))) (insn 51 50 52 5 (set (reg:RVVM1SI 97 v1 [150]) (unspec:RVVM1SI [ (unspec:RVVMF32BI [ (const_vector:RVVMF32BI repeat [ (const_int 1 [0x1]) ]) (reg:DI 15 a5 [151]) (const_int 2 [0x2]) (const_int 1 [0x1]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (unspec:RVVM1SI [ (reg:RVVM1SI 97 v1 [orig:134 vect_result_14.6 ] [134]) (reg:RVVM1SI 98 v2 [148]) ] UNSPEC_REDUC_SUM) (unspec:RVVM1SI [ (reg:DI 0 zero) ] UNSPEC_VUNDEF) ] UNSPEC_REDUC)) 17541 {pred_redsumrvvm1si} (expr_list:REG_DEAD (reg:RVVM1SI 98 v2 [148]) (expr_list:REG_DEAD (reg:SI 66 vl) (expr_list:REG_DEAD (reg:DI 15 a5 [151]) (expr_list:REG_DEAD (reg:DI 0 zero) (nil)))))) Such situation can only happen on auto-vectorization, never happen on intrinsic codes. Since the reduction is passed VLMAX AVL, it should be more natural to pass VLMAX to the scalar move which initial the value of the reduction. After this patch: vsetvli a5,a1,e32,m1,tu,ma slli a4,a5,2 sub a1,a1,a5 vle32.v v2,0(a0) add a0,a0,a4 vadd.vv v1,v2,v1 bne a1,zero,.L3 vsetvli a5,zero,e32,m1,ta,ma vmv.s.x v2,zero vredsum.vs v1,v1,v2 vmv.x.s a0,v1 ret Tested on both RV32/RV64 no regression. PR target/113697 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr113697.c: New test.
2024-02-02Revert "RISC-V: Allow LICM hoist POLY_INT configuration code sequence"Lehua Ding1-5/+4
This reverts commit 74489c19070703361acc20bc172f304cae845a96.
2024-02-02RISC-V: Allow LICM hoist POLY_INT configuration code sequenceJuzhe-Zhong1-4/+5
Realize in recent benchmark evaluation (coremark-pro zip-test): vid.v v2 vmv.v.i v5,0 .L9: vle16.v v3,0(a4) vrsub.vx v4,v2,a6 ---> LICM failed to hoist it outside the loop. The root cause is: (insn 56 47 57 4 (set (subreg:DI (reg:HI 220) 0) (reg:DI 223)) "rvv.c":11:9 208 {*movdi_64bit} -> Its result used by the following vrsub.vx then supress the hoist of the vrsub.vx (nil)) (insn 57 56 59 4 (set (reg:RVVMF2HI 216) (if_then_else:RVVMF2HI (unspec:RVVMF32BI [ (const_vector:RVVMF32BI repeat [ (const_int 1 [0x1]) ]) (reg:DI 350) (const_int 2 [0x2]) repeated x2 (const_int 1 [0x1]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (minus:RVVMF2HI (vec_duplicate:RVVMF2HI (reg:HI 220)) (reg:RVVMF2HI 217)) (unspec:RVVMF2HI [ (reg:DI 0 zero) ] UNSPEC_VUNDEF))) "rvv.c":11:9 6938 {pred_subrvvmf2hi_reverse_scalar} (expr_list:REG_DEAD (reg:HI 220) (nil))) This patch fixes it generate (set (reg:HI) (subreg:HI (reg:DI))) instead of (set (subreg:DI (reg:DI)) (reg:DI)). After this patch: vid.v v2 vrsub.vx v2,v2,a7 vmv.v.i v4,0 .L3: vle16.v v3,0(a4) Tested on both RV32 and RV64 no regression. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/poly_licm-1.c: New test. * gcc.target/riscv/rvv/autovec/poly_licm-2.c: New test.
2024-02-02RISC-V: Cleanup the comments for the psabiPan Li1-12/+9
This patch would like to cleanup some comments which are out of date or incorrect. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments. (riscv_pass_by_reference): Ditto. (riscv_fntype_abi): Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-02-02RISC-V: Remove vsetvl_pre bogus instructions in VSETVL PASSJuzhe-Zhong1-0/+64
I realize there is a RTL regression between GCC-14 and GCC-13. https://godbolt.org/z/Ga7K6MqaT GCC-14: (insn 9 13 31 2 (set (reg:DI 15 a5 [138]) (unspec:DI [ (const_int 64 [0x40]) ] UNSPEC_VLMAX)) "/app/example.c":5:15 2566 {vlmax_avldi} (expr_list:REG_EQUIV (unspec:DI [ (const_int 64 [0x40]) ] UNSPEC_VLMAX) (nil))) (insn 31 9 10 2 (parallel [ (set (reg:DI 15 a5 [138]) (unspec:DI [ (reg:DI 0 zero) (const_int 32 [0x20]) (const_int 7 [0x7]) (const_int 1 [0x1]) repeated x2 ] UNSPEC_VSETVL)) (set (reg:SI 66 vl) (unspec:SI [ (reg:DI 0 zero) (const_int 32 [0x20]) (const_int 7 [0x7]) ] UNSPEC_VSETVL)) (set (reg:SI 67 vtype) (unspec:SI [ (const_int 32 [0x20]) (const_int 7 [0x7]) (const_int 1 [0x1]) repeated x2 ] UNSPEC_VSETVL)) ]) "/app/example.c":5:15 3281 {vsetvldi} (nil)) GCC-13: (insn 10 7 26 2 (set (reg/f:DI 11 a1 [139]) (plus:DI (reg:DI 11 a1 [142]) (const_int 800 [0x320]))) "/app/example.c":6:32 5 {adddi3} (nil)) (insn 26 10 9 2 (parallel [ (set (reg:DI 15 a5) (unspec:DI [ (reg:DI 0 zero) (const_int 32 [0x20]) (const_int 7 [0x7]) (const_int 1 [0x1]) repeated x2 ] UNSPEC_VSETVL)) (set (reg:SI 66 vl) (unspec:SI [ (reg:DI 0 zero) (const_int 32 [0x20]) (const_int 7 [0x7]) ] UNSPEC_VSETVL)) (set (reg:SI 67 vtype) (unspec:SI [ (const_int 32 [0x20]) (const_int 7 [0x7]) (const_int 1 [0x1]) repeated x2 ] UNSPEC_VSETVL)) ]) "/app/example.c":5:15 792 {vsetvldi} (nil)) GCC-13 doesn't have: (insn 9 13 31 2 (set (reg:DI 15 a5 [138]) (unspec:DI [ (const_int 64 [0x40]) ] UNSPEC_VLMAX)) "/app/example.c":5:15 2566 {vlmax_avldi} (expr_list:REG_EQUIV (unspec:DI [ (const_int 64 [0x40]) ] UNSPEC_VLMAX) (nil))) vsetvl_pre doesn't emit any assembler which is just used for occupying scalar register. It should be removed in VSETVL PASS. Tested on both RV32 and RV64 no regression. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function. (pre_vsetvl::cleaup): Remove vsetvl_pre. (pre_vsetvl::remove_vsetvl_pre_insns): New function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: New test.
2024-02-01RISC-V: Support scheduling for sifive p600 seriesMonk Chiang9-12/+214
Add sifive p600 series scheduler module. For more information see https://www.sifive.com/cores/performance-p650-670. Add sifive-p650, sifive-p670 for mcpu option will come in separate patches. gcc/ChangeLog: * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type attribute, and include sifive-p600.md. * config/riscv/generic-ooo.md: Update type attribute. * config/riscv/generic.md: Update type attribute. * config/riscv/sifive-7.md: Update type attribute. * config/riscv/sifive-p600.md: New file. * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add sifive_p600. * config/riscv/riscv.cc (sifive_p600_tune_info): New. * config/riscv/riscv.h (TARGET_SFB_ALU): Update. * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
2024-02-01RISC-V: Add minimal support for 7 new unprivileged extensionsMonk Chiang1-0/+14
The RISC-V Profiles specification here: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions These extensions don't add any new features but describe existing features. So this patch only adds parsing. Za64rs: Reservation set size of 64 bytes Za128rs: Reservation set size of 128 bytes Ziccif: Main memory supports instruction fetch with atomicity requirement Ziccrse: Main memory supports forward progress on LR/SC sequences Ziccamoa: Main memory supports all atomics in A Zicclsm: Main memory supports misaligned loads/stores Zic64b: Cache block size isf 64 bytes gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items. * config/riscv/riscv.opt: New macro for 7 new unprivileged extensions. * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions. gcc/testsuite/ChangeLog: * gcc.target/riscv/za-ext.c: New test. * gcc.target/riscv/zi-ext.c: New test.
2024-01-31Revert "RISC-V: Add non-vector types to dfa pipelines"Edwin Lu6-102/+66
This reverts commit 26c34b809cd1a6249027730a8b52bbf6a1c0f4a8.
2024-01-31Revert "RISC-V: Add vector related pipelines"Edwin Lu3-145/+126
This reverts commit e56fb037d9d265682f5e7217d8a4c12a8d3fddf8.
2024-01-31Revert "RISC-V: Enable assert for insn_has_dfa_reservation"Edwin Lu1-0/+2
This reverts commit 23cd2961bd2ff63583f46e3499a07bd54491d45c.
2024-01-31RISC-V: Enable assert for insn_has_dfa_reservationEdwin Lu1-2/+0
Enables assert that every typed instruction is associated with a dfa reservation gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2024-01-31RISC-V: Add vector related pipelinesEdwin Lu3-126/+145
Creates new generic vector pipeline file common to all cpu tunes. Moves all vector related pipelines from generic-ooo to generic-vector-ooo. Creates new vector crypto related insn reservations. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo): Move reservation (generic_ooo_vec_load): ditto (generic_ooo_vec_store): ditto (generic_ooo_vec_loadstore_seg): ditto (generic_ooo_vec_alu): ditto (generic_ooo_vec_fcmp): ditto (generic_ooo_vec_imul): ditto (generic_ooo_vec_fadd): ditto (generic_ooo_vec_fmul): ditto (generic_ooo_crypto): ditto (generic_ooo_perm): ditto (generic_ooo_vec_reduction): ditto (generic_ooo_vec_ordered_reduction): ditto (generic_ooo_vec_idiv): ditto (generic_ooo_vec_float_divsqrt): ditto (generic_ooo_vec_mask): ditto (generic_ooo_vec_vesetvl): ditto (generic_ooo_vec_setrm): ditto (generic_ooo_vec_readlen): ditto * config/riscv/riscv.md: include generic-vector-ooo * config/riscv/generic-vector-ooo.md: New file. to here Signed-off-by: Edwin Lu <ewlu@rivosinc.com> Co-authored-by: Robin Dapp <rdapp.gcc@gmail.com>
2024-01-31RISC-V: Add non-vector types to dfa pipelinesEdwin Lu6-66/+102
This patch adds non-vector related insn reservations and updates/creates new insn reservations so all non-vector typed instructions have a reservation. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation (generic_ooo_branch): ditto * config/riscv/generic.md (generic_sfb_alu): ditto (generic_fmul_half): ditto * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation (sifive_7_popcount): ditto * config/riscv/vector.md: change rdfrm to fmove * config/riscv/zc.md: change pushpop to load/store Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-01-31RISC-V: Fix VSETLV PASS compile-time issueJuzhe-Zhong1-124/+60
The compile time issue was discovered in SPEC 2017 wrf: Use time and -ftime-report to analyze the profile data of SPEC 2017 wrf compilation . Before this patch (Lazy vsetvl): scheduling : 121.89 ( 15%) 0.53 ( 11%) 122.72 ( 15%) 13M ( 1%) machine dep reorg : 424.61 ( 53%) 1.84 ( 37%) 427.44 ( 53%) 5290k ( 0%) real 13m27.074s user 13m19.539s sys 0m5.180s Simple vsetvl: machine dep reorg : 0.10 ( 0%) 0.00 ( 0%) 0.11 ( 0%) 4138k ( 0%) real 6m5.780s user 6m2.396s sys 0m2.373s The machine dep reorg is the compile time of VSETVL PASS (424 seconds) which counts 53% of the compilation time, spends much more time than scheduling. After investigation, the critical patch of VSETVL pass is compute_lcm_local_properties which is called every iteration of phase 2 (earliest fusion) and phase 3 (global lcm). This patch optimized the codes of compute_lcm_local_properties to reduce the compilation time. After this patch: scheduling : 117.51 ( 27%) 0.21 ( 6%) 118.04 ( 27%) 13M ( 1%) machine dep reorg : 80.13 ( 18%) 0.91 ( 26%) 81.26 ( 18%) 5290k ( 0%) real 7m25.374s user 7m20.116s sys 0m3.795s The optimization of this patch is very obvious, lazy VSETVL PASS: 424s (53%) -> 80s (18%) which spend less time than scheduling. Tested on both RV32 and RV64 no regression. Ok for trunk ? PR target/113495 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove. (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue. (pre_vsetvl::compute_transparent): New function. (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
2024-01-30RISC-V: Bugfix for vls mode aggregated in GPR calling conventionPan Li1-0/+78
According to the issue as below. https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/416 When the mode size of vls integer mode is less than 2 * XLEN, we will take the gpr for both the args and the return values. Instead of the reference. For example the below code: typedef short v8hi __attribute__ ((vector_size (16))); v8hi __attribute__((noinline)) add (v8hi a, v8hi b) { v8hi r = a + b; return r; } Before this patch: add: vsetivli zero,8,e16,m1,ta,ma vle16.v v1,0(a1) <== arg by reference vle16.v v2,0(a2) <== arg by reference vadd.vv v1,v1,v2 vse16.v v1,0(a0) <== return by reference ret After this patch: add: addi sp,sp,-32 sd a0,0(sp) <== arg by register a0 - a3 sd a1,8(sp) sd a2,16(sp) sd a3,24(sp) addi a5,sp,16 vsetivli zero,8,e16,m1,ta,ma vle16.v v2,0(sp) vle16.v v1,0(a5) vadd.vv v1,v1,v2 vse16.v v1,0(sp) ld a0,0(sp) <== return by a0 - a1. ld a1,8(sp) addi sp,sp,32 jr ra For vls floating point, we take the same rules as integer and passed by the gpr or reference. The riscv regression passed for this patch. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to calculate the gpr count required by vls mode. (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode. (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr for vls mode. (riscv_get_arg_info): Add vls mode handling. (riscv_pass_by_reference): Return false if arg info has no zero gpr count. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add new helper macro. * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-01-30riscv: Move UNSPEC_XTHEAD* from unspecv to unspecChristoph Müllner1-4/+4
The UNSPEC_XTHEAD* macros ended up in the unspecv enum, which broke gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c. The INSNs expect these unspecs to be not volatile. Further, there is not reason to have them defined volatile. So let's simply move the macros into the unspec enum. With this patch we have again 0 fails in riscv.exp. gcc/ChangeLog: * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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