| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-12-23 | RISC-V: Fix vle constraints | Ju-Zhe Zhong | 1 | -8/+8 |
| 2022-12-23 | RISC-V: Remove side effects of vsetvl pattern in RTL. | Ju-Zhe Zhong | 1 | -0/+26 |
| 2022-12-19 | RISC-V: Remove unit-stride store from ta attribute | Ju-Zhe Zhong | 1 | -1/+1 |
| 2022-12-19 | RISC-V: Support VSETVL PASS for RVV support | Ju-Zhe Zhong | 1 | -27/+104 |
| 2022-12-02 | RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst | Ju-Zhe Zhong | 1 | -2/+0 |
| 2022-12-02 | RISC-V: Add attributes for VSETVL PASS | Ju-Zhe Zhong | 1 | -0/+185 |
| 2022-12-02 | RISC-V: Add duplicate vector support. | Ju-Zhe Zhong | 1 | -1/+52 |
| 2022-11-11 | RISC-V: Add RVV registers register spilling | Ju-Zhe Zhong | 1 | -33/+103 |
| 2022-10-26 | RISC-V: Support load/store in mov<mode> pattern for RVV modes. | Ju-Zhe Zhong | 1 | -6/+273 |
| 2022-10-21 | RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. | Ju-Zhe Zhong | 1 | -0/+72 |
 |
index : riscv-gnu-toolchain/gcc.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |