riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-12-02	RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions.	yulong	1	-1/+29
2024-11-29	RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.	yulong	1	-0/+32
2024-11-20	PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition...	Feng Wang	1	-1/+1
2024-11-18	RISC-V: Add VLS modes to strided loads.	Robin Dapp	1	-0/+243
2024-09-24	RISC-V: Add more vector-vector extract cases.	Robin Dapp	1	-0/+184
2024-08-29	RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].	Robin Dapp	1	-0/+202
2024-08-13	RISC-V: Fix non-obvious comment typos	Patrick O'Neill	1	-1/+1
2024-08-06	RISC-V: Fix comment typos	Patrick O'Neill	1	-1/+1
2024-07-15	RISC-V: Add md files for vector BFloat16	Feng Wang	1	-2/+167
2024-06-14	RISC-V: Bugfix vec_extract v mode iterator restriction mismatch	Pan Li	1	-1/+3
2024-06-13	RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch	Pan Li	1	-0/+4
2024-05-16	RISC-V: Implement vectorizable early exit with vcond_mask_len	Pan Li	1	-0/+1
2024-03-22	RISC-V: Don't add fractional LMUL types to V_VLS for XTheadVector	Christoph Müllner	1	-6/+13
2024-01-10	RISC-V: Refine unsigned avg_floor/avg_ceil	Juzhe-Zhong	1	-5/+0
2024-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2024-01-02	RISC-V: Add crypto machine descriptions	Feng Wang	1	-0/+36
2023-12-08	RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE	Pan Li	1	-1/+1
2023-11-27	RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p	Juzhe-Zhong	1	-6/+17
2023-11-22	RISC-V: Fix permutation indice mode bug	Juzhe-Zhong	1	-7/+7
2023-11-20	RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32	Juzhe-Zhong	1	-28/+0
2023-11-20	RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.	Robin Dapp	1	-32/+157
2023-11-18	RISC-V: Refactor RVV iterators[NFC]	Juzhe-Zhong	1	-507/+94
2023-11-13	RISC-V: Support FP l/ll round and rint HF mode autovec	Pan Li	1	-2/+80
2023-11-04	RISC-V: Remove HF modes of FP to INT rounding autovec	Pan Li	1	-57/+2
2023-11-03	RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator	Pan Li	1	-18/+181
2023-11-03	Revert "RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator"	Pan Li	1	-181/+18
2023-11-02	RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator	Pan Li	1	-18/+181
2023-10-31	RISC-V: Add vector fmin/fmax expanders.	Robin Dapp	1	-0/+8
2023-10-21	RISC-V: Support partial VLS mode when preference fixed-vlmax [PR111857]	Pan Li	1	-921/+922
2023-10-15	RISC-V: Fix vsingle attribute	Juzhe-Zhong	1	-1/+1
2023-10-14	RISC-V: Remove redundant iterators.	Juzhe-Zhong	1	-110/+0
2023-10-12	RISC-V: Support FP irintf auto vectorization	Pan Li	1	-37/+37
2023-10-11	RISC-V: Support FP lrint/lrintf auto vectorization	Pan Li	1	-0/+69
2023-09-28	RISC-V: Support {U}INT64 to FP16 auto-vectorization	Pan Li	1	-0/+38
2023-09-24	RISC-V: Support full coverage VLS combine support	Juzhe-Zhong	1	-0/+287
2023-09-22	RISC-V: Add VLS widen binary combine patterns	Juzhe-Zhong	1	-0/+44
2023-09-21	RISC-V: Support VLS mult high	Juzhe-Zhong	1	-0/+47
2023-09-21	RISC-V: Optimized for strided load/store with stride == element width[PR111450]	xuli	1	-0/+87
2023-09-21	RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names	Lehua Ding	1	-8/+8
2023-09-21	RISC-V: Support VLS INT <-> FP conversions	Juzhe-Zhong	1	-0/+202
2023-09-20	RISC-V: Support VLS floating-point extend/truncate	Juzhe-Zhong	1	-0/+95
2023-09-20	RISC-V: Extend VLS modes in 'VWEXTI' iterator	Juzhe-Zhong	1	-0/+201
2023-09-18	RISC-V: Support VLS reduction	Juzhe-Zhong	1	-0/+80
2023-09-15	RISC-V: Support combine extend and reduce sum to widen reduce sum	Lehua Ding	1	-0/+51
2023-09-14	RISC-V: Refactor vector reduction patterns	Lehua Ding	1	-11/+51
2023-09-14	RISC-V: Cleanup redundant reduction patterns after refactor vector mode	Lehua Ding	1	-19/+28
2023-09-13	RISC-V: Support cond vmulh.vv and vmulu.vv autovec patterns	Lehua Ding	1	-0/+4
2023-09-11	RISC-V: Add VLS modes VEC_PERM support[PR111311]	Juzhe-Zhong	1	-15/+274
2023-09-11	RISC-V: Add missing VLS mask bool mode reg -> reg patterns	Juzhe-Zhong	1	-0/+15
2023-09-09	RISC-V: Fix VLS floating-point operations predicate	Juzhe-Zhong	1	-12/+12