Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2023-01-02 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
2022-12-02 | RISC-V: Add duplicate vector support. | Ju-Zhe Zhong | 1 | -0/+9 |
2022-11-11 | RISC-V: Add RVV registers register spilling | Ju-Zhe Zhong | 1 | -0/+23 |
2022-10-26 | RISC-V: Support load/store in mov<mode> pattern for RVV modes. | Ju-Zhe Zhong | 1 | -0/+58 |