riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-12-13	RISC-V: Improve slide1up pattern.	Robin Dapp	1	-1/+17
2024-12-06	diagnostics: UX: add doc URLs for attributes (v2)	David Malcolm	1	-0/+3
2024-12-04	sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729]	Vineet Gupta	1	-0/+4
2024-12-02	riscv: Avoid narrowing warning	Andreas Schwab	1	-25/+39
2024-11-29	[PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC.	Mariam Arutunian	1	-0/+157
2024-11-25	RISC-V: Use dynamic shadow offset	Kito Cheng	1	-4/+14
2024-11-22	build: Remove INCLUDE_MEMORY [PR117737]	Andrew Pinski	1	-1/+0
2024-11-22	[RISC-V][PR target/109279] Improve RISC-V constant synthesis	Jeff Law	1	-0/+28
2024-11-21	[RISC-V][PR target/117690] Add missing shift in constant synthesis	Jeff Law	1	-4/+8
2024-11-19	RISC-V: Tie MUL and DIV masks to the M extension	Dimitar Dimitrov	1	-1/+5
2024-11-18	[committed][RISC-V][PR target/117595] Fix bogus use of simplify_gen_subreg	Jeff Law	1	-1/+1
2024-11-13	RISC-V: Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY and TARGET_GET_FUNC...	Yangyu Chen	1	-0/+587
2024-11-13	RISC-V: Implement TARGET_MANGLE_DECL_ASSEMBLER_NAME	Yangyu Chen	1	-0/+39
2024-11-13	RISC-V: Implement TARGET_COMPARE_VERSION_PRIORITY and TARGET_OPTION_FUNCTION_...	Yangyu Chen	1	-0/+127
2024-11-13	RISC-V: Implement TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P	Yangyu Chen	1	-0/+4
2024-11-12	[RISC-V] Fix costing of LO_SUM expressions	Xianmiao Qu	1	-1/+2
2024-11-12	RISC-V: Add norelax function attribute	yulong	1	-16/+28
2024-11-04	[PATCH v2 2/2] RISC-V: Disable by pieces for vector setmem length > UNITS_PER...	Craig Blackmore	1	-0/+19
2024-10-31	RISC-V: Do not inline when callee is versioned but caller is not	Yangyu Chen	1	-0/+4
2024-10-30	[RISC-V] Aggressively hoist VXRM assignments	Jeff Law	1	-0/+69
2024-10-28	[target/117316] Fix initializer for riscv code alignment handling	Jeff Law	1	-3/+27
2024-10-23	[PATCH] RISC-V: override alignment of function/jump/loop	Wang Pengcheng	1	-0/+15
2024-10-20	Revert "[PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNIT...	Jeff Law	1	-19/+0
2024-10-19	[PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD	Craig Blackmore	1	-0/+19
2024-10-16	Ternary operator formatting fixes	Jakub Jelinek	1	-2/+2
2024-10-08	RISC-V: Implement TARGET_CAN_INLINE_P	Yangyu Chen	1	-0/+66
2024-10-08	RISC-V: Implement scalar SAT_TRUNC for signed integer	Pan Li	1	-0/+61
2024-09-30	RISC-V: Implement scalar SAT_SUB for signed integer	Pan Li	1	-0/+69
2024-09-18	[PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expre...	Xianmiao Qu	1	-1/+1
2024-09-16	riscv: Fix duplicate assmbler label in @tlsdesc<mode> insn	Andreas Schwab	1	-3/+1
2024-09-05	[PATCH 2/2 v2] RISC-V: Constant synthesis of inverted halves	Raphael Moreira Zinsly	1	-0/+30
2024-09-05	[PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements	Raphael Moreira Zinsly	1	-6/+132
2024-09-05	[V2][RISC-V] Avoid unnecessary extensions after sCC insns	Jeff Law	1	-5/+41
2024-09-04	[PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants	Raphael Moreira Zinsly	1	-8/+21
2024-09-04	RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD	Pan Li	1	-1/+1
2024-09-03	RISC-V: Support form 1 of integer scalar .SAT_ADD	Pan Li	1	-0/+90
2024-09-01	[PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.	Xianmiao Qu	1	-0/+5
2024-09-02	RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64	Pan Li	1	-53/+46
2024-08-29	Use std::unique_ptr for optinfo_item	David Malcolm	1	-0/+1
2024-08-29	RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].	Robin Dapp	1	-0/+11
2024-08-27	RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander	Patrick O'Neill	1	-5/+3
2024-08-27	RISC-V: Emit costs for bool and stepped const vectors	Patrick O'Neill	1	-0/+42
2024-08-27	RISC-V: Reorder insn cost match order to match corresponding expander match o...	Patrick O'Neill	1	-9/+9
2024-08-27	RISC-V: Support IMM for operand 1 of ussub pattern	Pan Li	1	-1/+1
2024-08-26	RISC-V: Support IMM for operand 0 of ussub pattern	Pan Li	1	-1/+45
2024-08-22	RISC-V: Fix vector cfi notes for stack-clash protection	Raphael Moreira Zinsly	1	-2/+16
2024-08-18	RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]	Pan Li	1	-12/+22
2024-08-17	[RISC-V][PR target/116282] Stabilize pattern conditions	Jeff Law	1	-21/+45
2024-08-17	RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker	Jin Ma	1	-1/+4
2024-08-17	RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]	曾治金	1	-2/+2