| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-12-23 | RISC-V: Support vle.v/vse.v intrinsics | Ju-Zhe Zhong | 1 | -4/+45 |
| 2022-12-23 | RISC-V: Remove side effects of vsetvl pattern in RTL. | Ju-Zhe Zhong | 1 | -1/+1 |
| 2022-12-23 | RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties | Ju-Zhe Zhong | 1 | -5/+0 |
| 2022-12-19 | RISC-V: Change vlmul printing rule | Ju-Zhe Zhong | 1 | -1/+1 |
| 2022-10-31 | RISC-V: Change constexpr back to CONSTEXPR | Ju-Zhe Zhong | 1 | -2/+2 |
| 2022-10-26 | RISC-V: Support load/store in mov<mode> pattern for RVV modes. | Ju-Zhe Zhong | 1 | -12/+2 |
| 2022-10-24 | RISC-V: Replace CONSTEXPR with constexpr | Ju-Zhe Zhong | 1 | -2/+2 |
| 2022-10-21 | RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. | Ju-Zhe Zhong | 1 | -0/+104 |
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index : riscv-gnu-toolchain/gcc.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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