riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-12-13	RISC-V: Improve slide1up pattern.	Robin Dapp	1	-0/+1
2024-11-29	[PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC.	Mariam Arutunian	1	-0/+3
2024-11-13	RISC-V: Implement TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P	Yangyu Chen	1	-1/+3
2024-10-31	RISC-V: Split riscv_process_target_attr with const char *args argument	Yangyu Chen	1	-0/+2
2024-10-29	RISC-V: Implement the MASK_LEN_STRIDED_LOAD{STORE}	Pan Li	1	-0/+2
2024-10-21	RISC-V: Implement vector SAT_TRUNC for signed integer	Pan Li	1	-0/+4
2024-10-19	[PATCH 4/7] RISC-V: Honour -mrvv-max-lmul in riscv_vector::expand_block_move	Craig Blackmore	1	-1/+2
2024-10-12	RISC-V: Implement vector SAT_SUB for signed integer	Pan Li	1	-0/+1
2024-10-08	RISC-V: Implement scalar SAT_TRUNC for signed integer	Pan Li	1	-0/+1
2024-09-30	RISC-V: Implement scalar SAT_SUB for signed integer	Pan Li	1	-0/+1
2024-09-18	RISC-V: Implement SAT_ADD for signed integer vector	Pan Li	1	-0/+1
2024-09-03	RISC-V: Support form 1 of integer scalar .SAT_ADD	Pan Li	1	-0/+1
2024-08-17	[RISC-V][PR target/116282] Stabilize pattern conditions	Jeff Law	1	-1/+1
2024-08-17	RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker	Jin Ma	1	-0/+1
2024-08-06	RISC-V: Fix comment typos	Patrick O'Neill	1	-2/+2
2024-07-23	RISC-V: Implement the .SAT_TRUNC for scalar	Pan Li	1	-0/+1
2024-07-08	RISC-V: Implement .SAT_TRUNC for vector unsigned int	Pan Li	1	-0/+4
2024-07-05	RISC-V: Use tu policy for first-element vec_set [PR115725].	Robin Dapp	1	-0/+4
2024-06-25	[PATCH v2 3/3] RISC-V: cmpmem for RISCV with V extension	Sergei Lewis	1	-0/+1
2024-06-24	[PATCH v2 2/3] RISC-V: setmem for RISCV with V extension	Sergei Lewis	1	-0/+1
2024-06-11	RISC-V: Implement .SAT_SUB for unsigned vector int	Pan Li	1	-0/+1
2024-06-08	RISC-V: Implement .SAT_SUB for unsigned scalar int	Pan Li	1	-0/+1
2024-05-21	RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]	Vineet Gupta	1	-0/+2
2024-05-18	RISC-V: Implement IFN SAT_ADD for both the scalar and vector	Pan Li	1	-0/+2
2024-05-17	RISC-V: Add initial cost handling for segment loads/stores.	Robin Dapp	1	-0/+9
2024-05-15	[v2,1/2] RISC-V: Add cmpmemsi expansion	Christoph Müllner	1	-0/+1
2024-05-14	RISC-V: avoid LUI based const materialization ... [part of PR/106265]	Vineet Gupta	1	-0/+1
2024-05-14	[PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero	Christoph Müllner	1	-0/+1
2024-04-30	This is almost exclusively Jivan's work. His original post:	Jivan Hakobyan	1	-0/+1
2024-04-08	RISC-V: Implement TLS Descriptors.	Tatsuyuki Ishi	1	-2/+3
2024-04-08	RISC-V: Allow RVV intrinsic for more function target	Pan Li	1	-0/+2
2024-03-07	RISC-V: Refactor expand_vec_cmp [NFC]	demin.han	1	-1/+1
2024-02-16	RISC-V: Add new option -march=help to print all supported extensions	Kito Cheng	1	-0/+7
2024-02-07	RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty args	Pan Li	1	-1/+1
2024-01-22	RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x	Juzhe-Zhong	1	-0/+1
2024-01-19	RISC-V: Fix RVV_VLMAX	Juzhe-Zhong	1	-3/+2
2024-01-18	RISC-V: Adds the prefix "th." for the instructions of XTheadVector.	Jun Sha (Joshua)	1	-0/+2
2024-01-15	RISC-V: Fix regression (GCC-14 compare with GCC-13.2) of SHA256 from coremark...	Juzhe-Zhong	1	-0/+2
2024-01-12	RISC-V: Adjust scalar_to_vec cost	Juzhe-Zhong	1	-0/+11
2024-01-10	RISC-V: T-HEAD: Add support for the XTheadInt ISA extension	Jin Ma	1	-0/+3
2024-01-10	RISC-V: Refine unsigned avg_floor/avg_ceil	Juzhe-Zhong	1	-0/+8
2024-01-06	RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move	Juzhe-Zhong	1	-0/+1
2024-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2023-12-20	RISC-V: Support -mcmodel=large.	Kuan-Lin Chen	1	-0/+1
2023-12-14	expmed: Use GET_MODE_PRECISION and expander's output mode.	Robin Dapp	1	-1/+2
2023-12-14	RISC-V: Add RVV builtin vectorization cost model	Juzhe-Zhong	1	-0/+76
2023-12-12	RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC]	Juzhe-Zhong	1	-0/+1
2023-12-08	RISC-V: Add vectorized strcmp and strncmp.	Robin Dapp	1	-0/+1
2023-12-08	RISC-V: Add vectorized strlen.	Robin Dapp	1	-1/+1
2023-12-08	RISC-V: Support interleave vector with different step sequence	Juzhe-Zhong	1	-1/+1