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path: root/gcc/config/riscv/riscv-opts.h
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2023-11-27RISC-V: Initial RV64E and LP64E supportTsukasa OI1-0/+1
2023-11-20RISC-V: Implement -mmemcpy-strategy= options[PR112537]xuli1-0/+12
2023-10-27RISC-V: Move lmul calculation into macroJuzhe-Zhong1-0/+4
2023-10-21RISC-V: Support partial VLS mode when preference fixed-vlmax [PR111857]Pan Li1-5/+0
2023-10-11RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the buildKito Cheng1-0/+6
2023-10-09RISC-V: Add initial pipeline description for an out-of-order core.Robin Dapp1-1/+2
2023-10-09RISC-V: Support movmisalign of RVV VLA modesJuzhe-Zhong1-0/+3
2023-10-01RISC-V:Optimize the MASK opt generationFeng Wang1-217/+1
2023-09-07RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' supportTsukasa OI1-0/+6
2023-09-05RISC-V: Fix Dynamic LMUL compile optionJuzhe-Zhong1-1/+1
2023-09-01RISC-V: Add dynamic LMUL compile optionJuzhe-Zhong1-1/+3
2023-08-28RISC-V: __builtin_riscv_pause for all environmentTsukasa OI1-0/+2
2023-08-25[PATCH v10] RISC-V: Add support for the Zfa extensionJin Ma1-0/+3
2023-08-14RISC-V: Minimal support for ZC* extensions.Jiawei1-0/+16
2023-08-12RISC-V: Add TAREGT_VECTOR check into VLS modesJuzhe-Zhong1-1/+2
2023-08-10RISC-V: Add Ztso atomic mappingsPatrick O'Neill1-0/+4
2023-07-27RISC-V: Enable basic VLS modes supportJuzhe-Zhong1-0/+4
2023-07-26[PATCH 1/5] [RISC-V] Recognize Zicond extensionXiao Zeng1-0/+3
2023-07-14RISC-V: Recognized zihintntl extensionsMonk Chiang1-0/+2
2023-07-04RISC-V: Add support for vector crypto extensionsChristoph Müllner1-0/+34
2023-06-01RISC-V: Introduce vfloat16m{f}*_t and their machine mode.Pan Li1-0/+4
2023-05-31RISC-V: Add ZVFH extension to the -march= optionPan Li1-0/+2
2023-05-29RISC-V: Add ZVFHMIN extension to the -march= optionPan Li1-2/+4
2023-05-17RISC-V: Add mode switching target hook to insert rounding mode config for fix...Juzhe-Zhong1-0/+8
2023-05-08RISC-V: Handle multi-lib path correclty for linuxKito Cheng1-0/+9
2023-04-25RISC-V: Add auto-vectorization compile option for RVVJu-Zhe Zhong1-0/+15
2023-03-15riscv: Add basic XThead* vendor extension supportChristoph Müllner1-0/+26
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-11-15Revert "RISC-V: Add basic support for the Ventana-VT1 core"Philipp Tomsich1-1/+1
2022-11-14RISC-V: Add basic support for the Ventana-VT1 corePhilipp Tomsich1-1/+1
2022-11-02RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+3
2022-10-27RISC-V: Minimal support of z*inx extension.Jiawei1-0/+10
2022-10-26RISC-V: Recognized Svinval and Svnapot extensionsMonk Chiang1-0/+6
2022-09-05RISC-V: Support Zmmul extensionLiaoShihua1-0/+3
2022-08-16RISC-V: Support zfh and zfhmin extensionKito Cheng1-0/+6
2022-05-24RISC-V: Add mininal support for Zicbo[mzp]ShiYulong1-0/+8
2022-03-21RISC-V: Implement misc macro for vector extensions.Kito Cheng1-4/+21
2022-01-07RISC-V: Minimal support of vector extensionsKito Cheng1-0/+31
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-04RISC-V: Add option defines for Scalar CryptographySiYu Wu1-0/+22
2021-10-25RISC-V: Minimal support of bitmanip extensionKito Cheng1-0/+10
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-11-18RISC-V: Support version controling for ISA standard extensionsKito Cheng1-0/+10
2020-11-18RISC-V: Support zicsr and zifencei extension for -march.Kito Cheng1-0/+6
2020-07-31RISC-V: Add support for TLS stack protector canary accessCooper Qu1-0/+6
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-07-22RISC-V: Add -malign-data= option.Ilia Diachkov1-0/+5
2019-03-26RISC-V: Add sifive-7 pipeline description.Andrew Waterman1-0/+7
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
2018-05-18RISC-V: Add RV32E support.Kito Cheng1-0/+1