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2024-07-05MIPS: Support more cases with alien mode of SHF.DFYunQiang Su3-15/+170
Currently, we support the cases that strictly fit for the instructions. For example, for V16QImode, we only support shuffle like (0<=N0, N1, N2, N3<=3 here) N0, N1, N2, N3 N0+4 N1+4 N2+4, N3+4 N0+8 N1+8 N2+8, N3+8 N0+12 N1+12 N2+12, N3+12 While in fact we can support more cases to try use other SHF.DF instructions not strictly fitting the mode. 1) We can use SHF.H to support more cases for V16QImode: (M0/M1/M2/M3 are 0 or 2 or 4 or 6) M0 M0+1, M1, M1+1 M2 M2+1, M3, M3+1 M0+8 M0+9, M1+8, M1+9 M2+8 M2+9, M3+8, M3+9 2) We can use SHF.W to support some cases for V16QImode: (M0/M1/M2/M3 are 0 or 4 or 8 or 12) M0, M0+1, M0+2, M0+3 M1, M1+1, M1+2, M1+3 M2, M2+1, M2+2, M2+3 M3, M3+1, M3+2, M3+3 3) We can use SHF.W to support some cases for V8HImode: (M0/M1/M2/M3 are 0 or 2 or 4 or 6) M0, M0+1 M1, M1+1 M2, M2+1 M3, M3+1 4) We can also use SHF.W to swap the 2 parts of V2DF or V2DI. gcc * config/mips/mips-protos.h: New function mips_msa_shf_i8. * config/mips/mips-msa.md(MSA_WHB_W): Not used anymore; (msa_shf_<msafmt_f>): Use mips_msa_shf_i8. * config/mips/mips.cc(mips_const_vector_shuffle_set_p): Support more cases try to use alien mode instruction; (mips_msa_shf_i8): New function to get the correct MSA SHF instruction and IMM.
2024-06-25MIPS: Implement vcond_mask optabs for MSAYunQiang Su3-9/+28
Currently, we have `mips_expand_vec_cond_expr`, which calculate cmp_res first. We can just add a new extra argument to ask it to use operands[3] as cmp_res instead of calculating from operands[4] and operands[5]. gcc * config/mips/mips.cc(mips_expand_vec_cond_expr): Add extra argument to info that opernads[3] is cmp_res already. * config/mips/mips-protos.h(mips_expand_vec_cond_expr): Ditto. * config/mips/mips-msa.md(vcond_mask): Define new expand. (vcondu): Use mips_expand_vec_cond_expr with 4th argument. (vcond): Ditto.
2024-06-25MIPS: Output $0 for conditional trap if !ISA_HAS_COND_TRAPIYunQiang Su1-1/+1
MIPSr6 removes condition trap instructions with imm, so the instruction like `teq $2,imm` will be converted to li $at, imm teq $2, $at The current version of Gas cannot detect if imm is zero, and output teq $2, $0 Let's do it in GCC. gcc * config/mips/mips.md(conditional_trap_reg): Output $0 instead of 0 if !ISA_HAS_COND_TRAPI.
2024-06-25Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook mode_for_floating_typeKewen Lin3-9/+22
Currently how we determine which mode will be used for a floating point type is that for a given type precision (size) call mode_for_size to get the first mode which has this size in the specified class. On Powerpc, we have three modes (TF/KF/IF) having the same mode precision 128 (see[1]), so the processing forces us to have to place TF at the first place, it would require us to make more adjustment in some generic code to avoid some unexpected mode conversions and it would be even worse if we get rid of TF eventually one day. And as Joseph pointed out in [2], "floating types should have their mode, not a poorly defined precision value", as Joseph and Richi suggested, this patch is to introduce one hook mode_for_floating_type which returns the corresponding mode for type float, double or long double. The default implementation returns SFmode for float and DFmode for double or long double. For ports which need special treatment, there are some other patches for their own port specific implementation (referring to how {,LONG_}DOUBLE_TYPE_SIZE get used there). For all generic uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE, depending on the context, some of them are replaced with TYPE_PRECISION of the according type node, some other are replaced with GET_MODE_PRECISION on the mode from mode_for_floating_type. This patch also poisons {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE, so most defines of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE in port specific are removed, but there are still some which are good to be kept for readability then they get renamed with port specific prefix. [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651017.html [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651209.html gcc/jit/ChangeLog: * jit-recording.cc (recording::memento_of_get_type::get_size): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE. gcc/ChangeLog: * coretypes.h (enum tree_index): Forward declaration. * defaults.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * doc/rtl.texi: Update document by replacing {FLOAT,DOUBLE}_TYPE_SIZE with C type {float,double}. * doc/tm.texi.in: Document new hook mode_for_floating_type, remove document entries for {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE and update document for WIDEST_HARDWARE_FP_SIZE. * doc/tm.texi: Regenerate. * emit-rtl.cc (init_emit_once): Replace DOUBLE_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_DOUBLE_TYPE. * real.h (REAL_VALUE_TO_TARGET_LONG_DOUBLE): Use TYPE_PRECISION of long_double_type_node to replace LONG_DOUBLE_TYPE_SIZE. * system.h (FLOAT_TYPE_SIZE): Poison. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * target.def (mode_for_floating_type): New hook. * targhooks.cc (default_mode_for_floating_type): New function. (default_scalar_mode_supported_p): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE. * targhooks.h (default_mode_for_floating_type): New declaration. * tree-core.h (enum tree_index): Specify underlying type unsigned to sync with forward declaration in coretypes.h. (NUM_FLOATN_TYPES): Explicitly convert to int. (NUM_FLOATNX_TYPES): Likewise. (NUM_FLOATN_NX_TYPES): Likewise. * tree.cc (build_common_tree_nodes): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE and set type mode accordingly. * config/arc/arc.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/bpf/bpf.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/epiphany/epiphany.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/fr30/fr30.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/frv/frv.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/ft32/ft32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/gcn/gcn.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/iq2000/iq2000.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/lm32/lm32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/m32c/m32c.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/m32r/m32r.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/microblaze/microblaze.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/mmix/mmix.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/moxie/moxie.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/msp430/msp430.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nds32/nds32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nios2/nios2.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nvptx/nvptx.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/or1k/or1k.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pdp11/pdp11.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pru/pru.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/stormy16/stormy16.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/visium/visium.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/xtensa/xtensa.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rs6000/rs6000.cc (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (rs6000_c_mode_for_floating_type): New function. * config/rs6000/rs6000.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/aarch64/aarch64.cc (aarch64_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/aarch64/aarch64.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/alpha/alpha.cc (alpha_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/alpha/alpha.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/avr/avr.cc (avr_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/avr/avr.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/i386/i386.cc (ix86_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/i386/i386.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/ia64/ia64.cc (ia64_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/ia64/ia64.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/riscv/riscv.cc (riscv_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/riscv/riscv.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rl78/rl78.cc (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (rl78_c_mode_for_floating_type): New function. * config/rl78/rl78.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rx/rx.cc (rx_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/rx/rx.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/s390/s390.cc (s390_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/s390/s390.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/sh/sh.cc (sh_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/sh/sh.h (LONG_DOUBLE_TYPE_SIZE): Remove. * config/h8300/h8300.cc (h8300_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/h8300/h8300.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Remove. (DOUBLE_TYPE_MODE): New macro. * config/h8300/linux.h (DOUBLE_TYPE_SIZE): Remove. (DOUBLE_TYPE_MODE): New macro. * config/loongarch/loongarch.cc (loongarch_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/loongarch/loongarch.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (LA_LONG_DOUBLE_TYPE_SIZE): ... this. (UNITS_PER_FPVALUE): Replace LONG_DOUBLE_TYPE_SIZE with LA_LONG_DOUBLE_TYPE_SIZE. (MAX_FIXED_MODE_SIZE): Likewise. (STRUCTURE_SIZE_BOUNDARY): Likewise. (BIGGEST_ALIGNMENT): Likewise. * config/m68k/m68k.cc (m68k_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/m68k/m68k.h (LONG_DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_MODE): New macro. * config/m68k/netbsd-elf.h (LONG_DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_MODE): New macro. * config/mips/mips.cc (mips_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/mips/mips.h (UNITS_PER_FPVALUE): Replace LONG_DOUBLE_TYPE_SIZE with MIPS_LONG_DOUBLE_TYPE_SIZE. (MAX_FIXED_MODE_SIZE): Likewise. (STRUCTURE_SIZE_BOUNDARY): Likewise. (BIGGEST_ALIGNMENT): Likewise. (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (MIPS_LONG_DOUBLE_TYPE_SIZE): ... this. * config/mips/n32-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (MIPS_LONG_DOUBLE_TYPE_SIZE): ... this. * config/pa/pa.cc (pa_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (pa_scalar_mode_supported_p): Rename FLOAT_TYPE_SIZE to PA_FLOAT_TYPE_SIZE, rename DOUBLE_TYPE_SIZE to PA_DOUBLE_TYPE_SIZE and rename LONG_DOUBLE_TYPE_SIZE to PA_LONG_DOUBLE_TYPE_SIZE. * config/pa/pa.h (PA_FLOAT_TYPE_SIZE): New macro. (PA_DOUBLE_TYPE_SIZE): Likewise. (PA_LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pa/pa-64.h (FLOAT_TYPE_SIZE): Rename to ... (PA_FLOAT_TYPE_SIZE): ... this. (DOUBLE_TYPE_SIZE): Rename to ... (PA_DOUBLE_TYPE_SIZE): ... this. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (PA_LONG_DOUBLE_TYPE_SIZE): ... this. * config/pa/pa-hpux.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (PA_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sparc.cc (sparc_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. (sparc_type_code): Replace FLOAT_TYPE_SIZE with TYPE_PRECISION of float_type_node. * config/sparc/sparc.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. * config/sparc/freebsd.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/linux.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/linux64.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/netbsd-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/openbsd64.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sol2.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sp-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sp64-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/bfin/bfin.h (FLOAT_TYPE_SIZE): Rename to ... (BFIN_FLOAT_TYPE_SIZE): ... this. (DOUBLE_TYPE_SIZE): Rename to ... (BFIN_DOUBLE_TYPE_SIZE): ... this. (LONG_DOUBLE_TYPE_SIZE): Remove. (UNITS_PER_FLOAT): Replace FLOAT_TYPE_SIZE with BFIN_FLOAT_TYPE_SIZE. (UNITS_PER_DOUBLE): Replace DOUBLE_TYPE_SIZE with BFIN_DOUBLE_TYPE_SIZE.
2024-06-21MIPS: Set condmove cost to SET(REG, REG)YunQiang Su2-4/+28
On most uarch, the cost condmove is same as other noraml integer, and it should be COSTS_N_INSNS(1). In GCC12 or previous, the condmove is always enabled, and from GCC13, we start to compare the cost. The generic rtx_cost give the result of COSTS_N_INSN(2). Let's define it to COSTS_N_INSN(1) in mips_rtx_costs. gcc * config/mips/mips.cc(mips_rtx_costs): Set condmove cost. * config/mips/mips.md(mov<GPR:mode>_on_<MOVECC:mode>, mov<GPR:mode>_on_<MOVECC:mode>_mips16e2, mov<GPR:mode>_on_<GPR2:mode>_ne mov<GPR:mode>_on_<GPR2:mode>_ne_mips16e2): Define name by remove starting *, so that we can use CODE_FOR_. gcc/testsuite * gcc.target/mips/movcc-2.c: Add k?100:1000 test.
2024-06-13MIPS: Use FPU-enabled tune for mips32/mips64/mips64r2/mips64r3/mips64r5YunQiang Su1-5/+5
Currently, the default tune value of mips32 is PROCESSOR_4KC, and the default tune value of mips64/mips64r2/mips64r3/mips64r5 is PROCESSOR_5KC. PROCESSOR_4KC and PROCESSOR_5KC are both FPU-less. Let's use PROCESSOR_24KF1_1 for mips32, and PROCESSOR_5KF for mips64/ mips64r2/mips64r3/mips64r5. We find this problem when we try to fix gcc.target/mips/movcc-3.c. gcc: * config/mips/mips-cpus.def: Use PROCESSOR_24KF1_1 for mips32; Use PROCESSOR_5KF for mips64/mips64r2/mips64r3/mips64r5.
2024-06-13MIPS: Use signaling fcmp instructions for LT/LE/LTGTYunQiang Su5-11/+61
LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/cmp.le.fmt have different semantic: c.lt.fmt will signal for all NaN, including qNaN; cmp.lt.fmt will only signal sNaN, while not qNaN; cmp.slt.fmt has the same semantic as c.lt.fmt; lt/le of RTL will signaling qNaN. while in `s<code>_<SCALARF:mode>_using_<FPCC:mode>`, RTL operation `lt`/`le` are convert to c/cmp's lt/le, which is correct for C.cond.fmt, while not for CMP.cond.fmt. Let's convert them to slt/sle if ISA_HAS_CCF. For LTGT, which signals qNaN, `sne` of r6 has same semantic, while pre-R6 has only inverse one `ngl`. Thus for RTL we have to use the `uneq` as the operator, and introduce a new CC mode: CCEmode to mark it as signaling. This patch can fix gcc.dg/torture/pr91323.c for pre-R6; gcc.dg/torture/builtin-iseqsig-* for R6. gcc: * config/mips/mips-modes.def: New CC_MODE CCE. * config/mips/mips-protos.h(mips_output_compare): New function. * config/mips/mips.cc(mips_allocate_fcc): Set CCEmode count=1. (mips_emit_compare): Use CCEmode for LTGT/LT/LE for pre-R6. (mips_output_compare): New function. Convert lt/le to slt/sle for R6; convert ueq to ngl for CCEmode. (mips_hard_regno_mode_ok_uncached): Mention CCEmode. * config/mips/mips.h: Mention CCEmode for LOAD_EXTEND_OP. * config/mips/mips.md(FPCC): Add CCE. (define_mode_iterator MOVECC): Mention CCE. (define_mode_attr reg): Add CCE with "z". (define_mode_attr fpcmp): Add CCE with "c". (define_code_attr fcond): ltgt should use sne instead of ne. (s<code>_<SCALARF:mode>_using_<FPCC:mode>): call mips_output_compare.
2024-06-06MIPS: Need COSTS_N_INSNS in mips_insn_costYunQiang Su1-1/+1
In mips_insn_cost, COSTS_N_INSNS is missing when we return the cost if count * ratio > 0. gcc * config/mips/mips.cc(mips_insn_cost): Add missing COSTS_N_INSNS to count.
2024-05-30MIPS16: Mark $2/$3 as clobbered if GP is usedYunQiang Su1-1/+10
PR Target/84790. The gp init sequence li $2,%hi(_gp_disp) addiu $3,$pc,%lo(_gp_disp) sll $2,16 addu $2,$3 is generated directly in `mips_output_function_prologue`, and does not appear in the RTL. So the IRA/IPA passes are not aware that $2/$3 have been clobbered, so they may be used for cross (local) function call. Let's mark $2/$3 clobber both: - Just after the UNSPEC_GP RTL of a function; - Just after a function call. Reported-by: Matthias Schiffer <mschiffer@universe-factory.net> Origin-Patch-by: Felix Fietkau <nbd@nbd.name>. gcc * config/mips/mips.cc(mips16_gp_pseudo_reg): Mark MIPS16_PIC_TEMP and MIPS_PROLOGUE_TEMP clobbered. (mips_emit_call_insn): Mark MIPS16_PIC_TEMP and MIPS_PROLOGUE_TEMP clobbered if MIPS16 and CALL_CLOBBERED_GP.
2024-05-20MIPS: Remove -m(no-)lra optionYunQiang Su4-39/+3
PR target/113955 The `-mlra` option was introduced in 2014 for MIPS, and was set to default since then. It's time for us to drop no-lra support by dropping -m(no-)lra options. gcc: * config/mips/mips.cc(mips_option_override): Drop mips_lra_flag variable; (mips_lra_p): Removed. (TARGET_LRA_P): Remove definition here to use the default one. * config/mips/mips.md(*mul_acc_si, *mul_acc_si_r3900, *mul_sub_si): Drop mips_lra_flag variable. * config/mips/mips.opt(-mlra): Removed. * config/mips/mips.opt.urls(mlra): Removed.
2024-05-13Revert "MIPS: Support constraint 'w' for MSA instruction"YunQiang Su1-3/+0
This reverts commit 9ba01240864ac446052d97692e2199539b7c76d8. It is not needed at all: asm volatile ("fmadd.d %w0, %1, %2" : "+f"(a) : "f"(b), "f"(c)) is OK for us.
2024-05-09MIPS: Support constraint 'w' for MSA instructionYunQiang Su1-0/+3
Support syntax like: asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c)); gcc * config/mips/constraints.md: Add new constraint 'w'. gcc/testsuite * gcc.target/mips/msa-inline-asm.c: New test.
2024-04-29MIPS: Add MIN/MAX.fmt instructions support for MIPS R6Jie Mei4-4/+58
This patch adds the smin/smax RTL mode for the min/max.fmt instructions. Also, since the min/max.fmt instrucions applies to the IEEE 754-2008 "minNum" and "maxNum" operations, this patch also provides the new "fmin<mode>3" and "fmax<mode>3" modes. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_minmax): New define_insn_reservation. * config/mips/mips.h (ISA_HAS_FMIN_FMAX): Define new macro. * config/mips/mips.md (UNSPEC_FMIN): New unspec. (UNSPEC_FMAX): Same as above. (type): Add fminmax. (smin<mode>3): Generates MIN.fmt instructions. (smax<mode>3): Generates MAX.fmt instructions. (fmin<mode>3): Generates MIN.fmt instructions. (fmax<mode>3): Generates MAX.fmt instructions. * config/mips/p6600.md (p6600_fpu_fabs): Include fminmax type. gcc/testsuite/ChangeLog: * gcc.target/mips/mips-minmax1.c: New test for MIPS R6. * gcc.target/mips/mips-minmax2.c: Same as above.
2024-03-30mips: Fix C23 (...) functions returning large aggregates [PR114175]Xi Ruoyao1-1/+7
We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and there is nothing to advance, but that is not the case for (...) functions returning by hidden reference which have one such artificial argument. This is causing gcc.dg/c23-stdarg-{6,8,9}.c to fail. Fix the issue by checking if arg.type is NULL, as r14-9503 explains. gcc/ChangeLog: PR target/114175 * config/mips/mips.cc (mips_setup_incoming_varargs): Only skip mips_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions if arg.type is NULL.
2024-03-26MIPS: Predefine __mips_strict_alignment if STRICT_ALIGNMENTYunQiang Su1-0/+3
Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access, and RISC-V predefines __riscv_misaligned_avoid. Let's define __mips_strict_alignment for MIPSr6 and -mstrict-align is used. Note that, this macro is always defined for pre-R6. gcc * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Predefine __mips_strict_alignment if STRICT_ALIGNMENT.
2024-03-15MIPS: Add -m(no-)strict-align optionYunQiang Su3-3/+17
We support options -m(no-)unaligned-access 2 years ago, while currently most of other ports prefer -m(no-)strict-align. Let's support -m(no-)strict-align, and keep -m(no-)unaligned-access as alias. gcc * config/mips/mips.opt: Support -mstrict-align, and use TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access as alias. * config/mips/mips.h: Use TARGET_STRICT_ALIGN. * config/mips/mips.opt.urls: Regenerate. * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
2024-02-22invoke.texi: Fix some skipping UrlSuffix problem for MIPSYunQiang Su1-2/+10
The problem is that, there are these lines in mips.opt.urls: ; skipping UrlSuffix for 'mabi=' due to finding no URLs ; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs ; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs These lines is not fixed by this patch due to that we don't document these options: ; skipping UrlSuffix for 'mlra' due to finding no URLs ; skipping UrlSuffix for 'mdebug' due to finding no URLs ; skipping UrlSuffix for 'meb' due to finding no URLs ; skipping UrlSuffix for 'mel' due to finding no URLs gcc * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix problem of mabi=, mno-flush-func, mexplicit-relocs; add missing leading - of mbranch-cost option. * config/mips/mips.opt.urls: Regenerate.
2024-02-05mips: Fix missing mode in neg<mode:MSA>2Xi Ruoyao1-1/+1
I was too sleepy writting this :(. gcc/ChangeLog: * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for neg.
2024-02-05MIPS: Fix wrong MSA FP vector negationXi Ruoyao1-3/+15
We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is wrong because -0.0 is not 0 - 0.0. This causes some Python tests to fail when Python is built with MSA enabled. Use the bnegi.df instructions to simply reverse the sign bit instead. gcc/ChangeLog: * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr. (neg<mode>2): Change the mode iterator from MSA to IMSA because in FP arithmetic we cannot use (0 - x) for -x. (neg<mode>2): New define_insn to implement FP vector negation, using a bnegi instruction to negate the sign bit.
2024-01-24MIPS: Accept arguments for -mexplicit-relocsYunQiang Su4-4/+41
GAS introduced explicit relocs since 2001, and %pcrel_hi/low were introduced in 2014. In future, we may introduce more. Let's convert -mexplicit-relocs option, and accpet options: none, base, pcrel. We also update gcc/configure.ac to set the value to option the gas support when GCC itself is built. gcc * configure.ac: Detect the explicit relocs support for mips, and define C macro MIPS_EXPLICIT_RELOCS. * config.in: Regenerated. * configure: Regenerated. * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs. * config/mips/mips-opts.h: Define enum mips_explicit_relocs. * config/mips/mips.cc(mips_set_compression_mode): Sorry if !TARGET_EXPLICIT_RELOCS instead of just set it. * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs. * config/mips/mips.opt: Introduce -mexplicit-relocs= option and define -m(no-)explicit-relocs as aliases.
2024-01-17MIPS: avoid $gp store if global_pointer is not $gpYunQiang Su1-0/+2
$GP is used for expanding GOT load, but in the afterward passes, a temporary register is tried to replace $gp. If sucess, we have no need to store and reload $gp. The example of failure is that the function calls a preemtive function. We shouldn't use $GP for any other purpose in the code we generate. If a user's inline asm code clobbers $GP, it's their duty to save and restore $GP. gcc * config/mips/mips.cc (mips_compute_frame_info): If another register is used as global_pointer, mark $GP live false. gcc/testsuite * gcc.target/mips/mips.exp (mips_option_groups): Add -mxgot/-mno-xgot options. * gcc.target/mips/xgot-n32-avoid-gp.c: New test. * gcc.target/mips/xgot-n32-need-gp.c: New test.
2024-01-14[committed] Fix MIPS bootstrapJeff Law1-5/+5
mips bootstraps have been broken for a while. They've been triggering an error about mutually exclusive equal-tests always being false when building gencondmd. This was ultimately tracked down to the ior<mode>3_mips16_asmacro pattern. The pattern uses the GPR mode iterator which looks like this: (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) The condition for the pattern looks like this: "ISA_HAS_MIPS16E2" And if you dig into ISA_HAS_MIPS16E2: /* The MIPS16e V2 instructions are available. */ && !TARGET_64BIT) The way the mode iterator is handled is by adding its condition to the pattern's condition when we expand copies of the pattern resulting in this condition for one of the two generated patterns: (TARGET_MIPS16 && TARGET_MIPS16E2 && !TARGET_64BIT) && TARGET_64BIT This can never be true because of the TARGET_64BIT tests. The fix is trivial. Don't use a mode iterator on that pattern. Bootstrapped on mips64el. I don't have any tests to compare against, so no regression test data. gcc/ * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode, not the GPR iterator. Adjust pattern name and mode attribute accordingly.
2024-01-11MIPS: Add ATTRIBUTE_UNUSED to mips_start_function_definitionYunQiang Su1-1/+2
Fix build warning: mips.cc: warning: unused parameter 'decl'. gcc * config/mips/mips.cc (mips_start_function_definition): Add ATTRIBUTE_UNUSED.
2024-01-05Implement ASM_DECLARE_FUNCTION_NAME using ASM_OUTPUT_FUNCTION_LABELIlya Leoshkevich1-9/+10
gccint recommends using ASM_OUTPUT_FUNCTION_LABEL in ASM_DECLARE_FUNCTION_NAME, but many implementations use ASM_OUTPUT_LABEL instead. It's inconsistent and prevents changes to ASM_OUTPUT_FUNCTION_LABEL from affecting the respective targets. Link: https://inbox.sourceware.org/gcc-patches/20240102194511.3171559-2-iii@linux.ibm.com/ Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_declare_function_name): Use ASM_OUTPUT_FUNCTION_LABEL (). * config/alpha/alpha.cc (alpha_start_function): Likewise. * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise. * config/arm/arm.cc (arm_asm_declare_function_name): Likewise. * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise. * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise. * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise. * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise. * config/ia64/ia64.cc (ia64_start_function): Likewise. * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME): Likewise. * config/microblaze/microblaze.cc (microblaze_function_prologue): Likewise. * config/mips/mips.cc (mips_start_unique_function): Return the tree. (mips_start_function_definition): Use ASM_OUTPUT_FUNCTION_LABEL (). (mips_finish_stub): Pass the tree to mips_start_function_definition (). (mips16_build_function_stub): Likewise. (mips16_build_call_stub): Likewise. (mips_output_function_prologue): Likewise. * config/pa/pa.cc (pa_output_function_label): Use ASM_OUTPUT_FUNCTION_LABEL (). * config/riscv/riscv.cc (riscv_declare_function_name): Likewise. * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name): Likewise. (rs6000_xcoff_declare_function_name): Likewise.
2024-01-04Add generated .opt.urls filesDavid Malcolm3-0/+273
Changed in v5: regenerated Changed in v4: regenerated Changed in v3: regenerated Changed in v2: the files now contain some lang-specific URLs. gcc/ada/ChangeLog: * gcc-interface/lang.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/analyzer/ChangeLog: * analyzer.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/c-family/ChangeLog: * c.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/ChangeLog: * common.opt.urls: New file, autogenerated by regenerate-opt-urls.py. * config/aarch64/aarch64.opt.urls: Likewise. * config/alpha/alpha.opt.urls: Likewise. * config/alpha/elf.opt.urls: Likewise. * config/arc/arc-tables.opt.urls: Likewise. * config/arc/arc.opt.urls: Likewise. * config/arm/arm-tables.opt.urls: Likewise. * config/arm/arm.opt.urls: Likewise. * config/arm/vxworks.opt.urls: Likewise. * config/avr/avr.opt.urls: Likewise. * config/bpf/bpf.opt.urls: Likewise. * config/c6x/c6x-tables.opt.urls: Likewise. * config/c6x/c6x.opt.urls: Likewise. * config/cris/cris.opt.urls: Likewise. * config/cris/elf.opt.urls: Likewise. * config/csky/csky.opt.urls: Likewise. * config/csky/csky_tables.opt.urls: Likewise. * config/darwin.opt.urls: Likewise. * config/dragonfly.opt.urls: Likewise. * config/epiphany/epiphany.opt.urls: Likewise. * config/fr30/fr30.opt.urls: Likewise. * config/freebsd.opt.urls: Likewise. * config/frv/frv.opt.urls: Likewise. * config/ft32/ft32.opt.urls: Likewise. * config/fused-madd.opt.urls: Likewise. * config/g.opt.urls: Likewise. * config/gcn/gcn.opt.urls: Likewise. * config/gnu-user.opt.urls: Likewise. * config/h8300/h8300.opt.urls: Likewise. * config/hpux11.opt.urls: Likewise. * config/i386/cygming.opt.urls: Likewise. * config/i386/cygwin.opt.urls: Likewise. * config/i386/djgpp.opt.urls: Likewise. * config/i386/i386.opt.urls: Likewise. * config/i386/mingw-w64.opt.urls: Likewise. * config/i386/mingw.opt.urls: Likewise. * config/i386/nto.opt.urls: Likewise. * config/ia64/ia64.opt.urls: Likewise. * config/ia64/ilp32.opt.urls: Likewise. * config/ia64/vms.opt.urls: Likewise. * config/iq2000/iq2000.opt.urls: Likewise. * config/linux-android.opt.urls: Likewise. * config/linux.opt.urls: Likewise. * config/lm32/lm32.opt.urls: Likewise. * config/loongarch/loongarch.opt.urls: Likewise. * config/lynx.opt.urls: Likewise. * config/m32c/m32c.opt.urls: Likewise. * config/m32r/m32r.opt.urls: Likewise. * config/m68k/ieee.opt.urls: Likewise. * config/m68k/m68k-tables.opt.urls: Likewise. * config/m68k/m68k.opt.urls: Likewise. * config/m68k/uclinux.opt.urls: Likewise. * config/mcore/mcore.opt.urls: Likewise. * config/microblaze/microblaze.opt.urls: Likewise. * config/mips/mips-tables.opt.urls: Likewise. * config/mips/mips.opt.urls: Likewise. * config/mips/sde.opt.urls: Likewise. * config/mmix/mmix.opt.urls: Likewise. * config/mn10300/mn10300.opt.urls: Likewise. * config/moxie/moxie.opt.urls: Likewise. * config/msp430/msp430.opt.urls: Likewise. * config/nds32/nds32-elf.opt.urls: Likewise. * config/nds32/nds32-linux.opt.urls: Likewise. * config/nds32/nds32.opt.urls: Likewise. * config/netbsd-elf.opt.urls: Likewise. * config/netbsd.opt.urls: Likewise. * config/nios2/elf.opt.urls: Likewise. * config/nios2/nios2.opt.urls: Likewise. * config/nvptx/nvptx-gen.opt.urls: Likewise. * config/nvptx/nvptx.opt.urls: Likewise. * config/openbsd.opt.urls: Likewise. * config/or1k/elf.opt.urls: Likewise. * config/or1k/or1k.opt.urls: Likewise. * config/pa/pa-hpux.opt.urls: Likewise. * config/pa/pa-hpux1010.opt.urls: Likewise. * config/pa/pa-hpux1111.opt.urls: Likewise. * config/pa/pa-hpux1131.opt.urls: Likewise. * config/pa/pa.opt.urls: Likewise. * config/pa/pa64-hpux.opt.urls: Likewise. * config/pdp11/pdp11.opt.urls: Likewise. * config/pru/pru.opt.urls: Likewise. * config/riscv/riscv.opt.urls: Likewise. * config/rl78/rl78.opt.urls: Likewise. * config/rpath.opt.urls: Likewise. * config/rs6000/476.opt.urls: Likewise. * config/rs6000/aix64.opt.urls: Likewise. * config/rs6000/darwin.opt.urls: Likewise. * config/rs6000/linux64.opt.urls: Likewise. * config/rs6000/rs6000-tables.opt.urls: Likewise. * config/rs6000/rs6000.opt.urls: Likewise. * config/rs6000/sysv4.opt.urls: Likewise. * config/rtems.opt.urls: Likewise. * config/rx/elf.opt.urls: Likewise. * config/rx/rx.opt.urls: Likewise. * config/s390/s390.opt.urls: Likewise. * config/s390/tpf.opt.urls: Likewise. * config/sh/sh.opt.urls: Likewise. * config/sh/superh.opt.urls: Likewise. * config/sol2.opt.urls: Likewise. * config/sparc/long-double-switch.opt.urls: Likewise. * config/sparc/sparc.opt.urls: Likewise. * config/stormy16/stormy16.opt.urls: Likewise. * config/v850/v850.opt.urls: Likewise. * config/vax/elf.opt.urls: Likewise. * config/vax/vax.opt.urls: Likewise. * config/visium/visium.opt.urls: Likewise. * config/vms/vms.opt.urls: Likewise. * config/vxworks-smp.opt.urls: Likewise. * config/vxworks.opt.urls: Likewise. * config/xtensa/elf.opt.urls: Likewise. * config/xtensa/uclinux.opt.urls: Likewise. * config/xtensa/xtensa.opt.urls: Likewise. gcc/d/ChangeLog: * lang.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/fortran/ChangeLog: * lang.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/go/ChangeLog: * lang.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/lto/ChangeLog: * lang.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/m2/ChangeLog: * lang.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/ChangeLog: * params.opt.urls: New file, autogenerated by regenerate-opt-urls.py. gcc/rust/ChangeLog: * lang.opt.urls: New file, autogenerated by regenerate-opt-urls.py. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-01-04MIPS: Add pattern insqisi_extended and inshisi_extendedYunQiang Su1-0/+24
This match pattern allows combination (zero_extract:DI 8, 24, QI) with an sign-extend to 32bit INS instruction on TARGET_64BIT. For SI mode, if the sign-bit is modified by bitops, we will need a sign-extend operation. Since 32bit INS instruction can be sure that result is sign-extended, and the QImode src register is safe for INS, too. (insn 19 18 20 2 (set (zero_extract:DI (reg/v:DI 200 [ val ]) (const_int 8 [0x8]) (const_int 24 [0x18])) (subreg:DI (reg:QI 205) 0)) "../xx.c":7:29 -1 (nil)) (insn 20 19 23 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (subreg:SI (reg/v:DI 200 [ val ]) 0))) "../xx.c":7:29 -1 (nil)) Combine try to merge them to: (insn 20 19 23 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (ior:SI (and:SI (subreg:SI (reg/v:DI 200 [ val ]) 0) (const_int 16777215 [0xffffff])) (ashift:SI (subreg:SI (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) 0) (const_int 24 [0x18]))))) "../xx.c":7:29 18 {*insv_extended} (expr_list:REG_DEAD (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) (nil))) And do similarly for 16/16 pair: (insn 13 12 14 2 (set (zero_extract:DI (reg/v:DI 198 [ val ]) (const_int 16 [0x10]) (const_int 16 [0x10])) (subreg:DI (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) 0)) "xx.c":5:30 286 {*insvdi} (expr_list:REG_DEAD (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) (nil))) (insn 14 13 17 2 (set (reg/v:DI 198 [ val ]) (sign_extend:DI (subreg:SI (reg/v:DI 198 [ val ]) 0))) "xx.c":5:30 241 {extendsidi2} (nil)) ------------> (insn 14 13 17 2 (set (reg/v:DI 198 [ val ]) (sign_extend:DI (ior:SI (ashift:SI (subreg:SI (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) 0) (const_int 16 [0x10])) (zero_extend:SI (subreg:HI (reg/v:DI 198 [ val ]) 0))))) "xx.c":5:30 284 {*inshisi_extended} (expr_list:REG_DEAD (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) (nil))) Let's accept these patterns, and set the cost to 1 instruction. gcc PR rtl-optimization/104914 * config/mips/mips.md (insqisi_extended): New patterns. (inshisi_extended): Ditto. gcc/testsuite * gcc.target/mips/pr104914.c: New test.
2024-01-04MIPS: Implement TARGET_INSN_COSTSYunQiang Su1-0/+33
When combine some instructions, the generic `rtx_cost` may over estimate the cost of result RTL, due to that the RTL may be quite complex and `rtx_cost` has no information that this RTL can be convert to simple hardware instruction(s). In this case, Let's use `insn_count * perf_ratio` to estimate the cost if both of them are available. Otherwise fallback to pattern_cost. When non-speed, Let's use the length as cost. gcc * config/mips/mips.cc (mips_insn_cost): New function. gcc/testsuite * gcc.target/mips/data-sym-multi-pool.c: Skip Os or -O0.
2024-01-04MIPS: define_attr perf_ratio in mips.mdYunQiang Su1-0/+4
The accurate cost of an pattern can get with insn_count * perf_ratio The default value is set to 0 instead of 1, since that we will need to distinguish the default value and it is really set for an pattern. Since it is not set for most patterns yet, to use it, we will need to be sure that it's value is greater than 0. This attr will be used in `mips_insn_cost`. gcc * config/mips/mips.md (perf_ratio): New attribute.
2024-01-03Update copyright years.Jakub Jelinek95-96/+96
2023-12-23MIPS: Don't add nan2008 option for -mtune=nativeYunQiang Su1-1/+2
Users may wish just use -mtune=native for performance tuning only. Let's don't make trouble for its case. gcc/ * config/mips/driver-native.cc (host_detect_local_cpu): don't add nan2008 option for -mtune=native.
2023-12-23MIPS: Put the ret to the end of args of reconcat [PR112759]YunQiang Su1-2/+5
The function `reconcat` cannot append string(s) to NULL, as the concat process will stop at the first NULL. Let's always put the `ret` to the end, as it may be NULL. We keep use reconcat here, due to that reconcat can make it easier if we add more hardware features detecting, for example by hwcap. gcc/ PR target/112759 * config/mips/driver-native.cc (host_detect_local_cpu): Put the ret to the end of args of reconcat.
2023-12-02Allow target attributes in non-gnu namespacesRichard Sandiford1-4/+3
Currently there are four static sources of attributes: - LANG_HOOKS_ATTRIBUTE_TABLE - LANG_HOOKS_COMMON_ATTRIBUTE_TABLE - LANG_HOOKS_FORMAT_ATTRIBUTE_TABLE - TARGET_ATTRIBUTE_TABLE All of the attributes in these tables go in the "gnu" namespace. This means that they can use the traditional GNU __attribute__((...)) syntax and the standard [[gnu::...]] syntax. Standard attributes are registered dynamically with a null namespace. There are no supported attributes in other namespaces (clang, vendor namespaces, etc.). This patch tries to generalise things by making the namespace part of the attribute specification. It's usual for multiple attributes to be defined in the same namespace, so rather than adding the namespace to each individual definition, it seemed better to group attributes in the same namespace together. This would also allow us to reuse the same table for clang attributes that are written with the GNU syntax, or other similar situations where the attribute can be accessed via multiple "spellings". The patch therefore adds a scoped_attribute_specs that contains a namespace and a list of attributes in that namespace. It's still possible to have multiple scoped_attribute_specs for the same namespace. E.g. it makes sense to keep the C++-specific, C/C++-common, and format-related attributes in separate tables, even though they're all GNU attributes. Current lists of attributes are terminated by a null name. Rather than keep that for the new structure, it seemed neater to use an array_slice. This also makes the tables slighly more compact. In general, a target might want to support attributes in multiple namespaces. Rather than have a separate hook for each possibility (like the three langhooks above), it seemed better to make TARGET_ATTRIBUTE_TABLE a table of tables. Specifically, it's an array_slice of scoped_attribute_specs. We can do the same thing for langhooks, which allows the three hooks above to be merged into a single LANG_HOOKS_ATTRIBUTE_TABLE. It also allows the standard attributes to be registered statically and checked by the usual attribs.cc checks. The patch adds a TARGET_GNU_ATTRIBUTES helper for the common case in which a target wants a single table of gnu attributes. It can only be used if the table is free of preprocessor directives. There are probably other things we need to do to make vendor namespaces work smoothly. E.g. in principle it would be good to make exclusion sets namespace-aware. But to some extent we have that with standard vs. gnu attributes too. This patch is just supposed to be a first step. gcc/ * attribs.h (scoped_attribute_specs): New structure. (register_scoped_attributes): Take a reference to a scoped_attribute_specs instead of separate namespace and array parameters. * plugin.h (register_scoped_attributes): Likewise. * attribs.cc (register_scoped_attributes): Likewise. (attribute_tables): Change into an array of scoped_attribute_specs pointers. Reduce to 1 element for frontends and 1 element for targets. (empty_attribute_table): Delete. (check_attribute_tables): Update for changes to attribute_tables. Use a hash_set to identify duplicates. (handle_ignored_attributes_option): Update for above changes. (init_attributes): Likewise. (excl_pair): Delete. (test_attribute_exclusions): Update for above changes. Don't enforce symmetry for standard attributes in the top-level namespace. * langhooks-def.h (LANG_HOOKS_COMMON_ATTRIBUTE_TABLE): Delete. (LANG_HOOKS_FORMAT_ATTRIBUTE_TABLE): Likewise. (LANG_HOOKS_INITIALIZER): Update accordingly. (LANG_HOOKS_ATTRIBUTE_TABLE): Define to an empty constructor. * langhooks.h (lang_hooks::common_attribute_table): Delete. (lang_hooks::format_attribute_table): Likewise. (lang_hooks::attribute_table): Redefine to an array of scoped_attribute_specs pointers. * target-def.h (TARGET_GNU_ATTRIBUTES): New macro. * target.def (attribute_spec): Redefine to return an array of scoped_attribute_specs pointers. * tree-inline.cc (function_attribute_inlinable_p): Update accordingly. * doc/tm.texi: Regenerate. * config/aarch64/aarch64.cc (aarch64_attribute_table): Define using TARGET_GNU_ATTRIBUTES. * config/alpha/alpha.cc (vms_attribute_table): Likewise. * config/avr/avr.cc (avr_attribute_table): Likewise. * config/bfin/bfin.cc (bfin_attribute_table): Likewise. * config/bpf/bpf.cc (bpf_attribute_table): Likewise. * config/csky/csky.cc (csky_attribute_table): Likewise. * config/epiphany/epiphany.cc (epiphany_attribute_table): Likewise. * config/gcn/gcn.cc (gcn_attribute_table): Likewise. * config/h8300/h8300.cc (h8300_attribute_table): Likewise. * config/loongarch/loongarch.cc (loongarch_attribute_table): Likewise. * config/m32c/m32c.cc (m32c_attribute_table): Likewise. * config/m32r/m32r.cc (m32r_attribute_table): Likewise. * config/m68k/m68k.cc (m68k_attribute_table): Likewise. * config/mcore/mcore.cc (mcore_attribute_table): Likewise. * config/microblaze/microblaze.cc (microblaze_attribute_table): Likewise. * config/mips/mips.cc (mips_attribute_table): Likewise. * config/msp430/msp430.cc (msp430_attribute_table): Likewise. * config/nds32/nds32.cc (nds32_attribute_table): Likewise. * config/nvptx/nvptx.cc (nvptx_attribute_table): Likewise. * config/riscv/riscv.cc (riscv_attribute_table): Likewise. * config/rl78/rl78.cc (rl78_attribute_table): Likewise. * config/rx/rx.cc (rx_attribute_table): Likewise. * config/s390/s390.cc (s390_attribute_table): Likewise. * config/sh/sh.cc (sh_attribute_table): Likewise. * config/sparc/sparc.cc (sparc_attribute_table): Likewise. * config/stormy16/stormy16.cc (xstormy16_attribute_table): Likewise. * config/v850/v850.cc (v850_attribute_table): Likewise. * config/visium/visium.cc (visium_attribute_table): Likewise. * config/arc/arc.cc (arc_attribute_table): Likewise. Move further down file. * config/arm/arm.cc (arm_attribute_table): Update for above changes, using... (arm_gnu_attributes, arm_gnu_attribute_table): ...these new globals. * config/i386/i386-options.h (ix86_attribute_table): Delete. (ix86_gnu_attribute_table): Declare. * config/i386/i386-options.cc (ix86_attribute_table): Replace with... (ix86_gnu_attributes, ix86_gnu_attribute_table): ...these two globals. * config/i386/i386.cc (ix86_attribute_table): Define as an array of scoped_attribute_specs pointers. * config/ia64/ia64.cc (ia64_attribute_table): Update for above changes, using... (ia64_gnu_attributes, ia64_gnu_attribute_table): ...these new globals. * config/rs6000/rs6000.cc (rs6000_attribute_table): Update for above changes, using... (rs6000_gnu_attributes, rs6000_gnu_attribute_table): ...these new globals. gcc/ada/ * gcc-interface/gigi.h (gnat_internal_attribute_table): Change type to scoped_attribute_specs. * gcc-interface/utils.cc (gnat_internal_attribute_table): Likewise, using... (gnat_internal_attributes): ...this as the underlying array. * gcc-interface/misc.cc (gnat_attribute_table): New global. (LANG_HOOKS_ATTRIBUTE_TABLE): Use it. gcc/c-family/ * c-common.h (c_common_attribute_table): Replace with... (c_common_gnu_attribute_table): ...this. (c_common_format_attribute_table): Change type to scoped_attribute_specs. * c-attribs.cc (c_common_attribute_table): Replace with... (c_common_gnu_attributes, c_common_gnu_attribute_table): ...these new globals. (c_common_format_attribute_table): Change type to scoped_attribute_specs, using... (c_common_format_attributes): ...this as the underlying array. gcc/c/ * c-tree.h (std_attribute_table): Declare. * c-decl.cc (std_attribute_table): Change type to scoped_attribute_specs, using... (std_attributes): ...this as the underlying array. (c_init_decl_processing): Remove call to register_scoped_attributes. * c-objc-common.h (c_objc_attribute_table): New global. (LANG_HOOKS_ATTRIBUTE_TABLE): Use it. (LANG_HOOKS_COMMON_ATTRIBUTE_TABLE): Delete. (LANG_HOOKS_FORMAT_ATTRIBUTE_TABLE): Delete. gcc/cp/ * cp-tree.h (cxx_attribute_table): Delete. (cxx_gnu_attribute_table, std_attribute_table): Declare. * cp-objcp-common.h (LANG_HOOKS_COMMON_ATTRIBUTE_TABLE): Delete. (LANG_HOOKS_FORMAT_ATTRIBUTE_TABLE): Delete. (cp_objcp_attribute_table): New table. (LANG_HOOKS_ATTRIBUTE_TABLE): Redefine. * tree.cc (cxx_attribute_table): Replace with... (cxx_gnu_attributes, cxx_gnu_attribute_table): ...these globals. (std_attribute_table): Change type to scoped_attribute_specs, using... (std_attributes): ...this as the underlying array. (init_tree): Remove call to register_scoped_attributes. gcc/d/ * d-tree.h (d_langhook_attribute_table): Replace with... (d_langhook_gnu_attribute_table): ...this. (d_langhook_common_attribute_table): Change type to scoped_attribute_specs. * d-attribs.cc (d_langhook_common_attribute_table): Change type to scoped_attribute_specs, using... (d_langhook_common_attributes): ...this as the underlying array. (d_langhook_attribute_table): Replace with... (d_langhook_gnu_attributes, d_langhook_gnu_attribute_table): ...these new globals. (uda_attribute_p): Update accordingly, and update for new targetm.attribute_table type. * d-lang.cc (d_langhook_attribute_table): New global. (LANG_HOOKS_COMMON_ATTRIBUTE_TABLE): Delete. gcc/fortran/ * f95-lang.cc: Include attribs.h. (gfc_attribute_table): Change to an array of scoped_attribute_specs pointers, using... (gfc_gnu_attributes, gfc_gnu_attribute_table): ...these new globals. gcc/jit/ * dummy-frontend.cc (jit_format_attribute_table): Change type to scoped_attribute_specs, using... (jit_format_attributes): ...this as the underlying array. (jit_attribute_table): Change to an array of scoped_attribute_specs pointers, using... (jit_gnu_attributes, jit_gnu_attribute_table): ...these new globals for the original array. Include the format attributes. (LANG_HOOKS_COMMON_ATTRIBUTE_TABLE): Delete. (LANG_HOOKS_FORMAT_ATTRIBUTE_TABLE): Delete. (LANG_HOOKS_ATTRIBUTE_TABLE): Define. gcc/lto/ * lto-lang.cc (lto_format_attribute_table): Change type to scoped_attribute_specs, using... (lto_format_attributes): ...this as the underlying array. (lto_attribute_table): Change to an array of scoped_attribute_specs pointers, using... (lto_gnu_attributes, lto_gnu_attribute_table): ...these new globals for the original array. Include the format attributes. (LANG_HOOKS_COMMON_ATTRIBUTE_TABLE): Delete. (LANG_HOOKS_FORMAT_ATTRIBUTE_TABLE): Delete. (LANG_HOOKS_ATTRIBUTE_TABLE): Define.
2023-11-19[committed] Fix missing mode on a few unspec/unspec_volatile operandsJeff Law1-1/+1
This is fix for a minor problem Jivan and I found while testing the ext-dce work originally from Joern. The ext-dce pass will transform zero/sign extensions into subreg accesses when the upper bits are actually unused. So it's more likely with the ext-dce work to get a sequence like this prior to combine: > >> (insn 10 9 11 2 (set (reg:SI 144) >> (unspec_volatile [ >> (const_int 0 [0]) >> ] UNSPECV_FRFLAGS)) "j.c":11:3 discrim 1 362 {riscv_frflags} >> (nil)) >> (insn 11 10 55 2 (set (reg:DI 140 [ _12 ]) >> (subreg:DI (reg:SI 144) 0)) "j.c":11:3 discrim 1 206 {*movdi_64bit} >> (expr_list:REG_DEAD (reg:SI 144) >> (nil))) When we try to combine insn 10->11 we'll ultimately call simplify_subreg with something like (subreg:DI (unspec_volatile [...]) 0) Note the lack of a mode on the unspec_volatile. That in turn will cause simplify_subreg to trigger an assertion. The modeless unspec is generated by the RISC-V backend and the more I've pondered this issue over the last few days the more I'm convinced it's a backend bug. Basically if the LHS of the set has a mode, then the RHS of the set should have a mode as well. I've audited the various backends and only found a few problems which are fixed by this patch. I've tested the relevant ports in my tester. c6x, sh, mips and s390[x]. There are other patterns that are potentially problematical in various ports. They have a REG destination and an UNSPEC source, but the REG has no mode in the pattern. Since it wasn't clear what mode to give the UNSPEC, I left those alone. gcc/ * config/c6x/c6x.md (mvilc): Add mode to UNSPEC source. * config/mips/mips.md (rdhwr_synci_step_<mode>): Likewise. * config/riscv/riscv.md (riscv_frcsr, riscv_frflags): Likewise. * config/s390/s390.md (@split_stack_call<mode>): Likewise. (@split_stack_cond_call<mode>): Likewise. * config/sh/sh.md (sp_switch_1): Likewise.
2023-11-09MIPS: Use -mnan value for -mabs if not specifiedYunQiang Su1-0/+2
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008. Let's use this behaivor by default in GCC, aka gcc -mnan=2008 -c fabs.c will imply `-mabs=2008`. And of course, `gcc -mnan=2008 -mabs=legacy` can continue workable like previous. gcc/ChangeLog * config/mips/mips.cc(mips_option_override): Set mips_abs to 2008, if mips_abs is default and mips_nan is 2008. gcc/testsuite/ * gcc.target/mips/fabs-nan2008.c: New test. * gcc.target/mips/fabsf-nan2008.c: New test.
2023-08-09targhooks: Extend legitimate_address_p with code_helper [PR110248]Kewen Lin1-1/+2
As PR110248 shows, some middle-end passes like IVOPTs can query the target hook legitimate_address_p with some artificially constructed rtx to determine whether some addressing modes are supported by target for some gimple statement. But for now the existing legitimate_address_p only checks the given mode, it's unable to distinguish some special cases unfortunately, for example, for LEN_LOAD ifn on Power port, we would expand it with lxvl hardware insn, which only supports one register to hold the address (the other register is holding the length), that is we don't support base (reg) + index (reg) addressing mode for sure. But hook legitimate_address_p only considers the given mode which would be some vector mode for LEN_LOAD ifn, and we do support base + index addressing mode for normal vector load and store insns, so the hook will return true for the query unexpectedly. This patch is to introduce one extra argument of type code_helper for hook legitimate_address_p, it makes targets able to handle some special case like what's described above. PR tree-optimization/110248 gcc/ChangeLog: * coretypes.h (class code_helper): Add forward declaration. * doc/tm.texi: Regenerate. * lra-constraints.cc (valid_address_p): Call target hook targetm.addr_space.legitimate_address_p with an extra parameter ERROR_MARK as its prototype changes. * recog.cc (memory_address_addr_space_p): Likewise. * reload.cc (strict_memory_address_addr_space_p): Likewise. * target.def (legitimate_address_p, addr_space.legitimate_address_p): Extend with one more argument of type code_helper, update the documentation accordingly. * targhooks.cc (default_legitimate_address_p): Adjust for the new code_helper argument. (default_addr_space_legitimate_address_p): Likewise. * targhooks.h (default_legitimate_address_p): Likewise. (default_addr_space_legitimate_address_p): Likewise. * config/aarch64/aarch64.cc (aarch64_legitimate_address_hook_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/alpha/alpha.cc (alpha_legitimate_address_p): Likewise. * config/arc/arc.cc (arc_legitimate_address_p): Likewise. * config/arm/arm-protos.h (arm_legitimate_address_p): Likewise. (tree.h): New include for tree_code ERROR_MARK. * config/arm/arm.cc (arm_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/avr/avr.cc (avr_addr_space_legitimate_address_p): Likewise. * config/bfin/bfin.cc (bfin_legitimate_address_p): Likewise. * config/bpf/bpf.cc (bpf_legitimate_address_p): Likewise. * config/c6x/c6x.cc (c6x_legitimate_address_p): Likewise. * config/cris/cris-protos.h (cris_legitimate_address_p): Likewise. (tree.h): New include for tree_code ERROR_MARK. * config/cris/cris.cc (cris_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/csky/csky.cc (csky_legitimate_address_p): Likewise. * config/epiphany/epiphany.cc (epiphany_legitimate_address_p): Likewise. * config/frv/frv.cc (frv_legitimate_address_p): Likewise. * config/ft32/ft32.cc (ft32_addr_space_legitimate_address_p): Likewise. * config/gcn/gcn.cc (gcn_addr_space_legitimate_address_p): Likewise. * config/h8300/h8300.cc (h8300_legitimate_address_p): Likewise. * config/i386/i386.cc (ix86_legitimate_address_p): Likewise. * config/ia64/ia64.cc (ia64_legitimate_address_p): Likewise. * config/iq2000/iq2000.cc (iq2000_legitimate_address_p): Likewise. * config/lm32/lm32.cc (lm32_legitimate_address_p): Likewise. * config/loongarch/loongarch.cc (loongarch_legitimate_address_p): Likewise. * config/m32c/m32c.cc (m32c_legitimate_address_p): Likewise. (m32c_addr_space_legitimate_address_p): Likewise. * config/m32r/m32r.cc (m32r_legitimate_address_p): Likewise. * config/m68k/m68k.cc (m68k_legitimate_address_p): Likewise. * config/mcore/mcore.cc (mcore_legitimate_address_p): Likewise. * config/microblaze/microblaze-protos.h (tree.h): New include for tree_code ERROR_MARK. (microblaze_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/microblaze/microblaze.cc (microblaze_legitimate_address_p): Likewise. * config/mips/mips.cc (mips_legitimate_address_p): Likewise. * config/mmix/mmix.cc (mmix_legitimate_address_p): Likewise. * config/mn10300/mn10300.cc (mn10300_legitimate_address_p): Likewise. * config/moxie/moxie.cc (moxie_legitimate_address_p): Likewise. * config/msp430/msp430.cc (msp430_legitimate_address_p): Likewise. (msp430_addr_space_legitimate_address_p): Adjust with extra code_helper argument with default ERROR_MARK and adjust the call to function msp430_legitimate_address_p. * config/nds32/nds32.cc (nds32_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/nios2/nios2.cc (nios2_legitimate_address_p): Likewise. * config/nvptx/nvptx.cc (nvptx_legitimate_address_p): Likewise. * config/or1k/or1k.cc (or1k_legitimate_address_p): Likewise. * config/pa/pa.cc (pa_legitimate_address_p): Likewise. * config/pdp11/pdp11.cc (pdp11_legitimate_address_p): Likewise. * config/pru/pru.cc (pru_addr_space_legitimate_address_p): Likewise. * config/riscv/riscv.cc (riscv_legitimate_address_p): Likewise. * config/rl78/rl78-protos.h (rl78_as_legitimate_address): Likewise. (tree.h): New include for tree_code ERROR_MARK. * config/rl78/rl78.cc (rl78_as_legitimate_address): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/rs6000/rs6000.cc (rs6000_legitimate_address_p): Likewise. (rs6000_debug_legitimate_address_p): Adjust with extra code_helper argument and adjust the call to function rs6000_legitimate_address_p. * config/rx/rx.cc (rx_is_legitimate_address): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/s390/s390.cc (s390_legitimate_address_p): Likewise. * config/sh/sh.cc (sh_legitimate_address_p): Likewise. * config/sparc/sparc.cc (sparc_legitimate_address_p): Likewise. * config/v850/v850.cc (v850_legitimate_address_p): Likewise. * config/vax/vax.cc (vax_legitimate_address_p): Likewise. * config/visium/visium.cc (visium_legitimate_address_p): Likewise. * config/xtensa/xtensa.cc (xtensa_legitimate_address_p): Likewise. * config/stormy16/stormy16-protos.h (xstormy16_legitimate_address_p): Likewise. (tree.h): New include for tree_code ERROR_MARK. * config/stormy16/stormy16.cc (xstormy16_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK.
2023-07-05MIPS: Use unaligned access to expand block_move on r6YunQiang Su1-17/+19
MIPSr6 support unaligned memory access with normal lh/sh/lw/sw/ld/sd instructions, and thus lwl/lwr/ldl/ldr and swl/swr/sdl/sdr is removed. For microarchitecture, these memory access instructions issue 2 operation if the address is not aligned, which is like what lwl family do. For some situation (such as accessing boundary of pages) on some microarchitectures, the unaligned access may not be good enough, then the kernel should trap&emu it: the kernel may need -mno-unalgined-access option. gcc/ * config/mips/mips.cc (mips_expand_block_move): don't expand for r6 with -mno-unaligned-access option if one or both of src and dest are unaligned. restruct: return directly if length is not const. (mips_block_move_straight): emit_move if ISA_HAS_UNALIGNED_ACCESS. gcc/testsuite/ * gcc.target/mips/expand-block-move-r6-no-unaligned.c: new test. * gcc.target/mips/expand-block-move-r6.c: new test.
2023-07-03MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditionsJie Mei1-13/+17
This patch allows mips16e2 acts the same with -O1~3 when generating ZEB/ZEH instead of ANDI under the -O0 option, which shrinks the code size. gcc/ChangeLog: * config/mips/mips.md(*and<mode>3_mips16): Generates ZEB/ZEH instructions.
2023-07-03MIPS: Add CACHE instruction for mips16e2Jie Mei3-5/+26
This patch adds CACHE instruction from mips16e2 with corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_9bit_offset_address_p): Restrict the address register to M16_REGS for MIPS16. (BUILTIN_AVAIL_MIPS16E2): Defined a new macro. (AVAIL_MIPS16E2_OR_NON_MIPS16): Same as above. (AVAIL_NON_MIPS16 (cache..)): Update to AVAIL_MIPS16E2_OR_NON_MIPS16. * config/mips/mips.h (ISA_HAS_CACHE): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md (mips_cache): Mark as extended MIPS16. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-cache.c: New tests for mips16e2.
2023-07-03MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2Jie Mei1-3/+6
The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above. (ISA_HAS_LL_SC): Same as above.
2023-07-03MIPS: Add load/store word left/right instructions for mips16e2Jie Mei3-8/+53
This patch adds LWL/LWR, SWL/SWR instructions with their corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_expand_ins_as_unaligned_store): Add logics for generating instruction. * config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md(mov_<load>l): Generates instructions. (mov_<load>r): Same as above. (mov_<store>l): Adjusted for the conditions above. (mov_<store>r): Same as above. (mov_<store>l_mips16e2): Add machine description for `define_insn mov_<store>l_mips16e2`. (mov_<store>r_mips16e2): Add machine description for `define_insn mov_<store>r_mips16e2`. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: New tests for mips16e2.
2023-07-03MIPS: Add LUI instruction for mips16e2Jie Mei2-12/+34
This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue): Same as above. * config/mips/mips.md: Same as above gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: Add new tests for mips16e2.
2023-07-03MIPS: Add bitwise instructions for mips16e2Jie Mei6-21/+161
There are shortened bitwise instructions in the mips16e2 ASE, for instance, ANDI, ORI/XORI, EXT, INS etc. . This patch adds these instrutions with corresponding tests. gcc/ChangeLog: * config/mips/constraints.md(Yz): New constraints for mips16e2. * config/mips/mips-protos.h(mips_bit_clear_p): Declared new function. (mips_bit_clear_info): Same as above. * config/mips/mips.cc(mips_bit_clear_info): New function for generating instructions. (mips_bit_clear_p): Same as above. * config/mips/mips.h(ISA_HAS_EXT_INS): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md(extended_mips16): Generates EXT and INS instructions. (*and<mode>3): Generates INS instruction. (*and<mode>3_mips16): Generates EXT, INS and ANDI instructions. (ior<mode>3): Add logics for ORI instruction. (*ior<mode>3_mips16_asmacro): Generates ORI instrucion. (*ior<mode>3_mips16): Add logics for XORI instruction. (*xor<mode>3_mips16): Generates XORI instrucion. (*extzv<mode>): Add logics for EXT instruction. (*insv<mode>): Add logics for INS instruction. * config/mips/predicates.md(bit_clear_operand): New predicate for generating bitwise instructions. (and_reg_operand): Add logics for generating bitwise instructions. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: New tests for mips16e2.
2023-07-03MIPS: Add instruction about global pointer register for mips16e2Jie Mei3-7/+20
The mips16e2 ASE uses eight general-purpose registers from mips32, with some special-purpose registers, these registers are GPRs: s0-1, v0-1, a0-3, and special registers: t8, gp, sp, ra. As mentioned above, the special register gp is used in mips16e2, which is the global pointer register, it is used by some of the instructions in the ASE, for instance, ADDIU, LB/LBU, etc. . This patch adds these instructions with corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_regno_mode_ok_for_base_p): Generate instructions that uses global pointer register. (mips16_unextended_reference_p): Same as above. (mips_pic_base_register): Same as above. (mips_init_relocs): Same as above. * config/mips/mips.h(MIPS16_GP_LOADS): Defined a new macro. (GLOBAL_POINTER_REGNUM): Moved to machine description `mips.md`. * config/mips/mips.md(GLOBAL_POINTER_REGNUM): Moved to here from above. (*lowsi_mips16_gp):New `define_insn *low<mode>_mips16`. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-gp.c: New tests for mips16e2.
2023-07-03MIPS: Add MOVx instructions support for mips16e2Jie Mei3-2/+43
This patch adds MOVx instructions from mips16e2 (movn,movz,movtn,movtz) with corresponding tests. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2. * config/mips/mips.md(*mov<GPR:mode>_on_<MOVECC:mode>): Add logics for MOVx insts. (*mov<GPR:mode>_on_<MOVECC:mode>_mips16e2): Generate MOVx instruction. (*mov<GPR:mode>_on_<GPR2:mode>_ne): Add logics for MOVx insts. (*mov<GPR:mode>_on_<GPR2:mode>_ne_mips16e2): Generate MOVx instruction. * config/mips/predicates.md(reg_or_0_operand_mips16e2): New predicate for MOVx insts. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-cmov.c: Added tests for MOVx instructions.
2023-07-03MIPS: Add basic support for mips16e2Jie Mei4-2/+15
The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. It defines new special instructions for increasing code density (e.g. Extend, PC-relative instructions, etc.). This patch adds basic support for mips16e2 used by the following series of patches. gcc/ChangeLog: * config/mips/mips.cc(mips_file_start): Add mips16e2 info for output file. * config/mips/mips.h(__mips_mips16e2): Defined a new predefine macro. (ISA_HAS_MIPS16E2): Defined a new macro. (ASM_SPEC): Pass mmips16e2 to the assembler. * config/mips/mips.opt: Add -m(no-)mips16e2 option. * config/mips/predicates.md: Add clause for TARGET_MIPS16E2. * doc/invoke.texi: Add -m(no-)mips16e2 option.. gcc/testsuite/ChangeLog: * gcc.target/mips/mips.exp(mips_option_groups): Add -mmips16e2 option. (mips-dg-init): Handle the recognization of mips16e2 targets. (mips-dg-options): Add dependencies for mips16e2.
2023-06-30mips: Fix overaligned function arguments [PR109435]Jovan Dmitrovic1-1/+18
This patch changes alignment for typedef types when passed as arguments, making the alignment equal to the alignment of original (aliased) types. This change makes it impossible for a typedef type to have alignment that is less than its size. 2023-06-27 Jovan Dmitrović <jovan.dmitrovic@syrmia.com> gcc/ChangeLog: PR target/109435 * config/mips/mips.cc (mips_function_arg_alignment): Returns the alignment of function argument. In case of typedef type, it returns the aligment of the aliased type. (mips_function_arg_boundary): Relocated calculation of the aligment of function arguments. gcc/testsuite/ChangeLog: * gcc.target/mips/align-1-n64.c: New test. * gcc.target/mips/align-1-o32.c: New test.
2023-06-16MIPS16: Implement `code_readable` function attribute.Simon Dardis1-1/+96
Support for __attribute__ ((code_readable)). Takes up to one argument of "yes", "no", "pcrel". This will change the code readability setting for just that function. If no argument is supplied, then the setting is 'yes'. gcc/ChangeLog: * config/mips/mips.cc (enum mips_code_readable_setting):New enmu. (mips_handle_code_readable_attr):New static function. (mips_get_code_readable_attr):New static enum function. (mips_set_current_function):Set the code_readable mode. (mips_option_override):Same as above. * doc/extend.texi:Document code_readable. gcc/testsuite/ChangeLog: * gcc.target/mips/code-readable-attr-1.c: New test. * gcc.target/mips/code-readable-attr-2.c: New test. * gcc.target/mips/code-readable-attr-3.c: New test. * gcc.target/mips/code-readable-attr-4.c: New test. * gcc.target/mips/code-readable-attr-5.c: New test.
2023-06-05MIPS: Add speculation_barrier supportYunQiang Su3-0/+26
speculation_barrier for MIPS needs sync+jr.hb (r2+), so we implement __speculation_barrier in libgcc, like arm32 does. gcc/ChangeLog: * config/mips/mips-protos.h (mips_emit_speculation_barrier): New prototype. * config/mips/mips.cc (speculation_barrier_libfunc): New static variable. (mips_init_libfuncs): Initialize it. (mips_emit_speculation_barrier): New function. * config/mips/mips.md (speculation_barrier): Call mips_emit_speculation_barrier. libgcc/ChangeLog: * config/mips/lib1funcs.S: New file. define __speculation_barrier and include mips16.S. * config/mips/t-mips: define LIB1ASMSRC as mips/lib1funcs.S. define LIB1ASMFUNCS as _speculation_barrier. set version info for __speculation_barrier. * config/mips/libgcc-mips.ver: New file. * config/mips/t-mips16: don't define LIB1ASMSRC as mips16.S included in lib1funcs.S now.
2023-05-18gcc/config/*: use _P() defines from tree.hBernhard Reutner-Fischer1-1/+1
gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_short_vector_p): Use _P defines from tree.h. (aarch64_mangle_type): Ditto. * config/alpha/alpha.cc (alpha_in_small_data_p): Ditto. (alpha_gimplify_va_arg_1): Ditto. * config/arc/arc.cc (arc_encode_section_info): Ditto. (arc_is_aux_reg_p): Ditto. (arc_is_uncached_mem_p): Ditto. (arc_handle_aux_attribute): Ditto. * config/arm/arm.cc (arm_handle_isr_attribute): Ditto. (arm_handle_cmse_nonsecure_call): Ditto. (arm_set_default_type_attributes): Ditto. (arm_is_segment_info_known): Ditto. (arm_mangle_type): Ditto. * config/arm/unknown-elf.h (IN_NAMED_SECTION_P): Ditto. * config/avr/avr.cc (avr_lookup_function_attribute1): Ditto. (avr_decl_absdata_p): Ditto. (avr_insert_attributes): Ditto. (avr_section_type_flags): Ditto. (avr_encode_section_info): Ditto. * config/bfin/bfin.cc (bfin_handle_l2_attribute): Ditto. * config/bpf/bpf.cc (bpf_core_compute): Ditto. * config/c6x/c6x.cc (c6x_in_small_data_p): Ditto. * config/csky/csky.cc (csky_handle_isr_attribute): Ditto. (csky_mangle_type): Ditto. * config/darwin-c.cc (darwin_pragma_unused): Ditto. * config/darwin.cc (is_objc_metadata): Ditto. * config/epiphany/epiphany.cc (epiphany_function_ok_for_sibcall): Ditto. * config/epiphany/epiphany.h (ROUND_TYPE_ALIGN): Ditto. * config/frv/frv.cc (frv_emit_movsi): Ditto. * config/gcn/gcn-tree.cc (gcn_lockless_update): Ditto. * config/gcn/gcn.cc (gcn_asm_output_symbol_ref): Ditto. * config/h8300/h8300.cc (h8300_encode_section_info): Ditto. * config/i386/i386-expand.cc: Ditto. * config/i386/i386.cc (type_natural_mode): Ditto. (ix86_function_arg): Ditto. (ix86_data_alignment): Ditto. (ix86_local_alignment): Ditto. (ix86_simd_clone_compute_vecsize_and_simdlen): Ditto. * config/i386/winnt-cxx.cc (i386_pe_type_dllimport_p): Ditto. (i386_pe_type_dllexport_p): Ditto. (i386_pe_adjust_class_at_definition): Ditto. * config/i386/winnt.cc (i386_pe_determine_dllimport_p): Ditto. (i386_pe_binds_local_p): Ditto. (i386_pe_section_type_flags): Ditto. * config/ia64/ia64.cc (ia64_encode_section_info): Ditto. (ia64_gimplify_va_arg): Ditto. (ia64_in_small_data_p): Ditto. * config/iq2000/iq2000.cc (iq2000_function_arg): Ditto. * config/lm32/lm32.cc (lm32_in_small_data_p): Ditto. * config/loongarch/loongarch.cc (loongarch_handle_model_attribute): Ditto. * config/m32c/m32c.cc (m32c_insert_attributes): Ditto. * config/mcore/mcore.cc (mcore_mark_dllimport): Ditto. (mcore_encode_section_info): Ditto. * config/microblaze/microblaze.cc (microblaze_elf_in_small_data_p): Ditto. * config/mips/mips.cc (mips_output_aligned_decl_common): Ditto. * config/mmix/mmix.cc (mmix_encode_section_info): Ditto. * config/nvptx/nvptx.cc (nvptx_encode_section_info): Ditto. (pass_in_memory): Ditto. (nvptx_generate_vector_shuffle): Ditto. (nvptx_lockless_update): Ditto. * config/pa/pa.cc (pa_function_arg_padding): Ditto. (pa_function_value): Ditto. (pa_function_arg): Ditto. * config/pa/pa.h (IN_NAMED_SECTION_P): Ditto. (TEXT_SPACE_P): Ditto. * config/pa/som.h (MAKE_DECL_ONE_ONLY): Ditto. * config/pdp11/pdp11.cc (pdp11_return_in_memory): Ditto. * config/riscv/riscv.cc (riscv_in_small_data_p): Ditto. (riscv_mangle_type): Ditto. * config/rl78/rl78.cc (rl78_insert_attributes): Ditto. (rl78_addsi3_internal): Ditto. * config/rs6000/aix.h (ROUND_TYPE_ALIGN): Ditto. * config/rs6000/darwin.h (ROUND_TYPE_ALIGN): Ditto. * config/rs6000/freebsd64.h (ROUND_TYPE_ALIGN): Ditto. * config/rs6000/linux64.h (ROUND_TYPE_ALIGN): Ditto. * config/rs6000/rs6000-call.cc (rs6000_function_arg_boundary): Ditto. (rs6000_function_arg_advance_1): Ditto. (rs6000_function_arg): Ditto. (rs6000_pass_by_reference): Ditto. * config/rs6000/rs6000-logue.cc (rs6000_function_ok_for_sibcall): Ditto. * config/rs6000/rs6000.cc (rs6000_data_alignment): Ditto. (rs6000_set_default_type_attributes): Ditto. (rs6000_elf_in_small_data_p): Ditto. (IN_NAMED_SECTION): Ditto. (rs6000_xcoff_encode_section_info): Ditto. (rs6000_function_value): Ditto. (invalid_arg_for_unprototyped_fn): Ditto. * config/s390/s390-c.cc (s390_fn_types_compatible): Ditto. (s390_vec_n_elem): Ditto. * config/s390/s390.cc (s390_check_type_for_vector_abi): Ditto. (s390_function_arg_integer): Ditto. (s390_return_in_memory): Ditto. (s390_encode_section_info): Ditto. * config/sh/sh.cc (sh_gimplify_va_arg_expr): Ditto. (sh_function_value): Ditto. * config/sol2.cc (solaris_insert_attributes): Ditto. * config/sparc/sparc.cc (function_arg_slotno): Ditto. * config/sparc/sparc.h (ROUND_TYPE_ALIGN): Ditto. * config/stormy16/stormy16.cc (xstormy16_encode_section_info): Ditto. (xstormy16_handle_below100_attribute): Ditto. * config/v850/v850.cc (v850_encode_section_info): Ditto. (v850_insert_attributes): Ditto. * config/visium/visium.cc (visium_pass_by_reference): Ditto. (visium_return_in_memory): Ditto. * config/xtensa/xtensa.cc (xtensa_multibss_section_type_flags): Ditto.
2023-03-02MIPS: Bugfix for fix Dejagnu issues with RTL checking enabled.Robert Suchanek2-3/+3
gcc/ChangeLog: * config/mips/mips.cc (mips_set_text_contents_type): Use HOST_WIDE_INT instead of long. * config/mips/mips-protos.h (mips_set_text_contents_type): Likewise. Signed-off-by: Xin Liu <xin.liu@oss.cipunited.com>
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