Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2022-09-28 | LoongArch: Use UNSPEC for fmin/fmax RTL pattern [PR105414] | Xi Ruoyao | 1 | -4/+8 |
2022-08-24 | LoongArch: Add new code model 'medium'. | Lulu Cheng | 1 | -6/+119 |
2022-08-20 | LoongArch: Add support code model extreme. | Lulu Cheng | 1 | -1/+33 |
2022-08-17 | LoongArch: Provide fmin/fmax RTL pattern | Xi Ruoyao | 1 | -0/+18 |
2022-07-26 | LoongArch: Support split symbol. | Lulu Cheng | 1 | -67/+55 |
2022-07-26 | LoongArch: Subdivision symbol type, add SYMBOL_PCREL support. | Lulu Cheng | 1 | -243/+36 |
2022-07-10 | loongarch: avoid unnecessary sign-extend after 32-bit division | Xi Ruoyao | 1 | -4/+8 |
2022-07-10 | loongarch: add alternatives for idiv insns to improve code generation | Xi Ruoyao | 1 | -8/+20 |
2022-07-10 | loongarch: fix mulsidi3_64bit instruction | Xi Ruoyao | 1 | -1/+1 |
2022-04-27 | LoongArch: Add fdiv define_expand template. | Lulu Cheng | 1 | -0/+6 |
2022-04-27 | LoongArch: Add '(clobber (mem:BLK (scratch)))' to PLV instruction templates. | Lulu Cheng | 1 | -12/+28 |
2022-03-29 | LoongArch Port: Machine description files. | chenglulu | 1 | -0/+3393 |