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2021-11-08Fix couple of issues in large PIC model on x86-64/VxWorksEric Botcazou2-5/+17
2021-11-05x86: Make stringop_algs::stringop_strategy ctor constexpr [PR100246]Jakub Jelinek1-2/+3
2021-11-04vect: Convert cost hooks to classesRichard Sandiford1-53/+23
2021-11-04Extend vternlog define_insn_and_split to memory_operand to enable more optimz...liuhongt2-15/+32
2021-11-04i386: Auto vectorize sdot_prod, usdot_prod with VNNI instruction.Hongyu Wang1-8/+56
2021-11-04i386: Fix wrong result for AMX-TILE intrinsic when parsing expression.Hongyu Wang1-3/+3
2021-11-02x86_64: Improved implementation of TImode rotations.Roger Sayle1-2/+18
2021-11-02ia32: Disallow mode(V1TI) [PR103020]Jakub Jelinek1-0/+4
2021-11-02x86_64: Expand ashrv1ti (and PR target/102986)Roger Sayle3-13/+543
2021-10-29Enable vectorization for _Float16 floor/ceil/trunc/nearbyint/rint operations.liuhongt5-6/+69
2021-10-28AVX512FP16: Optimize _Float16 reciprocal for div and sqrtHongyu Wang3-19/+117
2021-10-26x86_64: Implement V1TI mode shifts/rotates by a constantRoger Sayle3-0/+209
2021-10-25Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A) and combine FADD(A, FMUL(B,...konglin11-0/+52
2021-10-23config/i386: Commentary typo fixBernhard Reutner-Fischer1-1/+1
2021-10-23x86_64: Add insn patterns for V1TI mode logic operations.Roger Sayle1-0/+25
2021-10-21i386: Fix wrong codegen for V8HF move without TARGET_AVX512FHongyu Wang1-3/+12
2021-10-20Revert "target: support spaces in target attribute."Martin Liska1-2/+0
2021-10-20Rename asm_out_file function arguments.Martin Liska2-12/+12
2021-10-19target: support spaces in target attribute.Martin Liska1-0/+2
2021-10-19AVX512FP16: Add *_set1_pch intrinsics.dianhong xu2-0/+39
2021-10-18i386: Fix ICE in ix86_print_opreand_address [PR 102761]Uros Bizjak1-1/+4
2021-10-18Try placing RTL folded constants in the constant pool.Roger Sayle1-0/+7
2021-10-15Darwin: Revise handling of some driver opts.Iain Sandoe1-4/+5
2021-10-15Allow early sets of SSE hard registers from standard_sse_constant_p.Roger Sayle1-1/+3
2021-10-15AVX512FP16: Enhance vector shuffle builtinsHongyu Wang2-1/+77
2021-10-15AVX512FP16: Fix ICE for 2 v4hf vector concatHongyu Wang1-1/+2
2021-10-14AVX512FP16: Adjust builtin for mask complex fmaHongyu Wang6-216/+333
2021-10-13x86_64: Some SUBREG related optimization tweaks to i386 backend.Roger Sayle2-3/+18
2021-10-12i386: Improve workaround for PR82524 LRA limitation [PR85730]Uros Bizjak1-55/+147
2021-10-12Support reduc_{plus,smax,smin,umax,umin}_scal_v4qi.liuhongt2-0/+50
2021-10-09Refine movhfcc.liuhongt3-6/+48
2021-10-08Come up with OPTION_SET_P macro.Martin Liska2-4/+4
2021-10-08Simplify (_Float16) ceil ((double) x) to .CEIL (x) when available.liuhongt1-8/+12
2021-10-08Support reduc_{plus,smax,smin,umax,min}_scal_v4hi.liuhongt2-0/+41
2021-10-01Fix PR c++/64697 at -O1 or aboveEric Botcazou1-13/+8
2021-09-30i386: Eliminate sign extension after logic operation [PR89954]Uros Bizjak1-0/+34
2021-09-28i386: Don't emit fldpi etc. if -frounding-math [PR102498]Jakub Jelinek1-1/+2
2021-09-28AVX512FP16: Support basic 64/32bit vector type and operation.Hongyu Wang4-15/+59
2021-09-28Support 128/256/512-bit vector plus/smin/smax reduction for _Float16.liuhongt2-2/+11
2021-09-27Revert "Optimize v4sf reduction.".liuhongt1-28/+11
2021-09-24AVX512FP16: Support cond_op for HFmodeHongyu Wang1-56/+56
2021-09-23AVX512FP16: Enable vec_cmpmn/vcondmn expanders for HF modes.Hongyu Wang2-12/+74
2021-09-23AVX512FP16: add truncmn2/extendmn2 expandersHongyu Wang1-7/+68
2021-09-23AVX512FP16: Add float(uns)?mn2 expanderHongyu Wang1-8/+38
2021-09-23AVX512FP16: Add fix(uns)?_truncmn2 for HF scalar and vector modesHongyu Wang2-0/+72
2021-09-23AVX512FP16: Add expander for smin/maxhf3.Hongyu Wang1-0/+11
2021-09-23AVX512FP16: Add expander for fmahf4liuhongt1-5/+6
2021-09-23AVX512FP16: Add expander for rint/nearbyinthf2.liuhongt1-0/+22
2021-09-22AVX512FP16: Add permutation and mask blend intrinsics.dianhong xu2-0/+93
2021-09-22AVX512FP16: Add complex conjugation intrinsic instructions.dianhong xu2-0/+80