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2019-08-20Use function_arg_info for TARGET_MUST_PASS_IN_STACKRichard Sandiford1-8/+12
2019-08-20Use function_arg_info for TARGET_FUNCTION_ARG_ADVANCERichard Sandiford1-15/+11
2019-08-20Use function_arg_info for TARGET_FUNCTION_(INCOMING_)ARGRichard Sandiford1-29/+21
2019-08-20Use function_arg_info for TARGET_SETUP_INCOMING_ARGSRichard Sandiford1-4/+5
2019-08-20Use function_arg_info for TARGET_PASS_BY_REFERENCERichard Sandiford1-5/+4
2019-08-20Add pass_va_arg_by_referenceRichard Sandiford1-1/+1
2019-08-20re PR target/91498 (STV change in r274481 causes 300.twolf regression on Hasw...Richard Biener1-7/+9
2019-08-20Add TIGERLAKE and COOPERLAKE to GCC.Hongtao Liu5-30/+84
2019-08-16mmx.md (mmxdoublemode): New mode attribute.Uros Bizjak2-37/+41
2019-08-16re PR target/91469 (ICE in extract_insn, at recog.c:2310 since r274481)Richard Biener1-0/+4
2019-08-15i386: Separate costs of pseudo registers from hard registersH.J. Lu3-537/+819
2019-08-15Remove TARGET_SETUP_INCOMING_VARARG_BOUNDSRichard Sandiford1-31/+0
2019-08-15re PR target/91454 (ICE in get_attr_avx_partial_xmm_update, at config/i386/i3...Richard Biener1-14/+23
2019-08-15* config/i386/i386.c (convertible_comparison_p): Fix argument declaration.Uros Bizjak1-1/+1
2019-08-15i386-features.c (general_scalar_chain::convert_insn): Revert 2019-08-14 change.Uros Bizjak1-11/+15
2019-08-14i386-expand.c (ix86_expand_vector_init_one_nonzero): Use vector_set path for ...Uros Bizjak1-0/+5
2019-08-14re PR rtl-optimization/91154 (456.hmmer regression on Haswell caused by r272922)Richard Biener3-181/+384
2019-08-14re PR rtl-optimization/91154 (456.hmmer regression on Haswell caused by r272922)Richard Biener1-14/+22
2019-08-13Use checking forms of DECL_FUNCTION_CODE (PR 91421)Richard Sandiford3-8/+9
2019-08-13[Darwin] There is no need to distinguish PIC/non-PIC symbol stubs.Iain Sandoe3-5/+5
2019-08-13i386.md (ix86_expand_vector_extract): Use vec_extr path for TARGET_MMX_WITH_S...Uros Bizjak2-5/+63
2019-08-13i386.md (ix86_expand_vector_set): Use vec_merge path for TARGET_MMX_WITH_SSE ...Uros Bizjak2-1/+73
2019-08-12re PR target/83250 (_mm256_zextsi128_si256 missing for AVX2 zero extension)Jakub Jelinek2-0/+62
2019-08-10re PR target/91408 (ICE in extract_insn, at recog.c:2310 since r273981)Jakub Jelinek1-2/+2
2019-08-07re PR target/91385 (Zero-extended negation (*negsi2_1_zext) is not generated)Uros Bizjak1-15/+5
2019-08-05re PR target/91341 (Missing AVX Intrinsics: load/store u2)Jakub Jelinek1-0/+42
2019-08-02re PR tree-optimization/91201 (SIMD not generated for horizontal sum of bytes...Uros Bizjak1-0/+19
2019-08-02re PR target/91323 (LTGT rtx produces UCOMISS instead of COMISS)Uros Bizjak1-3/+3
2019-08-02re PR tree-optimization/91201 (SIMD not generated for horizontal sum of bytes...Jakub Jelinek1-0/+11
2019-08-01re PR tree-optimization/85693 (Generation of SAD (Sum of Absolute Difference)...Uros Bizjak1-0/+15
2019-08-01mmx.md (vec_extractv2si_0): Add (r,x) alternative.Uros Bizjak1-12/+70
2019-07-31re PR target/91050 (-mdejagnu-cpu=<cpu> does not affect the -m<cpu> assembler...Peter Bergner1-0/+6
2019-07-31re PR tree-optimization/91201 (SIMD not generated for horizontal sum of bytes...Jakub Jelinek1-0/+15
2019-07-31re PR tree-optimization/91201 (SIMD not generated for horizontal sum of bytes...Jakub Jelinek1-3/+24
2019-07-30re PR target/91150 (wrong code with -O -mavx512vbmi due to wrong writemask)Jakub Jelinek1-2/+3
2019-07-30i386.md (movstrict<mode>): Use register_operand predicate for operand 0.Uros Bizjak1-20/+18
2019-07-24[Darwin] Partial reversion of 273749.Iain Sandoe1-1/+28
2019-07-23[Darwin] Fix PR87030 add missed commit hunks.Iain Sandoe3-29/+30
2019-07-23[Darwin] Fix PR87030 and tidy config fragments.Iain Sandoe5-5/+37
2019-07-23i386-common.c: Use PROCESSOR_ZNVER2 scheduler for znver2.Jan Hubicka1-175/+404
2019-07-23i386-options.c (ix86_option_override_internal): Default PARAM_AVOID_FMA_MAX_B...Jan Hubicka1-1/+5
2019-07-23* config/i386/x86-tune.def (X86_TUNE_AVOID_256FMA_CHAINS): Set of ZNVER2.Jan Hubicka1-0/+4
2019-07-23x86-tune-costs.h (znver2_memcpy): Update.Jan Hubicka1-6/+6
2019-07-23x86/AVX512: improve generated code for mask-to-vector-register conversionsJan Beulich1-6/+10
2019-07-22x86/AVX512: improve generated code for bit-wise negation of vectors of integersJan Beulich1-1/+21
2019-07-19re PR target/91204 (ICE in expand_expr_real_2, at expr.c:9215 with -O3)Uros Bizjak1-0/+8
2019-07-18i386.md (*addqi_2_slp): Remove.Uros Bizjak1-28/+0
2019-07-18re PR target/91188 (strict_low_part operations do not work)Uros Bizjak1-98/+96
2019-07-17i386.md (*add<dwi>3_doubleword): Remove redundant constraints.Uros Bizjak1-55/+50
2019-07-17i386.md (*andqi_2_maybe_si): Handle potential partial reg stall on alternativ...Uros Bizjak1-2/+7
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