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AgeCommit message (Expand)AuthorFilesLines
2023-11-03i386: Handle multiple address register classesUros Bizjak1-14/+17
2023-11-02Support cmul{_conj}v4hf3/cmla{_conj}v4hf4 with AVX512FP16 instruction.liuhongt1-0/+86
2023-10-31Fix wrong code due to incorrect define_splitliuhongt1-78/+34
2023-10-27Support vec_cmpmn/vcondmn for v2hf/v4hf.liuhongt1-2/+267
2023-10-23Remove unused mmx_pinsrw.liuhongt1-14/+0
2023-10-18Support 32/64-bit vectorization for _Float16 fma related operations.liuhongt1-1/+151
2023-10-16Support 32/64-bit vectorization for conversion between _Float16 and integer/f...liuhongt1-19/+145
2023-10-16Enable vectorization for V2HF/V4HF rounding operations and sqrt.liuhongt1-1/+190
2023-10-11Refine predicate of operands[2] in divv4hf3 with register_operand.liuhongt1-1/+1
2023-10-08Support signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V2HF/V4HF.liuhongt1-1/+113
2023-10-08Support smin/smax for V2HF/V4HFliuhongt1-31/+43
2023-10-07[APX EGPR] Handle vex insns that only support GPR16 (5/5)Kong Lingling1-5/+6
2023-10-07[APX_EGPR] Handle legacy insns that only support GPR16 (4/5)Kong Lingling1-57/+86
2023-08-18i386: Use PUNPCKL?? to implement vector extend and zero_extend for TARGET_SSE2.Uros Bizjak1-3/+21
2023-08-10i386: Do not sanitize upper part of V2HFmode and V4HFmode reg with -fno-trapp...liuhongt1-6/+14
2023-08-08i386: Do not sanitize upper part of V2SFmode reg with -fno-trapping-math [PR1...Uros Bizjak1-32/+43
2023-08-07i386: Clear upper bits of XMM register for V4HFmode/V2HFmode operations [PR11...liuhongt1-19/+90
2023-08-07x86: drop redundant "prefix_data16" attributesJan Beulich1-10/+0
2023-08-07x86: correct "length_immediate" in a few casesJan Beulich1-2/+2
2023-08-07x86: replace/correct bogus "prefix_extra"Jan Beulich1-4/+4
2023-08-07x86: "sse4arg" adjustmentsJan Beulich1-20/+6
2023-07-26i386: Clear upper half of XMM register for V2SFmode operations [PR110762]Uros Bizjak1-403/+475
2023-06-19Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_...liuhongt1-15/+30
2023-06-03i386: Add missing vector truncate patterns [PR92658].liuhongt1-0/+21
2023-05-24i386: Add v<any_shift:insn>v4qi3 expanderUros Bizjak1-0/+24
2023-05-23i386: Add V8QI and V4QImode partial vector shift operationsUros Bizjak1-0/+22
2023-05-18i386: Add infrastructure for QImode partial vector mult and shift operationsUros Bizjak1-0/+20
2023-05-12i386: Remove mulv2si emulated sequence for TARGET_SSE2 [PR109797]Uros Bizjak1-33/+1
2023-05-10i386: Add missing vector extend patterns [PR92658]Uros Bizjak1-0/+62
2023-05-05i386: Introduce mulv2si3 instructionUros Bizjak1-0/+49
2023-04-18i386: Improve permutations with INSERTPS instruction [PR94908]Uros Bizjak1-0/+40
2023-03-15i386: Fix blend vector permutation for 8-byte modesUros Bizjak1-0/+19
2023-03-14i386: Use movss to implement V2SImode VEC_PERM.Uros Bizjak1-5/+5
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-12-07Fix ICE due to condition mismatch between expander and define_insn.liuhongt1-1/+2
2022-11-22Guard 64/32-bit vector move patterns with ix86_hard_reg_move_ok.liuhongt1-2/+4
2022-10-31Enable V4BFmode and V2BFmode.liuhongt1-10/+16
2022-09-22Fix typo in floorv2sf2, should be register_operand for op1, not vector_operand.liuhongt1-1/+1
2022-09-20Support 64-bit vectorization for single-precision floating rounding operation.liuhongt1-0/+154
2022-07-22Extend 16/32-bit vector bit_op patterns with (m,0,i) alternative.liuhongt1-31/+39
2022-07-03x86: Support 2/4/8 byte constant vector storesH.J. Lu1-0/+37
2022-06-03x86: {,v}psadbw have commutative source operandsJan Beulich1-4/+12
2022-05-30i386: Remove constraints when used with constant integer predicates, take 2Uros Bizjak1-10/+10
2022-05-17i386: Fix ICE in final_scan_insn_1 [PR105624]Uros Bizjak1-10/+10
2022-05-15i386: Remove constraints when used with constant integer predicates.Uros Bizjak1-10/+10
2022-04-05i386: Fix movv2qi_internal xmm reg to xmm reg move for AVX512FP16 [PR105139]Uros Bizjak1-1/+1
2022-01-17Change references of .c files to .cc filesMartin Liska1-4/+4
2022-01-13i386: Introduce V2QImode vectorized shifts [PR103861]Uros Bizjak1-4/+40
2022-01-13i386: Cleanup V2QI arithmetic instructionsUros Bizjak1-28/+28
2022-01-13ii386: Add 16-bit vector modes to xop_pcmov [PR104003]Uros Bizjak1-5/+5
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