aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/i386/i386-builtin.def
AgeCommit message (Expand)AuthorFilesLines
2024-02-25x86: Properly implement AMX-TILE load/store intrinsicsH.J. Lu1-0/+4
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-20i386: Allow 64 bit mask register for -mno-evex512Haochen Jiang1-14/+14
2023-11-24i386: Fix AVX512 and AVX10 option issuesHaochen Jiang1-4/+4
2023-10-31Fix incorrect option mask and avx512cd target pushHaochen Jiang1-2/+2
2023-10-09[PATCH 5/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtinsHaochen Jiang1-78/+78
2023-10-09[PATCH 4/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtinsHaochen Jiang1-94/+94
2023-10-09[PATCH 3/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtinsHaochen Jiang1-113/+113
2023-10-09[PATCH 2/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtinsHaochen Jiang1-47/+47
2023-10-09[PATCH 1/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtinsHaochen Jiang1-324/+324
2023-08-24Revert "Support AVX10.1 for AVX512DQ+AVX512VL intrins"Haochen Jiang1-23/+23
2023-08-24Revert "[Patch 3/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins"Haochen Jiang1-32/+32
2023-08-24Revert "[Patch 5/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins"Haochen Jiang1-16/+16
2023-08-17[Patch 5/6] Support AVX10.1 for AVX512DQ+AVX512VL intrinsHaochen Jiang1-16/+16
2023-08-17[Patch 3/6] Support AVX10.1 for AVX512DQ+AVX512VL intrinsHaochen Jiang1-32/+32
2023-08-17Support AVX10.1 for AVX512DQ+AVX512VL intrinsHaochen Jiang1-23/+23
2023-07-17Support Intel SM4Haochen Jiang1-0/+6
2023-07-17Support Intel SHA512Haochen Jiang1-0/+5
2023-07-17Support Intel SM3Haochen Jiang1-0/+5
2023-07-17Support Intel AVX-VNNI-INT16Kong Lingling1-0/+14
2023-06-09Fold _mm{,256,512}_abs_{epi8,epi16,epi32,epi64} into gimple ABSU_EXPR + VCE.liuhongt1-3/+3
2023-06-01PR target/109973: CCZmode and CCCmode variants of [v]ptest on x86.Roger Sayle1-4/+4
2023-05-24Fold _mm{,256,512}_abs_{epi8,epi16,epi32,epi64} into gimple ABS_EXPR.liuhongt1-9/+9
2023-04-20i386: Add AVX512BW dependency to AVX512VBMI2Haochen Jiang1-24/+24
2023-04-20i386: Add AVX512BW dependency to AVX512BITALGHaochen Jiang1-5/+5
2023-04-18i386: Improve permutations with INSERTPS instruction [PR94908]Uros Bizjak1-1/+1
2023-03-31Rename ufix_trunc/ufloat* patterns to fixuns_trunc/floatuns* to align with st...liuhongt1-20/+20
2023-03-15i386:Add missing OPTION_MASK_ISA_AVX512VL in i386-builtin.def for VAES builtinsHu, Lin11-4/+4
2023-02-24i386: Update i386-builtin.def file comment description of BDESC{,_FIRST}Jakub Jelinek1-2/+2
2023-02-24i386: Fix up builtins used in avx512bf16vlintrin.h [PR108881]Jakub Jelinek1-16/+16
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-12-25Use movss/movsd to implement V4SI/V2DI VEC_PERM on x86.Roger Sayle1-2/+2
2022-11-28Fix incorrect _mm_cvtsbh_ss.liuhongt1-0/+2
2022-11-11i386: Add ISA check for newly introduced prefetch builtins.Haochen Jiang1-1/+1
2022-11-07Support Intel RAO-INTkonglin11-0/+10
2022-11-07Support Intel prefetchit0/t1Haochen Jiang1-0/+4
2022-11-04Support Intel CMPccXADDHaochen Jiang1-0/+4
2022-10-31Support Intel AVX-NE-CONVERTkonglin11-2/+16
2022-10-31i386:: using __bf16 for AVX512BF16 intrinsicskonglin11-27/+27
2022-10-21Support Intel AVX-VNNI-INT8Kong Lingling1-0/+14
2022-10-21Support Intel AVX-IFMAHongyu Wang1-12/+16
2022-09-06Fix _mm512_cvt_roundps_ph to generate sae instruction.liuhongt1-1/+1
2022-08-26Don't gimple fold ymm-version vblendvpd/vblendvps/vpblendvb w/o TARGET_AVX2liuhongt1-2/+2
2022-07-15i386: Fix _mm_[u]comixx_{ss,sd} codegen and add PF result. [PR106113]konglin11-16/+16
2022-07-05UNSPEC_PALIGNR optimizations and clean-ups on x86.Roger Sayle1-1/+1
2022-06-07x86: harmonize __builtin_ia32_psadbw*() typesJan Beulich1-1/+1
2022-03-16Don't fold __builtin_ia32_blendvpd w/o sse4.2.liuhongt1-1/+1
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-10-29Enable vectorization for _Float16 floor/ceil/trunc/nearbyint/rint operations.liuhongt1-0/+11
2021-10-14AVX512FP16: Adjust builtin for mask complex fmaHongyu Wang1-8/+16
generated by cgit v1.1 at 2025-01-31 01:05:18 +0000