aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/aarch64
AgeCommit message (Expand)AuthorFilesLines
2025-01-22aarch64: Fix aarch64_write_sysregdi predicateRichard Sandiford1-1/+1
2025-01-21Regenerate aarch64.opt.urlsAlfie Richards1-0/+3
2025-01-21AArch64: Add LUTI ACLE for SVE2Vladimir Miloserdov9-1/+125
2025-01-21Add warning for non-spec compliant FMV in Aarch64Alfie Richards2-0/+13
2025-01-20aarch64: Fix invalid subregs in xorsign [PR118501]Richard Sandiford1-2/+2
2025-01-20aarch64: Add missing simd requirements for INS [PR118531]Richard Sandiford1-3/+6
2025-01-18AArch64: Use standard names for saturating arithmeticAkram Ahmad5-56/+271
2025-01-18AArch64: Use standard names for SVE saturating arithmeticAkram Ahmad1-2/+2
2025-01-18Revert "AArch64: Use standard names for saturating arithmetic"Tamar Christina5-271/+56
2025-01-18Revert "AArch64: Use standard names for SVE saturating arithmetic"Tamar Christina1-2/+2
2025-01-17AArch64: Use standard names for SVE saturating arithmeticTamar Christina1-2/+2
2025-01-17AArch64: Use standard names for saturating arithmeticTamar Christina5-56/+271
2025-01-16AArch64: have -mcpu=native detect architecture extensions for unknown non-hom...Tamar Christina1-14/+38
2025-01-16AArch64: don't override march to assembler with mcpu if march is specified [P...Tamar Christina1-1/+1
2025-01-15AArch64: Update neoverse512tvb tuningWilco Dijkstra1-2/+4
2025-01-15AArch64: Add FULLY_PIPELINED_FMA to tune baselineWilco Dijkstra3-5/+4
2025-01-15AArch64: Deprecate -mabi=ilp32Wilco Dijkstra1-0/+2
2025-01-10AArch64: correct Cortex-X4 MIDRTamar Christina1-1/+1
2025-01-10Add new hardreg PRE passAndrew Carlotti1-0/+4
2025-01-10aarch64: Add new +xs flagAndrew Carlotti2-1/+3
2025-01-10aarch64: Add new +wfxt flagAndrew Carlotti2-1/+3
2025-01-10aarch64: Add new +rcpc2 flagAndrew Carlotti3-3/+5
2025-01-10aarch64: Add new +flagm2 flagAndrew Carlotti2-1/+3
2025-01-10aarch64: Add new +frintts flagAndrew Carlotti5-4/+6
2025-01-10aarch64: Add new +jscvt flagAndrew Carlotti4-3/+5
2025-01-10aarch64: Add new +fcma flagAndrew Carlotti4-4/+6
2025-01-10aarch64: Use PAUTH instead of V8_3A in some placesAndrew Carlotti2-7/+7
2025-01-09AArch64: Fix costing of emulated gathers/scatters [PR118188]Tamar Christina1-0/+41
2025-01-08aarch64: Fix overly restrictive sibcall check [PR107102]Richard Sandiford1-1/+11
2025-01-07AArch64: Block combine_and_move from creating FP literal loadsWilco Dijkstra3-27/+54
2025-01-07AArch64: Remove AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTSJennifer Schmitz13-29/+4
2025-01-06aarch64: remove extra XTN in vector concatenationAkram Ahmad1-0/+16
2025-01-06SVE intrinsics: Fold svmul by -1 to svneg for unsigned typesJennifer Schmitz3-29/+86
2025-01-06AArch64: Implement four and eight chunk VLA concats [PR118272]Tamar Christina3-11/+66
2025-01-02aarch64: Detect word-level modification in early-ra [PR118184]Richard Sandiford1-1/+50
2025-01-02Update copyright years.Jakub Jelinek125-125/+125
2024-12-30aarch64: Add mf8 data movement intrinsicsRichard Sandiford8-126/+1092
2024-12-30aarch64: Add missing makefile dependencyRichard Sandiford1-0/+1
2024-12-30aarch64: Use mf8 instead of f8 in builtin definitionsRichard Sandiford2-22/+22
2024-12-30aarch64: Macroise simd_type definitionsRichard Sandiford1-33/+32
2024-12-20AArch64: Implement vector concat of partial SVE vectors [PR96342]Tamar Christina4-2/+66
2024-12-20AArch64: Add SVE support for simd clones [PR96342]Tamar Christina3-30/+156
2024-12-13AArch64: Set L1 data cache size according to size on CPUsTamar Christina9-22/+9
2024-12-13AArch64: Add CMP+CSEL and CMP+CSET for cores that support itTamar Christina10-9/+17
2024-12-11middle-end: Pass stmt_vec_info to TARGET_SIMD_CLONE_USABLE [PR96342]Andre Vieira1-2/+2
2024-12-11aarch64: Use SVE ASRD instruction with Neon modes.Soumya AR3-12/+29
2024-12-11aarch64: Extend SVE2 bit-select instructions for Neon modes.Soumya AR1-0/+66
2024-12-10AArch64: Add baseline tuneWilco Dijkstra13-13/+16
2024-12-10AArch64: Cleanup alignment macrosWilco Dijkstra3-18/+62
2024-12-10AArch64: Use LDP/STP for large struct typesWilco Dijkstra2-83/+21
generated by cgit v1.1 at 2025-02-25 15:51:37 +0000