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AgeCommit message (Expand)AuthorFilesLines
2017-06-07aarch64.c (aarch64_rtx_costs): Make sdiv more expensive than udiv.Tamar Christina1-8/+6
2017-06-072017-06-07 Tamar Christina <tamar.christina@arm.com>Tamar Christina1-4/+6
2017-06-06Remove aarch32 support for falkor/qdf24xx, not in released hardware.Jim Wilson1-3/+105
2017-06-06[AArch64] Allow const0_rtx operand for atomic compare-exchange patternsKyrylo Tkachov1-4/+4
2017-06-05[AArch64] Add combine pattern for storing lane zero of a vectorKyrylo Tkachov1-0/+13
2017-06-05[AArch64] Use SUBS for parallel subtraction and comparison with immediateKyrylo Tkachov2-0/+35
2017-06-05[AArch64] Peephole for SUBSKyrylo Tkachov1-0/+18
2017-06-02[PATCH][AArch64] Allow CMP+SHIFT when comparing with zeroSudakshina Das1-1/+1
2017-06-02[AArch64] Add HF vector modes to lane-to-lane INS patternKyrylo Tkachov1-5/+5
2017-06-02[AArch64] Emit tighter strong atomic compare-exchange loop when comparing aga...Kyrylo Tkachov1-6/+35
2017-05-15[PATCH][AARCH64]Simplify call, call_value, sibcall, sibcall_value patterns.Renlin Li4-129/+65
2017-05-10Move an use-after-free access before the delete.Wilco Dijkstra1-2/+2
2017-05-08[AArch64] Tighten move constraints for symbolic operandsRichard Sandiford2-2/+10
2017-05-05Float to int moves currently generate inefficient code due to hacks used in t...Wilco Dijkstra1-4/+4
2017-05-04Many supported cores use the AUTOPREFETCHER_WEAK setting which tries to order...Wilco Dijkstra1-1/+1
2017-05-04Set jump alignment to 4 for Cortex cores as it reduces codesize by 0.4% on...Wilco Dijkstra1-5/+5
2017-05-04With -mcpu=generic the loop alignment is currently 4.Wilco Dijkstra1-2/+2
2017-05-04All cores which add a cpu_addrcost_table use a non-zero value for HI and TI...Wilco Dijkstra1-2/+2
2017-05-04[AArch64] Accept more addressing modes for PRFMKyrylo Tkachov5-10/+41
2017-04-27[AArch64] Fix for gcc-7 regression PR 80530Richard Earnshaw1-22/+29
2017-04-27re PR target/77728 (Miscompilation multiple vector iteration on ARM)Jakub Jelinek1-69/+21
2017-04-25re PR target/77728 (Miscompilation multiple vector iteration on ARM)Ramana Radhakrishnan1-26/+75
2017-04-25thunderx2t99.md (thunderx2t99_crc): New Reservation.Julian Brown1-0/+7
2017-04-25thunderx2t99.md (thunderx2t99_aes): New Reservation.Julian Brown1-0/+13
2017-04-25aarch64-simd.md (aarch64_simd_vec_set<mode>): Fix type for 1-element load.Julian Brown1-1/+1
2017-04-08aarch64-freebsd.h: Define MCOUNT_NAME.Andreas Tobler1-0/+5
2017-04-07aarch64-freebsd.h: Define WCHAR_TYPE.Andreas Tobler1-0/+3
2017-04-07Error message on target attribute on aarch64 target (PR target/79889).Martin Liska1-2/+6
2017-04-05re PR target/78002 (gcc.target/aarch64/stack-checking.c ICEs with -mabi=ilp32)Eric Botcazou2-23/+20
2017-03-22Recently we've put a lot of effort into improving ifcvt to use CSEL on AArch64.Wilco Dijkstra1-2/+2
2017-03-22Many supported cores implement fusion of AES instructions.Wilco Dijkstra1-1/+1
2017-03-17[aarch64] Fix typo in aarch64.opt (dummping -> dumping).Richard Earnshaw1-1/+1
2017-03-162017-03-16 Tamar Christina <tamar.christina@arm.com>Tamar Christina1-3/+3
2017-03-16[AArch64] Use 'x' constraint for vector HFmode multiplication by indexed elem...Kyrylo Tkachov2-5/+5
2017-03-11aarch64.c: tweaks to quoting in error messages (PR target/79925)David Malcolm1-5/+5
2017-03-09[AArch64] PR target/79913: VEC_SELECT bugs in aarch64 patternsKyrylo Tkachov2-8/+11
2017-03-03[AArch64] Fix bootstrap due to wide_int .elt (0) uninit warningKyrylo Tkachov1-1/+1
2017-02-14aarch64-cores.def (thunderx2t99): Move to under 'C" cores and change the part...Andrew Pinski2-2/+3
2017-02-14[Patch AArch64] Use 128-bit vectors when autovectorizing 16-bit float typesJames Greenhalgh1-0/+4
2017-02-14[AArch64] PR rtl-optimization/68664 Implement TARGET_SCHED_CAN_SPECULATE_INSN...Kyrylo Tkachov1-0/+32
2017-02-13[AArch64] Use contains_mem_rtx_p to detect memory sub-rtxesKyrylo Tkachov1-16/+1
2017-02-10[ARM,AArch64] more poly64 intrinsics and testsChristophe Lyon1-24/+23
2017-02-08aarch64.md (popcount<mode>2): New pattern.Andrew Pinski1-0/+33
2017-02-07aarch64-cores.def (thunderx): Disable LSE.Andrew Pinski1-5/+5
2017-02-06aarch64-cores.def: Change the scheduler to Thunderx2t99.Julian Brown3-2/+446
2017-02-03aarch64.c (thunderx2t99_tunings): Enable AES and cmp_branch fusion.Naveen H.S1-1/+1
2017-02-01tree-vect-loop.c (vect_compute_single_scalar_iteration_cost): Pass stmt_info ...Andrew Pinski2-28/+51
2017-01-30Fix aarch64 PGO bootstrap (bootstrap/78985)Martin Liska1-3/+3
2017-01-23aarch64.c (thunderx2t99_addrcost_table): Improve cost table.Andrew Pinski1-3/+3
2017-01-23aarch64.c (aarch64_elf_asm_constructor): Increase size of buf.Andreas Tobler1-2/+8
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