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2016-09-20[PATCH] [AArch64] Add missing attributes to arm_neon.hTamar Christina1-0/+12
2016-09-20[GCC][PATCH] Add __artificial__ attribute to Aarch64 NEON intrinsicsTamar Christina1-3333/+6639
2016-09-14Delete TARGET_LRA_P from those targets that set it to "true"Segher Boessenkool1-3/+0
2016-09-13[PATCH 1/2][AArch64] Add missing support for poly64x1_tTamar Christina1-3/+3
2016-09-12Add tunning of ldpw for THunderX.Andrew Pinski2-1/+24
2016-09-07Improve aarch64_legitimize_address - avoid splitting the offset if it is supp...Wilco Dijkstra1-2/+12
2016-09-01This patch adds legitimize_address_displacement hook so that stack accesses...Wilco Dijkstra1-0/+22
2016-09-01[AArch64] Add ANDS pattern for CMP+ZERO_EXTENDKyrylo Tkachov2-0/+20
2016-08-30[PATCH][Aarch64][gcc] Fix vld2/3/4 on big endian systemsTamar Christina1-16/+159
2016-08-16re PR tree-optimization/69848 (poor vectorization of a loop from SPEC2006 464...Bin Cheng1-0/+40
2016-08-12re PR c/7652 (-Wswitch-break : Warn if a switch case falls through)Marek Polacek2-0/+3
2016-08-11aarch64-simd.md (vcond<mode><mode>): Delete unused declaration.Bin Cheng1-4/+0
2016-08-11aarch64-simd.md (vec_cmp<mode><v_cmp_result>): Init variable explicitly, also...Bin Cheng1-1/+3
2016-08-10iterators.md (V_cmp_mixed, [...]): New.Bin Cheng2-326/+63
2016-08-10aarch64-simd.md (vec_cmp<mode><mode>): New pattern.Alan Lawrence1-0/+269
2016-08-09[PATCH][PR64971]Convert function pointer to Pmode when emit call.Renlin Li1-15/+0
2016-08-05[AArch64] Handle HFAs of float16 types properlyJames Greenhalgh3-17/+32
2016-08-04aarch64.c (thunderx_vector_cost): New variable.Andrew Pinski1-1/+19
2016-08-02[Patch AArch64 Obvious] Fix Bootstrap for my mistake in r238977James Greenhalgh1-1/+1
2016-08-02[PATCH AArch64] Add more AArch64 NEON intrinsicsTamar Christina5-37/+56
2016-08-01This patch optimizes the prolog and epilog code to reduce the number of instr...Wilco Dijkstra2-199/+188
2016-08-01[AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STPKyrylo Tkachov1-2/+4
2016-08-01aarch64.c (vulcan_tunings): Update vulcan L1 cache_line_size.Virendra Pathak1-1/+1
2016-07-28On AArch64 the UXTB and UXTH instructions are aliases of UBFM,Wilco Dijkstra3-11/+18
2016-07-28This patchset improves zero extend costs and code generation.Kristina Martsenko1-5/+6
2016-07-28This patch improves the readability of the prolog and epilog code by moving s...Wilco Dijkstra1-36/+35
2016-07-25[AArch64][10/10] ARMv8.2-A FP16 lane scalar intrinsicsJiong Wang1-0/+52
2016-07-25[AArch64][9/10] ARMv8.2-A FP16 three operands scalar intrinsicsJiong Wang3-10/+27
2016-07-25[AArch64][8/10] ARMv8.2-A FP16 two operands scalar intrinsicsJiong Wang5-63/+311
2016-07-25[AArch64][7/10] ARMv8.2-A FP16 one operand scalar intrinsicsJiong Wang7-57/+498
2016-07-25[AArch64][6/14] ARMv8.2-A FP16 reduction vector intrinsicsJiong Wang4-12/+65
2016-07-25[AArch64][5/10] ARMv8.2-A FP16 lane vector intrinsicsJiong Wang3-16/+173
2016-07-25[AArch64][4/10] ARMv8.2-A FP16 three operands vector intrinsicsJiong Wang3-15/+43
2016-07-25[AArch64][3/10] ARMv8.2-A FP16 two operands vector intrinsicsJiong Wang5-94/+482
2016-07-25[AArch64][2/10] ARMv8.2-A FP16 one operand vector intrinsicsJiong Wang6-59/+483
2016-07-25[AArch64][1/10] ARMv8.2-A FP16 data processing intrinsicsJiong Wang3-15/+298
2016-07-25[AArch64][3/3] Migrate aarch64_expand_prologue/epilogue to aarch64_add_constantJiong Wang1-63/+24
2016-07-25[AArch64][2/3] Optimize aarch64_add_constant to generate better addition sequ...Jiong Wang1-38/+41
2016-07-25[AArch64][1/3] Migrate aarch64_add_constant to new interface & kill aarch64_b...Jiong Wang1-90/+13
2016-07-15[PATCH/AARCH64] Add rtx_costs routine for vulcan.Virendra Pathak3-1/+178
2016-07-08[AArch64] Use fmin/fmax for v[min|max]nm{q} intrinsicsJiong Wang2-8/+12
2016-07-04[AArch64] Renaming ARMv8.1 to ARMv8.1-A in comments and documentationsJiong Wang4-6/+6
2016-07-04[AArch64] Fix PR target/63874Ramana Radhakrishnan1-4/+8
2016-07-04[AArch64] ARMv8.2 command line and feature macros supportMatthew Wahab4-2/+23
2016-06-30This patch sets the branch cost to the same most optimal setting for all Cort...Wilco Dijkstra1-6/+6
2016-06-30[AArch64][2/2] (Re)Implement vcopy<q>_lane<q> intrinsicsKyrylo Tkachov1-156/+392
2016-06-30[AArch64][1/2] Add support INS (element) instruction to copy lanes between ve...James Greenhalgh1-0/+43
2016-06-29Add qdf24xx base tuning support.Jim Wilson2-1/+52
2016-06-29Increase loop alignment on Cortex cores to 8 and set function alignment to 16.Wilco Dijkstra1-7/+7
2016-06-22aarch64-protos.h (aarch64_elf_asm_named_section): Remove declaration.Andreas Schwab1-1/+0
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