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2013-11-19[AArch64] Fix over length lines around aarch64_save_or_restore_fprs.Marcus Shawcroft1-6/+9
2013-11-19[PATCH] [AArch64] Fix whitespace around aarch64_movdi_<mode>lowMarcus Shawcroft1-3/+3
2013-11-19[AArch64] Fix whitespace around PROFILE_HOOK.Marcus Shawcroft1-7/+7
2013-11-19Factor unrelated declarations out of tree.h.Diego Novillo2-0/+7
2013-11-19[AArch64] Remove v8type attribute.James Greenhalgh1-573/+208
2013-11-18c-common.c (convert_vector_to_pointer_for_subscript): Remove cast to unsigned...Richard Sandiford1-3/+3
2013-11-18decl.c, [...]: Replace tree_low_cst (..., 1) with tree_to_uhwi throughout.Richard Sandiford1-5/+5
2013-11-18c-common.c, [...]: Replace tree_low_cst (..., 0) with tree_to_shwi throughout.Richard Sandiford1-1/+1
2013-11-18decl.c, [...]: Replace host_integerp (..., 1) with tree_fits_uhwi_p throughout.Richard Sandiford1-5/+5
2013-11-15[AArch64] Remove simd_typeJames Greenhalgh2-790/+219
2013-11-14gimplify-be.h: New file.Andrew MacLeod1-0/+1
2013-11-14[AArch64] [-mtune cleanup 4/5] Remove "example-1", "example-2" tuning options.James Greenhalgh5-605/+2
2013-11-14[AArch64] [-mtune cleanup 3/5] [Temporary] When asked to tune forJames Greenhalgh3-3/+4
2013-11-14[AArch64] [-mtune cleanup 2/5] Tune for Cortex-A53 by default.James Greenhalgh5-47/+6
2013-11-14[AArch64] [-mtune cleanup 1/5] Remove -march=generic.James Greenhalgh1-1/+0
2013-11-14aarch64.c: Include aarch-cost-tables.h.Kyrylo Tkachov2-55/+23
2013-11-13gimple-walk.h: New File.Andrew Macleod1-0/+1
2013-11-13aarch64-simd.md (vec_extract): New.Tejas Belagod1-0/+16
2013-11-13aarch64-simd.md (vec_set<mode>): Add w -> w option to the constraint.Tejas Belagod1-20/+24
2013-11-13aarch64.h (FRAME_GROWS_DOWNWARD): Define to 1.Christophe Lyon2-4/+5
2013-11-12gimple-expr.h (create_tmp_var_name, [...]): Relocate prototypes from gimple.h.Andrew MacLeod1-1/+1
2013-11-07aarch64.c (aarch64_legitimize_reload_address): Explain why plus_constant is n...Kyrylo Tkachov1-1/+5
2013-11-06[AArch64] Fix size of memory store for the vst<n>_lane intrinsicsJames Greenhalgh1-9/+18
2013-11-05rtlanal.c (tablejump_p): Expect a JUMP_TABLE_DATA to always follow immediatel...Steven Bosscher1-1/+1
2013-10-24[AArch64,PATCH] Adjust preferred_reload_class of SP+CIan Bolton1-0/+18
2013-10-18[AArch64] Fix types for vcvt<sd>_n intrinsics.James Greenhalgh1-8/+8
2013-10-17aarch64.c (aarch64_print_operand): Handle 'c'.Kyrylo Tkachov1-0/+26
2013-10-17[AArch64] Fix preferred_reload_class for regclass STACK_REG.Marcus Shawcroft1-1/+10
2013-10-16[AArch64] Fix output template for Scalar Neon->Neon register move.James Greenhalgh1-1/+1
2013-10-16[AArch64] Classify FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM as POINTER_REGS.Marcus Shawcroft1-1/+1
2013-10-15[AArch64] [Neon types 4/10] Add type attributes to all simd insnsJames Greenhalgh2-84/+209
2013-10-15[AArch64] [Neon types 2/10] Update Current type attributes to new Neon Types.James Greenhalgh2-3/+12
2013-10-12[AArch64] Fix early-clobber operands to vtbx[1,3]James Greenhalgh1-6/+6
2013-10-09[AArch64] Implement vclz ADVSimd intrinsic.Alex Velenko3-134/+76
2013-10-09[AArch64] Implement vadd_f64 and vsub_f64 ADVSimd intrinsics.Alex Velenko1-0/+12
2013-10-09[AArch64] Implemented vdiv_f64 ADVSimd intrinsic.Alex Velenko1-0/+6
2013-10-09[AArch64] vneg ADVSimd intrinsics rewritten in C.Alex Velenko1-109/+74
2013-10-03[AArch64] Fix PR58460Marcus Shawcroft1-9/+9
2013-10-03[AArch64] Remove un-necessary secondary reload for addition to SP.Ian Bolton2-46/+0
2013-10-02aarch64.c (aarch64_expand_prologue): Use plus_constant.Renlin Li1-13/+13
2013-10-01gcc/Vidya Praveen1-8/+23
2013-09-30Function profiling macro support for Aarch64Venkataramanan Kumar2-9/+16
2013-09-26aarch64.opt (mlra): New option.Yvan Roux2-0/+15
2013-09-23rtl.texi (REG_NOTES): Say that int_list can also be used.Richard Sandiford1-2/+2
2013-09-23Revert r202780:James Greenhalgh1-16/+16
2013-09-20aarch64-builtins.c (aarch64_simd_expand_args): Call aarch64_simd_expand_args ...Yufeng Zhang1-0/+2
2013-09-20[AArch64] Use plus_constant.Renlin Li1-16/+16
2013-09-16[AArch64] Improve arm_neon.h vml<as>_lane handling.James Greenhalgh4-561/+702
2013-09-16[AArch64] Implement vmul<q>_lane<q>_<fsu><16,32,64> intrinsics in CJames Greenhalgh3-287/+228
2013-09-16[AArch64] Fix parameters to vcvtx_highJames Greenhalgh1-2/+2