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2014-06-02aarch64-linux.h (GLIBC_DYNAMIC_LINKER): /lib/ld-linux32-aarch64.so.1 is used ...Andrew Pinski2-7/+4
2014-06-02expr.h: Remove prototypes of functions defined in builtins.c.Andrew MacLeod1-0/+1
2014-06-02[AArch64] Remove ISB after FPCR write.Marcus Shawcroft1-1/+1
2014-06-02Fix ICE in aarch64_float_const_representable_pTom de Vries1-0/+3
2014-05-29Detect EXT patterns to vec_perm_const, use for EXT intrinsicsAlan Lawrence6-313/+390
2014-05-27aarch64.md (stack_protect_set_<mode>): Use <w> for the register in assembly t...Andrew Pinski1-5/+5
2014-05-23[AARCH64] Support tail indirect function call.Jiong Wang5-20/+38
2014-05-22aarch64.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.Kugan Vivekanandarajah4-0/+194
2014-05-22aarch64.c (aarch64_regno_regclass): Change CORE_REGS to GENERAL_REGS.Kugan Vivekanandarajah2-8/+4
2014-05-21arm_neon.h (vqdmulh_n_s16): Change the last operand's constraint.Guozhi Wei1-2/+2
2014-05-17use templates instead of gengtype for typed allocation functionsTrevor Saunders1-1/+1
2014-05-16[AArch64 costs] Fixup to costing of FNMULJames Greenhalgh1-10/+4
2014-05-16[AArch64 costs 18/18] Dump a message if we are unable to cost an insn.James Greenhalgh1-1/+5
2014-05-16[AArch64 costs 17/18] Cost for SYMBOL_REF, HIGH and LO_SUMJames Greenhalgh1-6/+35
2014-05-16[AArch64 costs 16/18] Cost TRUNCATEJames Greenhalgh1-0/+33
2014-05-16[AArch64 costs 15/18] Cost more Floating point RTX.James Greenhalgh1-0/+83
2014-05-16[AArch64 costs 14/18] Cost comparisons, flag setting operators and IF_THEN_ELSEJames Greenhalgh1-11/+148
2014-05-16[AArch64 costs 13/18] Improve costs for div/modJames Greenhalgh1-8/+7
2014-05-16[AArch64 costs 12/18] Improve costs for sign/zero extractsJames Greenhalgh1-2/+61
2014-05-16[AArch64 costs 11/18] Improve costs for rotate and shift operations.James Greenhalgh1-9/+47
2014-05-16[AArch64 costs 10/18] Improve costs for sign/zero extend operationsJames Greenhalgh1-6/+47
2014-05-16[AArch64 costs 9/18] Better cost logical operationsJames Greenhalgh1-5/+60
2014-05-16[AArch64 costs 8/18] Cost memory accesses using address costs James Greenhalgh1-2/+30
2014-05-16[AArch64 costs 7/18] Improve SET cost.James Greenhalgh1-8/+35
2014-05-16[AArch64 costs 6/18] Set default costs and handle vector modes.James Greenhalgh1-0/+15
2014-05-16[AArch64 costs 5/18] Factor out common MULT casesJames Greenhalgh1-110/+254
2014-05-16[AArch64 costs 4/18] Better estimate cost of building a constantJames Greenhalgh1-12/+84
2014-05-16[AArch64 costs 3/18] Wrap aarch64_rtx_costs to dump verbose outputJames Greenhalgh1-0/+21
2014-05-16[AArch64 costs 2/18] Add cost tables for Cortex-A57James Greenhalgh1-2/+43
2014-05-16[AArch64 costs 1/18] Refactor aarch64_address_costs.James Greenhalgh2-31/+117
2014-05-13Implement HARD_REGNO_CALLER_SAVE_MODE for AArch64Ian Bolton3-0/+25
2014-05-07Reimplement AArch64 TRN intrinsics with __builtin_shuffle.Alan Lawrence1-462/+432
2014-05-06Merge in wide-int.Kenneth Zadeck1-19/+19
2014-05-02One-line tidy of bit-twiddle expression in aarch64.cAlan Lawrence1-1/+2
2014-04-30Rewrite AArch64 UZP Intrinsics using __builtin_shuffle.Alan Lawrence1-461/+432
2014-04-29arm_neon.h (vzip1_f32, [...]): Replace inline __asm__ with __builtin_shuffle.Alan Lawrence1-462/+438
2014-04-29aarch64.md (mov<mode>cc): New for GPF.Zhenqiang Chen1-0/+19
2014-04-28[AArch64] Improve vst4_lane intrinsicsJames Greenhalgh6-125/+340
2014-04-28[AArch64] Relax modes_tieable_p and cannot_change_mode_classJames Greenhalgh3-3/+35
2014-04-24[AArch64] Enable TBL for big-endian.Alan Lawrence1-5/+0
2014-04-24[AArch64] Reverse TBL indices for big-endian.Tejas Belagod1-1/+9
2014-04-24[AArch64] Wire up TARGET_SIMD and TARGET_FLOAT properlyKyrylo Tkachov1-6/+6
2014-04-24[AArch64] Vectorise bswap[16,32,64]Kyrylo Tkachov4-1/+39
2014-04-23[AARCH64] Use standard patterns for stack protection.Venkataramanan Kumar1-0/+63
2014-04-23[AArch64] Fully support rotate on logical operations.Richard Earnshaw2-2/+29
2014-04-23[AArch64] Add handling of bswap operations in rtx costsKyrylo Tkachov1-0/+8
2014-04-23[AArch64][2/3] Recognise rev16 operations on SImode and DImode dataKyrylo Tkachov2-0/+42
2014-04-22AArch64 add, sub, mul in TImodeRichard Henderson1-5/+84
2014-04-22[AArch64] Fix TLS for ILP32.Andrew Pinski2-18/+81
2014-04-22[AArch64] Define TARGET_FLAGS_REGNUMRamana Radhakrishnan1-0/+3
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