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path: root/gcc/config/aarch64/constraints.md
AgeCommit message (Expand)AuthorFilesLines
2023-08-04AArch64: Undo vec_widen_<sur>shiftl optabs [PR106346]Tamar Christina1-0/+14
2023-04-25aarch64: Leveraging the use of STP instruction for vec_duplicateVictor Do Nascimento1-1/+1
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-12-06AArch64: Cleanup move immediate codeWilco Dijkstra1-0/+5
2022-11-14aarch64: Add support for +csscKyrylo Tkachov1-0/+10
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-11-05AArch64: Fix PR103085Wilco Dijkstra1-1/+2
2021-11-03AArch64: Improve GOT addressingWilco Dijkstra1-0/+7
2021-10-20AArch64: Add pattern for sshr to cmltTamar Christina1-0/+8
2021-04-28aarch64: Fix address mode for vec_concat pattern [PR100305]Richard Sandiford1-0/+2
2021-03-23[PR99581] Use relaxed memory for more aarch64 memory constraintsVladimir N. Makarov1-6/+6
2021-03-22[PR99581] Define relaxed memory and use it for aarch64Vladimir N. Makarov1-1/+1
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-07-09aarch64: Mitigate SLS for BLR instructionMatthew Malcomson1-0/+9
2020-03-31aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368]Jakub Jelinek1-0/+7
2020-01-17[AArch64] [SVE] Implement svld1ro intrinsic.Matthew Malcomson1-0/+25
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-11-14aarch64: Add "c" constraintRichard Henderson1-0/+4
2019-10-29[AArch64] Add support for arm_sve.hRichard Sandiford1-0/+68
2019-08-19[AArch64] Use scvtf fbits option where appropriateJoel Hutton1-0/+7
2019-08-15[AArch64] Rework SVE INC/DEC handlingRichard Sandiford1-1/+7
2019-08-15[AArch64] Use SVE binary immediate instructions for conditional arithmeticRichard Sandiford1-1/+1
2019-08-14[AArch64] Make more use of SVE conditional constant movesRichard Sandiford1-1/+7
2019-08-14[AArch64] Add support for SVE F{MAX,MIN}NM immediateRichard Sandiford1-1/+8
2019-08-14[AArch64] Add support for SVE [SU]{MAX,MIN} immediateRichard Sandiford1-3/+9
2019-08-13[AArch64] Improve SVE constant movesRichard Sandiford1-0/+6
2019-08-13[AArch64] Add a "y" constraint for V0-V7Richard Sandiford1-0/+3
2019-08-07[AArch64] Fix INSR for zero floatsRichard Sandiford1-2/+2
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
2018-09-19[AARCH64] Use STLUR for atomic_storeMatthew Malcomson1-0/+5
2018-09-13[Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bi...Sam Tebbs1-0/+7
2018-07-19[AArch64][PATCH 1/2] Fix addressing printing of LDP/STPAndre Vieira1-13/+7
2018-04-27[AArch64] PR target/85512: Tighten SIMD right shift immediate constraints pt2Kyrylo Tkachov1-2/+2
2018-04-24[AArch64] PR target/85512: Tighten SIMD right shift immediate constraintsKyrylo Tkachov1-0/+14
2018-02-01[PR83370][AARCH64]Use tighter register constraint for sibcall patterns.Renlin Li1-2/+2
2018-01-17[AArch64] PR82964: Fix 128-bit immediate ICEsWilco Dijkstra1-0/+6
2018-01-13[AArch64] SVE load/store_lanes supportRichard Sandiford1-0/+6
2018-01-13[AArch64] Add SVE supportRichard Sandiford1-6/+114
2018-01-11aarch64-modes.def (V2HF): New VECTOR_MODE.Michael Collison1-0/+12
2018-01-03[AArch64] Rewrite aarch64_simd_valid_immediateRichard Sandiford1-6/+5
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
2017-12-21[AArch64] Tweak aarch64_classify_address interfaceRichard Sandiford1-7/+7
2017-11-08[AArch64] Add STP pattern to store a vec_concat of two 64-bit registersKyrylo Tkachov1-0/+9
2017-11-08vec_merge + vec_duplicate + vec_concat simplificationKyrylo Tkachov1-0/+7
2017-11-01[AArch64] Rename the internal "Upl" constraintRichard Sandiford1-1/+1
2017-10-04[PATCH][AArch64] Add BIC-imm and ORR-imm SIMD patternSudakshina Das1-0/+14
2017-09-13[AArch64, PATCH] Improve Neon store of zeroJackson Woodruff1-0/+8
2017-07-282017-07-28 Tamar Christina <tamar.christina@arm.com>Tamar Christina1-2/+16
2017-05-15[PATCH][AARCH64]Simplify call, call_value, sibcall, sibcall_value patterns.Renlin Li1-1/+2
2017-05-08[AArch64] Tighten move constraints for symbolic operandsRichard Sandiford1-0/+8
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