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path: root/gcc/config/aarch64/aarch64.cc
AgeCommit message (Expand)AuthorFilesLines
2023-08-04AArch64: update costing for MLA by invariantTamar Christina1-9/+15
2023-08-04AArch64: Avoid the ICE on empty reduction definition in info_for_reduction [P...Hao Liu1-1/+1
2023-07-31AArch64: Do not increase the vect reduction latency by multiplying count [PR1...Hao Liu1-4/+23
2023-06-26aarch64: Clean up some rounding immediate predicatesKyrylo Tkachov1-5/+5
2023-06-22Change fma_reassoc_width tuning for ampere1Di Zhao OS1-1/+1
2023-06-20aarch64: Robustify stack tie handlingRichard Sandiford1-4/+14
2023-06-19Fix build of aarc64Richard Biener1-1/+2
2023-06-13aarch64: Extend -mtp= argumentsKyrylo Tkachov1-1/+2
2023-06-12[aarch64] Improve code-gen for vector initialization with single constant ele...Prathamesh Kulkarni1-8/+30
2023-06-06aarch64: Improve representation of ADDLV instructionsKyrylo Tkachov1-0/+44
2023-05-30stor-layout, aarch64: Express SRA intrinsics with RTL codesKyrylo Tkachov1-9/+74
2023-05-25[aarch64] Ignore cost of scalar moves for seq in vector initialization.Prathamesh Kulkarni1-2/+42
2023-05-23aarch64: Provide FPR alternatives for some bit insertions [PR109632]Richard Sandiford1-0/+12
2023-05-18gcc/config/*: use _P() defines from tree.hBernhard Reutner-Fischer1-2/+2
2023-05-15aarch64: Cost vector comparisons more accuratelyKyrylo Tkachov1-0/+21
2023-05-13[aarch64] Recursively intialize even and odd sub-parts and merge with zip1.Prathamesh Kulkarni1-36/+79
2023-05-09aarch64: Improve register allocation for lane instructionsRichard Sandiford1-0/+38
2023-05-03aarch64: Fix ABI handling of aligned enums [PR109661]Richard Sandiford1-5/+38
2023-05-03aarch64: Rename abi_break parameters [PR109661]Richard Sandiford1-34/+36
2023-04-24[4/4] aarch64: Convert UABAL2 and SABAL2 patterns to standard RTL codesKyrylo Tkachov1-2/+36
2023-04-21PR target/108779 aarch64: Implement -mtp= optionKyrylo Tkachov1-0/+17
2023-04-21[aarch64] Use force_reg instead of copy_to_mode_reg.Prathamesh Kulkarni1-6/+6
2023-04-19aarch64: PR target/108840 Simplify register shift RTX costs and eliminate shi...Kyrylo Tkachov1-52/+11
2023-04-18aarch64: Give hint for -mcpu options that match -march insteadKyrylo Tkachov1-0/+6
2023-04-17aarch64: disable LDP via tuning structure for -mcpu=ampere1Philipp Tomsich1-2/+16
2023-04-13aarch64: Don't trust TYPE_ALIGN for pointers [PR108910]Richard Sandiford1-1/+14
2023-04-01aarch64, builtins: Include PR registers in FUNCTION_ARG_REGNO_P etc. [PR109254]Jakub Jelinek1-1/+9
2023-03-28aarch64: Restore vectorisation of vld1 inputs [PR109072]Richard Sandiford1-4/+66
2023-03-27aarch64: update ampere1 vectorization costPhilipp Tomsich1-6/+6
2023-03-13aarch64: Add bfloat16_t support for aarch64Jakub Jelinek1-49/+5
2023-03-12AArch64: Update div-bitmask to implement new optab instead of target hook [PR...Tamar Christina1-44/+17
2023-02-08aarch64: Fix return_address_sign_ab_exception.C regressionAndrea Corallo1-2/+0
2023-02-01AArch64: Fix native detection in the presence of mandatory features which don...Tamar Christina1-8/+0
2023-01-31PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1Philipp Tomsich1-0/+1
2023-01-29aarch64: Correct the maximum shift amount for shifted operandsPhilipp Tomsich1-1/+1
2023-01-23[PATCH 12/15] arm: implement bti injectionAndrea Corallo1-0/+4
2023-01-23[PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm bac...Andrea Corallo1-4/+54
2023-01-23[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64Andrea Corallo1-279/+81
2023-01-19aarch64: fix ICE in aarch64_layout_arg [PR108411]Christophe Lyon1-7/+20
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2023-01-13aarch64: Fix DWARF frame register sizes for predicatesRichard Sandiford1-0/+17
2023-01-13aarch64: Don't update EH info when folding [PR107209]Richard Biener1-1/+1
2023-01-12aarch64: Fix bit-field alignment in param passing [PR105549]Christophe Lyon1-28/+120
2023-01-12aarch64: fix warning emission for ABI break since GCC 9.1Christophe Lyon1-7/+21
2023-01-06Revert "aarch64: Make existing V2HF be usable."Tamar Christina1-1/+0
2022-12-14AArch64: div-by-255, ensure that arguments are registers. [PR107988]Tamar Christina1-8/+8
2022-12-12AArch64: Enable TARGET_CONST_ANCHORWilco Dijkstra1-0/+13
2022-12-12AArch64: Fix vector re-interpretation between partial SIMD modesTamar Christina1-4/+6
2022-12-12aarch64: Make existing V2HF be usable.Tamar Christina1-0/+1
2022-12-08AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776]Sebastian Pop1-15/+41
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