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2023-10-12Support Intel USER_MSRHu, Lin11-1/+2
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect USER_MSR. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_USER_MSR_SET): New. (OPTION_MASK_ISA2_USER_MSR_UNSET): Ditto. (ix86_handle_option): Handle -musermsr. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_USER_MSR. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for usermsr. * config.gcc: Add usermsrintrin.h * config/i386/cpuid.h (bit_USER_MSR): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (VOID, UINT64, UINT64). * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins): Add __builtin_urdmsr and __builtin_uwrmsr. * config/i386/i386-builtins.h (ix86_builtins): Add IX86_BUILTIN_URDMSR and IX86_BUILTIN_UWRMSR. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __USER_MSR__. * config/i386/i386-expand.cc (ix86_expand_builtin): Handle new builtins. * config/i386/i386-isa.def (USER_MSR): Add DEF_PTA(USER_MSR). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle usermsr. * config/i386/i386.md (urdmsr): New define_insn. (uwrmsr): Ditto. * config/i386/i386.opt: Add option -musermsr. * config/i386/x86gprintrin.h: Include usermsrintrin.h * doc/extend.texi: Document usermsr. * doc/invoke.texi: Document -musermsr. * doc/sourcebuild.texi: Document target usermsr. * config/i386/usermsrintrin.h: New file. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/x86gprintrin-1.c: Add -musermsr for 64bit target. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add musermsr for 64bit target. * gcc.target/i386/x86gprintrin-5.c: Ditto * gcc.target/i386/user_msr-1.c: New test. * gcc.target/i386/user_msr-2.c: Ditto.
2023-10-12LoongArch: Adjust makefile dependency for loongarch headers.Yang Yujie1-2/+2
gcc/ChangeLog: * config.gcc: Add loongarch-driver.h to tm_files. * config/loongarch/loongarch.h: Do not include loongarch-driver.h. * config/loongarch/t-loongarch: Append loongarch-multilib.h to $(GTM_H) instead of $(TM_H) for building generator programs.
2023-10-09[PATCH 4/5] Push evex512 target for 512 bit intrinsHaochen Jiang1-9/+10
gcc/ChangeLog: * config.gcc: Add avx512bitalgvlintrin.h. * config/i386/avx5124fmapsintrin.h: Add evex512 target for 512 bit intrins. * config/i386/avx5124vnniwintrin.h: Ditto. * config/i386/avx512bf16intrin.h: Ditto. * config/i386/avx512bitalgintrin.h: Add evex512 target for 512 bit intrins. Split 128/256 bit intrins to avx512bitalgvlintrin.h. * config/i386/avx512erintrin.h: Add evex512 target for 512 bit intrins * config/i386/avx512ifmaintrin.h: Ditto * config/i386/avx512pfintrin.h: Ditto * config/i386/avx512vbmi2intrin.h: Ditto. * config/i386/avx512vbmiintrin.h: Ditto. * config/i386/avx512vnniintrin.h: Ditto. * config/i386/avx512vp2intersectintrin.h: Ditto. * config/i386/avx512vpopcntdqintrin.h: Ditto. * config/i386/gfniintrin.h: Ditto. * config/i386/immintrin.h: Add avx512bitalgvlintrin.h. * config/i386/vaesintrin.h: Add evex512 target for 512 bit intrins. * config/i386/vpclmulqdqintrin.h: Ditto. * config/i386/avx512bitalgvlintrin.h: New.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-*linux*.Iain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (*linux*): Set rust target_objs, and target_has_targetrustm, * config/t-linux (linux-rust.o): New rule. * config/linux-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for i[34567]86-*-mingw* and x86_64-*-mingw*.Iain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (i[34567]86-*-mingw* | x86_64-*-mingw*): Set rust_target_objs and target_has_targetrustm. * config/t-winnt (winnt-rust.o): New rule. * config/winnt-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-fuchsia*.Iain Buclaw1-0/+3
gcc/ChangeLog: * config.gcc (*-*-fuchsia): Set tmake_rule, rust_target_objs, and target_has_targetrustm. * config/fuchsia-rust.cc: New file. * config/t-fuchsia: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-vxworks*Iain Buclaw1-0/+3
gcc/ChangeLog: * config.gcc (*-*-vxworks*): Set rust_target_objs and target_has_targetrustm. * config/t-vxworks (vxworks-rust.o): New rule. * config/vxworks-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-dragonfly*Iain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (*-*-dragonfly*): Set rust_target_objs and target_has_targetrustm. * config/t-dragonfly (dragonfly-rust.o): New rule. * config/dragonfly-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-solaris2*.Iain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (*-*-solaris2*): Set rust_target_objs and target_has_targetrustm. * config/t-sol2 (sol2-rust.o): New rule. * config/sol2-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-openbsd*Iain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (*-*-openbsd*): Set rust_target_objs and target_has_targetrustm. * config/t-openbsd (openbsd-rust.o): New rule. * config/openbsd-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-netbsd*Iain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (*-*-netbsd*): Set rust_target_objs and target_has_targetrustm. * config/t-netbsd (netbsd-rust.o): New rule. * config/netbsd-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-freebsd*Iain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (*-*-freebsd*): Set rust_target_objs and target_has_targetrustm. * config/t-freebsd (freebsd-rust.o): New rule. * config/freebsd-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-darwin*Iain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (*-*-darwin*): Set rust_target_objs and target_has_targetrustm. * config/t-darwin (darwin-rust.o): New rule. * config/darwin-rust.cc: New file.
2023-09-21rust: Add skeleton support and documentation for targetrustm hooks.Iain Buclaw1-0/+25
gcc/ChangeLog: * Makefile.in (tm_rust_file_list, tm_rust_include_list, TM_RUST_H, RUST_TARGET_DEF, RUST_TARGET_H, RUST_TARGET_OBJS): New variables. (tm_rust.h, cs-tm_rust.h, default-rust.o, rust/rust-target-hooks-def.h, s-rust-target-hooks-def-h): New rules. (s-tm-texi): Also check timestamp on rust-target.def. (generated_files): Add TM_RUST_H and rust-target-hooks-def.h. (build/genhooks.o): Also depend on RUST_TARGET_DEF. * config.gcc (tm_rust_file, rust_target_objs, target_has_targetrustm): New variables. * configure: Regenerate. * configure.ac (tm_rust_file_list, tm_rust_include_list, rust_target_objs): Add substitutes. * doc/tm.texi: Regenerate. * doc/tm.texi.in (targetrustm): Document. (target_has_targetrustm): Document. * genhooks.cc: Include rust/rust-target.def. * config/default-rust.cc: New file. gcc/rust/ChangeLog: * rust-target-def.h: New file. * rust-target.def: New file. * rust-target.h: New file.
2023-09-15LoongArch: Reimplement multilib build option handling.Yang Yujie1-3/+3
Library build options from --with-multilib-list used to be processed with *self_spec, which missed the driver's initial canonicalization. This caused limitations on CFLAGS override and the use of driver-only options like -m[no]-lsx. The problem is solved by promoting the injection rules of --with-multilib-list options to the first element of DRIVER_SELF_SPECS, to make them execute before the canonialization. The library-build options are also hard-coded in the driver and can be used conveniently by the builders of other non-gcc libraries via the use of -fmultiflags. Bootstrapped and tested on loongarch64-linux-gnu. ChangeLog: * config-ml.in: Remove unneeded loongarch clause. * configure.ac: Register custom makefile fragments mt-loongarch-* for loongarch targets. * configure: Regenerate. config/ChangeLog: * mt-loongarch-mlib: New file. Pass -fmultiflags when building target libraries (FLAGS_FOR_TARGET). * mt-loongarch-elf: New file. * mt-loongarch-gnu: New file. gcc/ChangeLog: * config.gcc: Pass the default ABI via TM_MULTILIB_CONFIG. * config/loongarch/loongarch-driver.h: Invoke MLIB_SELF_SPECS before the driver canonicalization routines. * config/loongarch/loongarch.h: Move definitions of CC1_SPEC etc. to loongarch-driver.h * config/loongarch/t-linux: Move multilib-related definitions to t-multilib. * config/loongarch/t-multilib: New file. Inject library build options obtained from --with-multilib-list. * config/loongarch/t-loongarch: Same.
2023-09-12riscv: Add support for strlen inline expansionChristoph Müllner1-1/+2
This patch implements the expansion of the strlen builtin for RV32/RV64 for xlen-aligned aligned strings if Zbb or XTheadBb instructions are available. The inserted sequences are: rv32gc_zbb (RV64 is similar): add a3,a0,4 li a4,-1 .L1: lw a5,0(a0) add a0,a0,4 orc.b a5,a5 beq a5,a4,.L1 not a5,a5 ctz a5,a5 srl a5,a5,0x3 add a0,a0,a5 sub a0,a0,a3 rv64gc_xtheadbb (RV32 is similar): add a4,a0,8 .L2: ld a5,0(a0) add a0,a0,8 th.tstnbz a5,a5 beqz a5,.L2 th.rev a5,a5 th.ff1 a5,a5 srl a5,a5,0x3 add a0,a0,a5 sub a0,a0,a4 This allows to inline calls to strlen(), with optimized code for xlen-aligned strings, resulting in the following benefits over a call to libc: * no call/ret instructions * no stack frame allocation * no register saving/restoring * no alignment test The inlining mechanism is gated by a new switch ('-minline-strlen') and by the variable 'optimize_size'. Tested using the glibc string tests. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> gcc/ChangeLog: * config.gcc: Add new object riscv-string.o. riscv-string.cc. * config/riscv/riscv-protos.h (riscv_expand_strlen): New function. * config/riscv/riscv.md (strlen<mode>): New expand INSN. * config/riscv/riscv.opt: New flag 'minline-strlen'. * config/riscv/t-riscv: Add new object riscv-string.o. * config/riscv/thead.md (th_rev<mode>2): Export INSN name. (th_rev<mode>2): Likewise. (th_tstnbz<mode>2): New INSN. * doc/invoke.texi: Document '-minline-strlen'. * emit-rtl.cc (emit_likely_jump_insn): New helper function. (emit_unlikely_jump_insn): Likewise. * rtl.h (emit_likely_jump_insn): New prototype. (emit_unlikely_jump_insn): Likewise. * config/riscv/riscv-string.cc: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadbb-strlen-unaligned.c: New test. * gcc.target/riscv/xtheadbb-strlen.c: New test. * gcc.target/riscv/zbb-strlen-disabled-2.c: New test. * gcc.target/riscv/zbb-strlen-disabled.c: New test. * gcc.target/riscv/zbb-strlen-unaligned.c: New test. * gcc.target/riscv/zbb-strlen.c: New test.
2023-09-08LoongArch: Fix unintentional bash-ism in r14-3665.Yang Yujie1-1/+1
gcc/ChangeLog: * config.gcc: remove non-POSIX syntax "<<<".
2023-09-05LoongArch: Add Loongson ASX directive builtin function support.Lulu Cheng1-1/+1
gcc/ChangeLog: * config.gcc: Export the header file lasxintrin.h. * config/loongarch/loongarch-builtins.cc (enum loongarch_builtin_type): Add Loongson ASX builtin functions support. (AVAIL_ALL): Ditto. (LASX_BUILTIN): Ditto. (LASX_NO_TARGET_BUILTIN): Ditto. (LASX_BUILTIN_TEST_BRANCH): Ditto. (CODE_FOR_lasx_xvsadd_b): Ditto. (CODE_FOR_lasx_xvsadd_h): Ditto. (CODE_FOR_lasx_xvsadd_w): Ditto. (CODE_FOR_lasx_xvsadd_d): Ditto. (CODE_FOR_lasx_xvsadd_bu): Ditto. (CODE_FOR_lasx_xvsadd_hu): Ditto. (CODE_FOR_lasx_xvsadd_wu): Ditto. (CODE_FOR_lasx_xvsadd_du): Ditto. (CODE_FOR_lasx_xvadd_b): Ditto. (CODE_FOR_lasx_xvadd_h): Ditto. (CODE_FOR_lasx_xvadd_w): Ditto. (CODE_FOR_lasx_xvadd_d): Ditto. (CODE_FOR_lasx_xvaddi_bu): Ditto. (CODE_FOR_lasx_xvaddi_hu): Ditto. (CODE_FOR_lasx_xvaddi_wu): Ditto. (CODE_FOR_lasx_xvaddi_du): Ditto. (CODE_FOR_lasx_xvand_v): Ditto. (CODE_FOR_lasx_xvandi_b): Ditto. (CODE_FOR_lasx_xvbitsel_v): Ditto. (CODE_FOR_lasx_xvseqi_b): Ditto. (CODE_FOR_lasx_xvseqi_h): Ditto. (CODE_FOR_lasx_xvseqi_w): Ditto. (CODE_FOR_lasx_xvseqi_d): Ditto. (CODE_FOR_lasx_xvslti_b): Ditto. (CODE_FOR_lasx_xvslti_h): Ditto. (CODE_FOR_lasx_xvslti_w): Ditto. (CODE_FOR_lasx_xvslti_d): Ditto. (CODE_FOR_lasx_xvslti_bu): Ditto. (CODE_FOR_lasx_xvslti_hu): Ditto. (CODE_FOR_lasx_xvslti_wu): Ditto. (CODE_FOR_lasx_xvslti_du): Ditto. (CODE_FOR_lasx_xvslei_b): Ditto. (CODE_FOR_lasx_xvslei_h): Ditto. (CODE_FOR_lasx_xvslei_w): Ditto. (CODE_FOR_lasx_xvslei_d): Ditto. (CODE_FOR_lasx_xvslei_bu): Ditto. (CODE_FOR_lasx_xvslei_hu): Ditto. (CODE_FOR_lasx_xvslei_wu): Ditto. (CODE_FOR_lasx_xvslei_du): Ditto. (CODE_FOR_lasx_xvdiv_b): Ditto. (CODE_FOR_lasx_xvdiv_h): Ditto. (CODE_FOR_lasx_xvdiv_w): Ditto. (CODE_FOR_lasx_xvdiv_d): Ditto. (CODE_FOR_lasx_xvdiv_bu): Ditto. (CODE_FOR_lasx_xvdiv_hu): Ditto. (CODE_FOR_lasx_xvdiv_wu): Ditto. (CODE_FOR_lasx_xvdiv_du): Ditto. (CODE_FOR_lasx_xvfadd_s): Ditto. (CODE_FOR_lasx_xvfadd_d): Ditto. (CODE_FOR_lasx_xvftintrz_w_s): Ditto. (CODE_FOR_lasx_xvftintrz_l_d): Ditto. (CODE_FOR_lasx_xvftintrz_wu_s): Ditto. (CODE_FOR_lasx_xvftintrz_lu_d): Ditto. (CODE_FOR_lasx_xvffint_s_w): Ditto. (CODE_FOR_lasx_xvffint_d_l): Ditto. (CODE_FOR_lasx_xvffint_s_wu): Ditto. (CODE_FOR_lasx_xvffint_d_lu): Ditto. (CODE_FOR_lasx_xvfsub_s): Ditto. (CODE_FOR_lasx_xvfsub_d): Ditto. (CODE_FOR_lasx_xvfmul_s): Ditto. (CODE_FOR_lasx_xvfmul_d): Ditto. (CODE_FOR_lasx_xvfdiv_s): Ditto. (CODE_FOR_lasx_xvfdiv_d): Ditto. (CODE_FOR_lasx_xvfmax_s): Ditto. (CODE_FOR_lasx_xvfmax_d): Ditto. (CODE_FOR_lasx_xvfmin_s): Ditto. (CODE_FOR_lasx_xvfmin_d): Ditto. (CODE_FOR_lasx_xvfsqrt_s): Ditto. (CODE_FOR_lasx_xvfsqrt_d): Ditto. (CODE_FOR_lasx_xvflogb_s): Ditto. (CODE_FOR_lasx_xvflogb_d): Ditto. (CODE_FOR_lasx_xvmax_b): Ditto. (CODE_FOR_lasx_xvmax_h): Ditto. (CODE_FOR_lasx_xvmax_w): Ditto. (CODE_FOR_lasx_xvmax_d): Ditto. (CODE_FOR_lasx_xvmaxi_b): Ditto. (CODE_FOR_lasx_xvmaxi_h): Ditto. (CODE_FOR_lasx_xvmaxi_w): Ditto. (CODE_FOR_lasx_xvmaxi_d): Ditto. (CODE_FOR_lasx_xvmax_bu): Ditto. (CODE_FOR_lasx_xvmax_hu): Ditto. (CODE_FOR_lasx_xvmax_wu): Ditto. (CODE_FOR_lasx_xvmax_du): Ditto. (CODE_FOR_lasx_xvmaxi_bu): Ditto. (CODE_FOR_lasx_xvmaxi_hu): Ditto. (CODE_FOR_lasx_xvmaxi_wu): Ditto. (CODE_FOR_lasx_xvmaxi_du): Ditto. (CODE_FOR_lasx_xvmin_b): Ditto. (CODE_FOR_lasx_xvmin_h): Ditto. (CODE_FOR_lasx_xvmin_w): Ditto. (CODE_FOR_lasx_xvmin_d): Ditto. (CODE_FOR_lasx_xvmini_b): Ditto. (CODE_FOR_lasx_xvmini_h): Ditto. (CODE_FOR_lasx_xvmini_w): Ditto. (CODE_FOR_lasx_xvmini_d): Ditto. (CODE_FOR_lasx_xvmin_bu): Ditto. (CODE_FOR_lasx_xvmin_hu): Ditto. (CODE_FOR_lasx_xvmin_wu): Ditto. (CODE_FOR_lasx_xvmin_du): Ditto. (CODE_FOR_lasx_xvmini_bu): Ditto. (CODE_FOR_lasx_xvmini_hu): Ditto. (CODE_FOR_lasx_xvmini_wu): Ditto. (CODE_FOR_lasx_xvmini_du): Ditto. (CODE_FOR_lasx_xvmod_b): Ditto. (CODE_FOR_lasx_xvmod_h): Ditto. (CODE_FOR_lasx_xvmod_w): Ditto. (CODE_FOR_lasx_xvmod_d): Ditto. (CODE_FOR_lasx_xvmod_bu): Ditto. (CODE_FOR_lasx_xvmod_hu): Ditto. (CODE_FOR_lasx_xvmod_wu): Ditto. (CODE_FOR_lasx_xvmod_du): Ditto. (CODE_FOR_lasx_xvmul_b): Ditto. (CODE_FOR_lasx_xvmul_h): Ditto. (CODE_FOR_lasx_xvmul_w): Ditto. (CODE_FOR_lasx_xvmul_d): Ditto. (CODE_FOR_lasx_xvclz_b): Ditto. (CODE_FOR_lasx_xvclz_h): Ditto. (CODE_FOR_lasx_xvclz_w): Ditto. (CODE_FOR_lasx_xvclz_d): Ditto. (CODE_FOR_lasx_xvnor_v): Ditto. (CODE_FOR_lasx_xvor_v): Ditto. (CODE_FOR_lasx_xvori_b): Ditto. (CODE_FOR_lasx_xvnori_b): Ditto. (CODE_FOR_lasx_xvpcnt_b): Ditto. (CODE_FOR_lasx_xvpcnt_h): Ditto. (CODE_FOR_lasx_xvpcnt_w): Ditto. (CODE_FOR_lasx_xvpcnt_d): Ditto. (CODE_FOR_lasx_xvxor_v): Ditto. (CODE_FOR_lasx_xvxori_b): Ditto. (CODE_FOR_lasx_xvsll_b): Ditto. (CODE_FOR_lasx_xvsll_h): Ditto. (CODE_FOR_lasx_xvsll_w): Ditto. (CODE_FOR_lasx_xvsll_d): Ditto. (CODE_FOR_lasx_xvslli_b): Ditto. (CODE_FOR_lasx_xvslli_h): Ditto. (CODE_FOR_lasx_xvslli_w): Ditto. (CODE_FOR_lasx_xvslli_d): Ditto. (CODE_FOR_lasx_xvsra_b): Ditto. (CODE_FOR_lasx_xvsra_h): Ditto. (CODE_FOR_lasx_xvsra_w): Ditto. (CODE_FOR_lasx_xvsra_d): Ditto. (CODE_FOR_lasx_xvsrai_b): Ditto. (CODE_FOR_lasx_xvsrai_h): Ditto. (CODE_FOR_lasx_xvsrai_w): Ditto. (CODE_FOR_lasx_xvsrai_d): Ditto. (CODE_FOR_lasx_xvsrl_b): Ditto. (CODE_FOR_lasx_xvsrl_h): Ditto. (CODE_FOR_lasx_xvsrl_w): Ditto. (CODE_FOR_lasx_xvsrl_d): Ditto. (CODE_FOR_lasx_xvsrli_b): Ditto. (CODE_FOR_lasx_xvsrli_h): Ditto. (CODE_FOR_lasx_xvsrli_w): Ditto. (CODE_FOR_lasx_xvsrli_d): Ditto. (CODE_FOR_lasx_xvsub_b): Ditto. (CODE_FOR_lasx_xvsub_h): Ditto. (CODE_FOR_lasx_xvsub_w): Ditto. (CODE_FOR_lasx_xvsub_d): Ditto. (CODE_FOR_lasx_xvsubi_bu): Ditto. (CODE_FOR_lasx_xvsubi_hu): Ditto. (CODE_FOR_lasx_xvsubi_wu): Ditto. (CODE_FOR_lasx_xvsubi_du): Ditto. (CODE_FOR_lasx_xvpackod_d): Ditto. (CODE_FOR_lasx_xvpackev_d): Ditto. (CODE_FOR_lasx_xvpickod_d): Ditto. (CODE_FOR_lasx_xvpickev_d): Ditto. (CODE_FOR_lasx_xvrepli_b): Ditto. (CODE_FOR_lasx_xvrepli_h): Ditto. (CODE_FOR_lasx_xvrepli_w): Ditto. (CODE_FOR_lasx_xvrepli_d): Ditto. (CODE_FOR_lasx_xvandn_v): Ditto. (CODE_FOR_lasx_xvorn_v): Ditto. (CODE_FOR_lasx_xvneg_b): Ditto. (CODE_FOR_lasx_xvneg_h): Ditto. (CODE_FOR_lasx_xvneg_w): Ditto. (CODE_FOR_lasx_xvneg_d): Ditto. (CODE_FOR_lasx_xvbsrl_v): Ditto. (CODE_FOR_lasx_xvbsll_v): Ditto. (CODE_FOR_lasx_xvfmadd_s): Ditto. (CODE_FOR_lasx_xvfmadd_d): Ditto. (CODE_FOR_lasx_xvfmsub_s): Ditto. (CODE_FOR_lasx_xvfmsub_d): Ditto. (CODE_FOR_lasx_xvfnmadd_s): Ditto. (CODE_FOR_lasx_xvfnmadd_d): Ditto. (CODE_FOR_lasx_xvfnmsub_s): Ditto. (CODE_FOR_lasx_xvfnmsub_d): Ditto. (CODE_FOR_lasx_xvpermi_q): Ditto. (CODE_FOR_lasx_xvpermi_d): Ditto. (CODE_FOR_lasx_xbnz_v): Ditto. (CODE_FOR_lasx_xbz_v): Ditto. (CODE_FOR_lasx_xvssub_b): Ditto. (CODE_FOR_lasx_xvssub_h): Ditto. (CODE_FOR_lasx_xvssub_w): Ditto. (CODE_FOR_lasx_xvssub_d): Ditto. (CODE_FOR_lasx_xvssub_bu): Ditto. (CODE_FOR_lasx_xvssub_hu): Ditto. (CODE_FOR_lasx_xvssub_wu): Ditto. (CODE_FOR_lasx_xvssub_du): Ditto. (CODE_FOR_lasx_xvabsd_b): Ditto. (CODE_FOR_lasx_xvabsd_h): Ditto. (CODE_FOR_lasx_xvabsd_w): Ditto. (CODE_FOR_lasx_xvabsd_d): Ditto. (CODE_FOR_lasx_xvabsd_bu): Ditto. (CODE_FOR_lasx_xvabsd_hu): Ditto. (CODE_FOR_lasx_xvabsd_wu): Ditto. (CODE_FOR_lasx_xvabsd_du): Ditto. (CODE_FOR_lasx_xvavg_b): Ditto. (CODE_FOR_lasx_xvavg_h): Ditto. (CODE_FOR_lasx_xvavg_w): Ditto. (CODE_FOR_lasx_xvavg_d): Ditto. (CODE_FOR_lasx_xvavg_bu): Ditto. (CODE_FOR_lasx_xvavg_hu): Ditto. (CODE_FOR_lasx_xvavg_wu): Ditto. (CODE_FOR_lasx_xvavg_du): Ditto. (CODE_FOR_lasx_xvavgr_b): Ditto. (CODE_FOR_lasx_xvavgr_h): Ditto. (CODE_FOR_lasx_xvavgr_w): Ditto. (CODE_FOR_lasx_xvavgr_d): Ditto. (CODE_FOR_lasx_xvavgr_bu): Ditto. (CODE_FOR_lasx_xvavgr_hu): Ditto. (CODE_FOR_lasx_xvavgr_wu): Ditto. (CODE_FOR_lasx_xvavgr_du): Ditto. (CODE_FOR_lasx_xvmuh_b): Ditto. (CODE_FOR_lasx_xvmuh_h): Ditto. (CODE_FOR_lasx_xvmuh_w): Ditto. (CODE_FOR_lasx_xvmuh_d): Ditto. (CODE_FOR_lasx_xvmuh_bu): Ditto. (CODE_FOR_lasx_xvmuh_hu): Ditto. (CODE_FOR_lasx_xvmuh_wu): Ditto. (CODE_FOR_lasx_xvmuh_du): Ditto. (CODE_FOR_lasx_xvssran_b_h): Ditto. (CODE_FOR_lasx_xvssran_h_w): Ditto. (CODE_FOR_lasx_xvssran_w_d): Ditto. (CODE_FOR_lasx_xvssran_bu_h): Ditto. (CODE_FOR_lasx_xvssran_hu_w): Ditto. (CODE_FOR_lasx_xvssran_wu_d): Ditto. (CODE_FOR_lasx_xvssrarn_b_h): Ditto. (CODE_FOR_lasx_xvssrarn_h_w): Ditto. (CODE_FOR_lasx_xvssrarn_w_d): Ditto. (CODE_FOR_lasx_xvssrarn_bu_h): Ditto. (CODE_FOR_lasx_xvssrarn_hu_w): Ditto. (CODE_FOR_lasx_xvssrarn_wu_d): Ditto. (CODE_FOR_lasx_xvssrln_bu_h): Ditto. (CODE_FOR_lasx_xvssrln_hu_w): Ditto. (CODE_FOR_lasx_xvssrln_wu_d): Ditto. (CODE_FOR_lasx_xvssrlrn_bu_h): Ditto. (CODE_FOR_lasx_xvssrlrn_hu_w): Ditto. (CODE_FOR_lasx_xvssrlrn_wu_d): Ditto. (CODE_FOR_lasx_xvftint_w_s): Ditto. (CODE_FOR_lasx_xvftint_l_d): Ditto. (CODE_FOR_lasx_xvftint_wu_s): Ditto. (CODE_FOR_lasx_xvftint_lu_d): Ditto. (CODE_FOR_lasx_xvsllwil_h_b): Ditto. (CODE_FOR_lasx_xvsllwil_w_h): Ditto. (CODE_FOR_lasx_xvsllwil_d_w): Ditto. (CODE_FOR_lasx_xvsllwil_hu_bu): Ditto. (CODE_FOR_lasx_xvsllwil_wu_hu): Ditto. (CODE_FOR_lasx_xvsllwil_du_wu): Ditto. (CODE_FOR_lasx_xvsat_b): Ditto. (CODE_FOR_lasx_xvsat_h): Ditto. (CODE_FOR_lasx_xvsat_w): Ditto. (CODE_FOR_lasx_xvsat_d): Ditto. (CODE_FOR_lasx_xvsat_bu): Ditto. (CODE_FOR_lasx_xvsat_hu): Ditto. (CODE_FOR_lasx_xvsat_wu): Ditto. (CODE_FOR_lasx_xvsat_du): Ditto. (loongarch_builtin_vectorized_function): Ditto. (loongarch_expand_builtin_insn): Ditto. (loongarch_expand_builtin): Ditto. * config/loongarch/loongarch-ftypes.def (1): Ditto. (2): Ditto. (3): Ditto. (4): Ditto. * config/loongarch/lasxintrin.h: New file.
2023-09-05LoongArch: Add Loongson SX directive builtin function support.Lulu Cheng1-1/+1
gcc/ChangeLog: * config.gcc: Export the header file lsxintrin.h. * config/loongarch/loongarch-builtins.cc (LARCH_FTYPE_NAME4): Add builtin function support. (enum loongarch_builtin_type): Ditto. (AVAIL_ALL): Ditto. (LARCH_BUILTIN): Ditto. (LSX_BUILTIN): Ditto. (LSX_BUILTIN_TEST_BRANCH): Ditto. (LSX_NO_TARGET_BUILTIN): Ditto. (CODE_FOR_lsx_vsadd_b): Ditto. (CODE_FOR_lsx_vsadd_h): Ditto. (CODE_FOR_lsx_vsadd_w): Ditto. (CODE_FOR_lsx_vsadd_d): Ditto. (CODE_FOR_lsx_vsadd_bu): Ditto. (CODE_FOR_lsx_vsadd_hu): Ditto. (CODE_FOR_lsx_vsadd_wu): Ditto. (CODE_FOR_lsx_vsadd_du): Ditto. (CODE_FOR_lsx_vadd_b): Ditto. (CODE_FOR_lsx_vadd_h): Ditto. (CODE_FOR_lsx_vadd_w): Ditto. (CODE_FOR_lsx_vadd_d): Ditto. (CODE_FOR_lsx_vaddi_bu): Ditto. (CODE_FOR_lsx_vaddi_hu): Ditto. (CODE_FOR_lsx_vaddi_wu): Ditto. (CODE_FOR_lsx_vaddi_du): Ditto. (CODE_FOR_lsx_vand_v): Ditto. (CODE_FOR_lsx_vandi_b): Ditto. (CODE_FOR_lsx_bnz_v): Ditto. (CODE_FOR_lsx_bz_v): Ditto. (CODE_FOR_lsx_vbitsel_v): Ditto. (CODE_FOR_lsx_vseqi_b): Ditto. (CODE_FOR_lsx_vseqi_h): Ditto. (CODE_FOR_lsx_vseqi_w): Ditto. (CODE_FOR_lsx_vseqi_d): Ditto. (CODE_FOR_lsx_vslti_b): Ditto. (CODE_FOR_lsx_vslti_h): Ditto. (CODE_FOR_lsx_vslti_w): Ditto. (CODE_FOR_lsx_vslti_d): Ditto. (CODE_FOR_lsx_vslti_bu): Ditto. (CODE_FOR_lsx_vslti_hu): Ditto. (CODE_FOR_lsx_vslti_wu): Ditto. (CODE_FOR_lsx_vslti_du): Ditto. (CODE_FOR_lsx_vslei_b): Ditto. (CODE_FOR_lsx_vslei_h): Ditto. (CODE_FOR_lsx_vslei_w): Ditto. (CODE_FOR_lsx_vslei_d): Ditto. (CODE_FOR_lsx_vslei_bu): Ditto. (CODE_FOR_lsx_vslei_hu): Ditto. (CODE_FOR_lsx_vslei_wu): Ditto. (CODE_FOR_lsx_vslei_du): Ditto. (CODE_FOR_lsx_vdiv_b): Ditto. (CODE_FOR_lsx_vdiv_h): Ditto. (CODE_FOR_lsx_vdiv_w): Ditto. (CODE_FOR_lsx_vdiv_d): Ditto. (CODE_FOR_lsx_vdiv_bu): Ditto. (CODE_FOR_lsx_vdiv_hu): Ditto. (CODE_FOR_lsx_vdiv_wu): Ditto. (CODE_FOR_lsx_vdiv_du): Ditto. (CODE_FOR_lsx_vfadd_s): Ditto. (CODE_FOR_lsx_vfadd_d): Ditto. (CODE_FOR_lsx_vftintrz_w_s): Ditto. (CODE_FOR_lsx_vftintrz_l_d): Ditto. (CODE_FOR_lsx_vftintrz_wu_s): Ditto. (CODE_FOR_lsx_vftintrz_lu_d): Ditto. (CODE_FOR_lsx_vffint_s_w): Ditto. (CODE_FOR_lsx_vffint_d_l): Ditto. (CODE_FOR_lsx_vffint_s_wu): Ditto. (CODE_FOR_lsx_vffint_d_lu): Ditto. (CODE_FOR_lsx_vfsub_s): Ditto. (CODE_FOR_lsx_vfsub_d): Ditto. (CODE_FOR_lsx_vfmul_s): Ditto. (CODE_FOR_lsx_vfmul_d): Ditto. (CODE_FOR_lsx_vfdiv_s): Ditto. (CODE_FOR_lsx_vfdiv_d): Ditto. (CODE_FOR_lsx_vfmax_s): Ditto. (CODE_FOR_lsx_vfmax_d): Ditto. (CODE_FOR_lsx_vfmin_s): Ditto. (CODE_FOR_lsx_vfmin_d): Ditto. (CODE_FOR_lsx_vfsqrt_s): Ditto. (CODE_FOR_lsx_vfsqrt_d): Ditto. (CODE_FOR_lsx_vflogb_s): Ditto. (CODE_FOR_lsx_vflogb_d): Ditto. (CODE_FOR_lsx_vmax_b): Ditto. (CODE_FOR_lsx_vmax_h): Ditto. (CODE_FOR_lsx_vmax_w): Ditto. (CODE_FOR_lsx_vmax_d): Ditto. (CODE_FOR_lsx_vmaxi_b): Ditto. (CODE_FOR_lsx_vmaxi_h): Ditto. (CODE_FOR_lsx_vmaxi_w): Ditto. (CODE_FOR_lsx_vmaxi_d): Ditto. (CODE_FOR_lsx_vmax_bu): Ditto. (CODE_FOR_lsx_vmax_hu): Ditto. (CODE_FOR_lsx_vmax_wu): Ditto. (CODE_FOR_lsx_vmax_du): Ditto. (CODE_FOR_lsx_vmaxi_bu): Ditto. (CODE_FOR_lsx_vmaxi_hu): Ditto. (CODE_FOR_lsx_vmaxi_wu): Ditto. (CODE_FOR_lsx_vmaxi_du): Ditto. (CODE_FOR_lsx_vmin_b): Ditto. (CODE_FOR_lsx_vmin_h): Ditto. (CODE_FOR_lsx_vmin_w): Ditto. (CODE_FOR_lsx_vmin_d): Ditto. (CODE_FOR_lsx_vmini_b): Ditto. (CODE_FOR_lsx_vmini_h): Ditto. (CODE_FOR_lsx_vmini_w): Ditto. (CODE_FOR_lsx_vmini_d): Ditto. (CODE_FOR_lsx_vmin_bu): Ditto. (CODE_FOR_lsx_vmin_hu): Ditto. (CODE_FOR_lsx_vmin_wu): Ditto. (CODE_FOR_lsx_vmin_du): Ditto. (CODE_FOR_lsx_vmini_bu): Ditto. (CODE_FOR_lsx_vmini_hu): Ditto. (CODE_FOR_lsx_vmini_wu): Ditto. (CODE_FOR_lsx_vmini_du): Ditto. (CODE_FOR_lsx_vmod_b): Ditto. (CODE_FOR_lsx_vmod_h): Ditto. (CODE_FOR_lsx_vmod_w): Ditto. (CODE_FOR_lsx_vmod_d): Ditto. (CODE_FOR_lsx_vmod_bu): Ditto. (CODE_FOR_lsx_vmod_hu): Ditto. (CODE_FOR_lsx_vmod_wu): Ditto. (CODE_FOR_lsx_vmod_du): Ditto. (CODE_FOR_lsx_vmul_b): Ditto. (CODE_FOR_lsx_vmul_h): Ditto. (CODE_FOR_lsx_vmul_w): Ditto. (CODE_FOR_lsx_vmul_d): Ditto. (CODE_FOR_lsx_vclz_b): Ditto. (CODE_FOR_lsx_vclz_h): Ditto. (CODE_FOR_lsx_vclz_w): Ditto. (CODE_FOR_lsx_vclz_d): Ditto. (CODE_FOR_lsx_vnor_v): Ditto. (CODE_FOR_lsx_vor_v): Ditto. (CODE_FOR_lsx_vori_b): Ditto. (CODE_FOR_lsx_vnori_b): Ditto. (CODE_FOR_lsx_vpcnt_b): Ditto. (CODE_FOR_lsx_vpcnt_h): Ditto. (CODE_FOR_lsx_vpcnt_w): Ditto. (CODE_FOR_lsx_vpcnt_d): Ditto. (CODE_FOR_lsx_vxor_v): Ditto. (CODE_FOR_lsx_vxori_b): Ditto. (CODE_FOR_lsx_vsll_b): Ditto. (CODE_FOR_lsx_vsll_h): Ditto. (CODE_FOR_lsx_vsll_w): Ditto. (CODE_FOR_lsx_vsll_d): Ditto. (CODE_FOR_lsx_vslli_b): Ditto. (CODE_FOR_lsx_vslli_h): Ditto. (CODE_FOR_lsx_vslli_w): Ditto. (CODE_FOR_lsx_vslli_d): Ditto. (CODE_FOR_lsx_vsra_b): Ditto. (CODE_FOR_lsx_vsra_h): Ditto. (CODE_FOR_lsx_vsra_w): Ditto. (CODE_FOR_lsx_vsra_d): Ditto. (CODE_FOR_lsx_vsrai_b): Ditto. (CODE_FOR_lsx_vsrai_h): Ditto. (CODE_FOR_lsx_vsrai_w): Ditto. (CODE_FOR_lsx_vsrai_d): Ditto. (CODE_FOR_lsx_vsrl_b): Ditto. (CODE_FOR_lsx_vsrl_h): Ditto. (CODE_FOR_lsx_vsrl_w): Ditto. (CODE_FOR_lsx_vsrl_d): Ditto. (CODE_FOR_lsx_vsrli_b): Ditto. (CODE_FOR_lsx_vsrli_h): Ditto. (CODE_FOR_lsx_vsrli_w): Ditto. (CODE_FOR_lsx_vsrli_d): Ditto. (CODE_FOR_lsx_vsub_b): Ditto. (CODE_FOR_lsx_vsub_h): Ditto. (CODE_FOR_lsx_vsub_w): Ditto. (CODE_FOR_lsx_vsub_d): Ditto. (CODE_FOR_lsx_vsubi_bu): Ditto. (CODE_FOR_lsx_vsubi_hu): Ditto. (CODE_FOR_lsx_vsubi_wu): Ditto. (CODE_FOR_lsx_vsubi_du): Ditto. (CODE_FOR_lsx_vpackod_d): Ditto. (CODE_FOR_lsx_vpackev_d): Ditto. (CODE_FOR_lsx_vpickod_d): Ditto. (CODE_FOR_lsx_vpickev_d): Ditto. (CODE_FOR_lsx_vrepli_b): Ditto. (CODE_FOR_lsx_vrepli_h): Ditto. (CODE_FOR_lsx_vrepli_w): Ditto. (CODE_FOR_lsx_vrepli_d): Ditto. (CODE_FOR_lsx_vsat_b): Ditto. (CODE_FOR_lsx_vsat_h): Ditto. (CODE_FOR_lsx_vsat_w): Ditto. (CODE_FOR_lsx_vsat_d): Ditto. (CODE_FOR_lsx_vsat_bu): Ditto. (CODE_FOR_lsx_vsat_hu): Ditto. (CODE_FOR_lsx_vsat_wu): Ditto. (CODE_FOR_lsx_vsat_du): Ditto. (CODE_FOR_lsx_vavg_b): Ditto. (CODE_FOR_lsx_vavg_h): Ditto. (CODE_FOR_lsx_vavg_w): Ditto. (CODE_FOR_lsx_vavg_d): Ditto. (CODE_FOR_lsx_vavg_bu): Ditto. (CODE_FOR_lsx_vavg_hu): Ditto. (CODE_FOR_lsx_vavg_wu): Ditto. (CODE_FOR_lsx_vavg_du): Ditto. (CODE_FOR_lsx_vavgr_b): Ditto. (CODE_FOR_lsx_vavgr_h): Ditto. (CODE_FOR_lsx_vavgr_w): Ditto. (CODE_FOR_lsx_vavgr_d): Ditto. (CODE_FOR_lsx_vavgr_bu): Ditto. (CODE_FOR_lsx_vavgr_hu): Ditto. (CODE_FOR_lsx_vavgr_wu): Ditto. (CODE_FOR_lsx_vavgr_du): Ditto. (CODE_FOR_lsx_vssub_b): Ditto. (CODE_FOR_lsx_vssub_h): Ditto. (CODE_FOR_lsx_vssub_w): Ditto. (CODE_FOR_lsx_vssub_d): Ditto. (CODE_FOR_lsx_vssub_bu): Ditto. (CODE_FOR_lsx_vssub_hu): Ditto. (CODE_FOR_lsx_vssub_wu): Ditto. (CODE_FOR_lsx_vssub_du): Ditto. (CODE_FOR_lsx_vabsd_b): Ditto. (CODE_FOR_lsx_vabsd_h): Ditto. (CODE_FOR_lsx_vabsd_w): Ditto. (CODE_FOR_lsx_vabsd_d): Ditto. (CODE_FOR_lsx_vabsd_bu): Ditto. (CODE_FOR_lsx_vabsd_hu): Ditto. (CODE_FOR_lsx_vabsd_wu): Ditto. (CODE_FOR_lsx_vabsd_du): Ditto. (CODE_FOR_lsx_vftint_w_s): Ditto. (CODE_FOR_lsx_vftint_l_d): Ditto. (CODE_FOR_lsx_vftint_wu_s): Ditto. (CODE_FOR_lsx_vftint_lu_d): Ditto. (CODE_FOR_lsx_vandn_v): Ditto. (CODE_FOR_lsx_vorn_v): Ditto. (CODE_FOR_lsx_vneg_b): Ditto. (CODE_FOR_lsx_vneg_h): Ditto. (CODE_FOR_lsx_vneg_w): Ditto. (CODE_FOR_lsx_vneg_d): Ditto. (CODE_FOR_lsx_vshuf4i_d): Ditto. (CODE_FOR_lsx_vbsrl_v): Ditto. (CODE_FOR_lsx_vbsll_v): Ditto. (CODE_FOR_lsx_vfmadd_s): Ditto. (CODE_FOR_lsx_vfmadd_d): Ditto. (CODE_FOR_lsx_vfmsub_s): Ditto. (CODE_FOR_lsx_vfmsub_d): Ditto. (CODE_FOR_lsx_vfnmadd_s): Ditto. (CODE_FOR_lsx_vfnmadd_d): Ditto. (CODE_FOR_lsx_vfnmsub_s): Ditto. (CODE_FOR_lsx_vfnmsub_d): Ditto. (CODE_FOR_lsx_vmuh_b): Ditto. (CODE_FOR_lsx_vmuh_h): Ditto. (CODE_FOR_lsx_vmuh_w): Ditto. (CODE_FOR_lsx_vmuh_d): Ditto. (CODE_FOR_lsx_vmuh_bu): Ditto. (CODE_FOR_lsx_vmuh_hu): Ditto. (CODE_FOR_lsx_vmuh_wu): Ditto. (CODE_FOR_lsx_vmuh_du): Ditto. (CODE_FOR_lsx_vsllwil_h_b): Ditto. (CODE_FOR_lsx_vsllwil_w_h): Ditto. (CODE_FOR_lsx_vsllwil_d_w): Ditto. (CODE_FOR_lsx_vsllwil_hu_bu): Ditto. (CODE_FOR_lsx_vsllwil_wu_hu): Ditto. (CODE_FOR_lsx_vsllwil_du_wu): Ditto. (CODE_FOR_lsx_vssran_b_h): Ditto. (CODE_FOR_lsx_vssran_h_w): Ditto. (CODE_FOR_lsx_vssran_w_d): Ditto. (CODE_FOR_lsx_vssran_bu_h): Ditto. (CODE_FOR_lsx_vssran_hu_w): Ditto. (CODE_FOR_lsx_vssran_wu_d): Ditto. (CODE_FOR_lsx_vssrarn_b_h): Ditto. (CODE_FOR_lsx_vssrarn_h_w): Ditto. (CODE_FOR_lsx_vssrarn_w_d): Ditto. (CODE_FOR_lsx_vssrarn_bu_h): Ditto. (CODE_FOR_lsx_vssrarn_hu_w): Ditto. (CODE_FOR_lsx_vssrarn_wu_d): Ditto. (CODE_FOR_lsx_vssrln_bu_h): Ditto. (CODE_FOR_lsx_vssrln_hu_w): Ditto. (CODE_FOR_lsx_vssrln_wu_d): Ditto. (CODE_FOR_lsx_vssrlrn_bu_h): Ditto. (CODE_FOR_lsx_vssrlrn_hu_w): Ditto. (CODE_FOR_lsx_vssrlrn_wu_d): Ditto. (loongarch_builtin_vector_type): Ditto. (loongarch_build_cvpointer_type): Ditto. (LARCH_ATYPE_CVPOINTER): Ditto. (LARCH_ATYPE_BOOLEAN): Ditto. (LARCH_ATYPE_V2SF): Ditto. (LARCH_ATYPE_V2HI): Ditto. (LARCH_ATYPE_V2SI): Ditto. (LARCH_ATYPE_V4QI): Ditto. (LARCH_ATYPE_V4HI): Ditto. (LARCH_ATYPE_V8QI): Ditto. (LARCH_ATYPE_V2DI): Ditto. (LARCH_ATYPE_V4SI): Ditto. (LARCH_ATYPE_V8HI): Ditto. (LARCH_ATYPE_V16QI): Ditto. (LARCH_ATYPE_V2DF): Ditto. (LARCH_ATYPE_V4SF): Ditto. (LARCH_ATYPE_V4DI): Ditto. (LARCH_ATYPE_V8SI): Ditto. (LARCH_ATYPE_V16HI): Ditto. (LARCH_ATYPE_V32QI): Ditto. (LARCH_ATYPE_V4DF): Ditto. (LARCH_ATYPE_V8SF): Ditto. (LARCH_ATYPE_UV2DI): Ditto. (LARCH_ATYPE_UV4SI): Ditto. (LARCH_ATYPE_UV8HI): Ditto. (LARCH_ATYPE_UV16QI): Ditto. (LARCH_ATYPE_UV4DI): Ditto. (LARCH_ATYPE_UV8SI): Ditto. (LARCH_ATYPE_UV16HI): Ditto. (LARCH_ATYPE_UV32QI): Ditto. (LARCH_ATYPE_UV2SI): Ditto. (LARCH_ATYPE_UV4HI): Ditto. (LARCH_ATYPE_UV8QI): Ditto. (loongarch_builtin_vectorized_function): Ditto. (LARCH_GET_BUILTIN): Ditto. (loongarch_expand_builtin_insn): Ditto. (loongarch_expand_builtin_lsx_test_branch): Ditto. (loongarch_expand_builtin): Ditto. * config/loongarch/loongarch-ftypes.def (1): Ditto. (2): Ditto. (3): Ditto. (4): Ditto. * config/loongarch/lsxintrin.h: New file.
2023-09-05LoongArch: support loongarch*-elf targetYang Yujie1-1/+14
gcc/ChangeLog: * config.gcc: add loongarch*-elf target. * config/loongarch/elf.h: New file. Link against newlib by default. libgcc/ChangeLog: * config.host: add loongarch*-elf target.
2023-09-05LoongArch: add new configure option --with-strict-align-libYang Yujie1-1/+15
LoongArch processors may not support memory accesses without natural alignments. Building libraries with -mstrict-align may help with toolchain binary compatiblity and performance on these implementations (e.g. Loongson 2K1000LA). No significant performance degredation is observed on current mainstream LoongArch processors when the option is enabled. gcc/ChangeLog: * config.gcc: use -mstrict-align for building libraries if --with-strict-align-lib is given. * doc/install.texi: likewise.
2023-09-05LoongArch: improved target configuration interfaceYang Yujie1-173/+206
The configure script and the GCC driver are updated so that it is easier to customize and control GCC builds for targeting different LoongArch implementations. * Make --with-abi obsolete, since it might cause different default ABI under the same target triplet, which is undesirable. The default ABI is now purely decided by the target triplet. * Support options for LoongArch SIMD extensions: new configure options --with-simd={none,lsx,lasx}; new compiler option -msimd={none,lsx,lasx}; new driver options -m[no]-l[a]sx. * Enforce the priority of configuration paths (for <parm>={fpu,tune,simd}): -m<parm> > -march-implied > --with-<parm> > --with-arch-implied. * Allow the user to control the compiler options used when building GCC libraries for each multilib variant via --with-multilib-list and --with-multilib-default. This could become more useful when we have 32-bit support later. Example 1: the following configure option --with-multilib-list=lp64d/la464/mno-strict-align/msimd=lsx,lp64s/mfpu=32 | | | | -mabi=ABI -march=ARCH a list of other options (mandatory) (optional) (optional) builds two sets of libraries: 1. lp64d/base ABI (built with "-march=la464 -mno-strict-align -msimd=lsx") 2. lp64s/base ABI (built with "-march=abi-default -mfpu=32") Example 2: the following 3 configure options --with-arch=loongarch64 --with-multilib-list=lp64d,lp64f,lp64s/la464 --with-multilib-default=fixed/mno-strict-align/mfpu=64 | | | -march=ARCH a list of other options (optional) (optional) is equivalent to (in terms of building libraries): --with-multilib-list=\ lp64d/loongarch64/mno-strict-align/mfpu=64,\ lp64f/loongarch64/mno-strict-align/mfpu=64,\ lp64s/la464 Note: 1. the GCC driver and compiler proper does not support "-march=fixed". "fixed" that appear here acts as a placeholder for "use whatever ARCH in --with-arch=ARCH" (or the default value of --with-arch=ARCH if --with-arch is not explicitly configured). 2. if the ARCH part is omitted, "-march=abi-default" is used for building all library variants, which practically means enabling the minimal ISA features that can support the given ABI. ChangeLog: * config-ml.in: Do not build the multilib library variant that is duplicate with the toplevel one. gcc/ChangeLog: * config.gcc: Make --with-abi= obsolete, decide the default ABI with target triplet. Allow specifying multilib library build options with --with-multilib-list and --with-multilib-default. * config/loongarch/t-linux: Likewise. * config/loongarch/genopts/loongarch-strings: Likewise. * config/loongarch/loongarch-str.h: Likewise. * doc/install.texi: Likewise. * config/loongarch/genopts/loongarch.opt.in: Introduce -m[no-]l[a]sx options. Only process -m*-float and -m[no-]l[a]sx in the GCC driver. * config/loongarch/loongarch.opt: Likewise. * config/loongarch/la464.md: Likewise. * config/loongarch/loongarch-c.cc: Likewise. * config/loongarch/loongarch-cpu.cc: Likewise. * config/loongarch/loongarch-cpu.h: Likewise. * config/loongarch/loongarch-def.c: Likewise. * config/loongarch/loongarch-def.h: Likewise. * config/loongarch/loongarch-driver.cc: Likewise. * config/loongarch/loongarch-driver.h: Likewise. * config/loongarch/loongarch-opts.cc: Likewise. * config/loongarch/loongarch-opts.h: Likewise. * config/loongarch/loongarch.cc: Likewise. * doc/invoke.texi: Likewise.
2023-08-31RISC-V: Add Vector cost model framework for RVVJuzhe-Zhong1-1/+1
Hi, currently RVV vectorization only support picking LMUL according to compile option --param=riscv-autovec-lmul= which is no ideal. Compiler should be able to pick optimal LMUL/vectorization factor to vectorize the loop according to the loop_vec_info and SSA-based register pressure analysis. Now, I figure out current GCC cost model provide the approach that we can choose LMUL/vectorization factor by adjusting the COST. This patch is just add the minimum COST model framework which is still applying the default cost model (No vector codes changed from before). Regression all pased and no difference. gcc/ChangeLog: * config.gcc: Add vector cost model framework for RVV. * config/riscv/riscv.cc (riscv_vectorize_create_costs): Ditto. (TARGET_VECTORIZE_CREATE_COSTS): Ditto. * config/riscv/t-riscv: Ditto. * config/riscv/riscv-vector-costs.cc: New file. * config/riscv/riscv-vector-costs.h: New file.
2023-08-03bpf: Implementation of BPF CO-RE builtinsCupertino Miranda1-2/+2
This patch updates the support for the BPF CO-RE builtins __builtin_preserve_access_index and __builtin_preserve_field_info, and adds support for the CO-RE builtins __builtin_btf_type_id, __builtin_preserve_type_info and __builtin_preserve_enum_value. These CO-RE relocations are now converted to __builtin_core_reloc which abstracts all of the original builtins in a polymorphic relocation specific builtin. The builtin processing is now split in 2 stages, the first (pack) is executed right after the front-end and the second (process) right before the asm output. In expand pass the __builtin_core_reloc is converted to a unspec:UNSPEC_CORE_RELOC rtx entry. The data required to process the builtin is now collected in the packing stage (after front-end), not allowing the compiler to optimize any of the relevant information required to compose the relocation when necessary. At expansion, that information is recovered and CTF/BTF is queried to construct the information that will be used in the relocation. At this point the relocation is added to specific section and the builtin is expanded to the expected default value for the builtin. In order to process __builtin_preserve_enum_value, it was necessary to hook the front-end to collect the original enum value reference. This is needed since the parser folds all the enum values to its integer_cst representation. More details can be found within the core-builtins.cc. Regtested in host x86_64-linux-gnu and target bpf-unknown-none. gcc/ChangeLog: PR target/107844 PR target/107479 PR target/107480 PR target/107481 * config.gcc: Added core-builtins.cc and .o files. * config/bpf/bpf-passes.def: Removed file. * config/bpf/bpf-protos.h (bpf_add_core_reloc, bpf_replace_core_move_operands): New prototypes. * config/bpf/bpf.cc (enum bpf_builtins, is_attr_preserve_access, maybe_make_core_relo, bpf_core_field_info, bpf_core_compute, bpf_core_get_index, bpf_core_new_decl, bpf_core_walk, bpf_is_valid_preserve_field_info_arg, is_attr_preserve_access, handle_attr_preserve, pass_data_bpf_core_attr, pass_bpf_core_attr): Removed. (def_builtin, bpf_expand_builtin, bpf_resolve_overloaded_builtin): Changed. * config/bpf/bpf.md (define_expand mov<MM:mode>): Changed. (mov_reloc_core<mode>): Added. * config/bpf/core-builtins.cc (struct cr_builtin, enum cr_decision struct cr_local, struct cr_final, struct core_builtin_helpers, enum bpf_plugin_states): Added types. (builtins_data, core_builtin_helpers, core_builtin_type_defs): Added variables. (allocate_builtin_data, get_builtin-data, search_builtin_data, remove_parser_plugin, compare_same_kind, compare_same_ptr_expr, compare_same_ptr_type, is_attr_preserve_access, core_field_info, bpf_core_get_index, compute_field_expr, pack_field_expr_for_access_index, pack_field_expr_for_preserve_field, process_field_expr, pack_enum_value, process_enum_value, pack_type, process_type, bpf_require_core_support, make_core_relo, read_kind, kind_access_index, kind_preserve_field_info, kind_enum_value, kind_type_id, kind_preserve_type_info, get_core_builtin_fndecl_for_type, bpf_handle_plugin_finish_type, bpf_init_core_builtins, construct_builtin_core_reloc, bpf_resolve_overloaded_core_builtin, bpf_expand_core_builtin, bpf_add_core_reloc, bpf_replace_core_move_operands): Added functions. * config/bpf/core-builtins.h (enum bpf_builtins): Added. (bpf_init_core_builtins, bpf_expand_core_builtin, bpf_resolve_overloaded_core_builtin): Added functions. * config/bpf/coreout.cc (struct bpf_core_extra): Added. (bpf_core_reloc_add, output_asm_btfext_core_reloc): Changed. * config/bpf/coreout.h (bpf_core_reloc_add) Changed prototype. * config/bpf/t-bpf: Added core-builtins.o. * doc/extend.texi: Added documentation for new BPF builtins.
2023-08-03Introduce -msmp to select /lib_smp/ on ppc-vx6Alexandre Oliva1-1/+1
The .spec files used for linking on ppc-vx6, when the rtp-smp runtime is selected, add -L flags for /lib_smp/ and /lib/. There was a problem, though: although /lib_smp/ and /lib/ were to be searched in this order, and the specs files do that correctly, the compiler would search /lib/ first regardless, because STARTFILE_PREFIX_SPEC said so, and specs files cannot override that. With this patch, we arrange for the presence of -msmp to affect STARTFILE_PREFIX_SPEC, so that the compiler searches /lib_smp/ rather than /lib/ for crt files. A separate patch for GNAT ensures that when the rtp-smp runtime is selected, -msmp is passed to the compiler driver for linking, along with the --specs flags. for gcc/ChangeLog * config/vxworks-smp.opt: New. Introduce -msmp. * config.gcc: Enable it on powerpc* vxworks prior to 7r*. * config/rs6000/vxworks.h (STARTFILE_PREFIX_SPEC): Choose lib_smp when -msmp is present in the command line. * doc/invoke.texi: Document it.
2023-07-17Initial Lunar Lake, Arrow Lake and Arrow Lake S SupportMo, Zewei1-1/+2
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Lunar Lake, Arrow Lake and Arrow Lake S. * common/config/i386/i386-common.cc: (processor_name): Add arrowlake. (processor_alias_table): Add arrow lake, arrow lake s and lunar lake. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add INTEL_COREI7_ARROWLAKE and INTEL_COREI7_ARROWLAKE_S. * config.gcc: Add -march=arrowlake and -march=arrowlake-s. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle arrowlake-s. * config/i386/i386-c.cc (ix86_target_macros_internal): Add arrowlake. * config/i386/i386-options.cc (m_ARROWLAKE): New. (processor_cost_table): Add arrowlake. * config/i386/i386.h (enum processor_type): Add PROCESSOR_ARROWLAKE. * config/i386/x86-tune.def: Add m_ARROWLAKE. * doc/extend.texi: Add arrowlake and arrowlake-s. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add arrowlake and arrowlake-s. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-07-17Support Intel SM4Haochen Jiang1-1/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detech SM4. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET, OPTION_MASK_ISA2_SM4_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM4. (ix86_handle_option): Handle -msm4. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SM4. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for sm4. * config.gcc: Add sm4intrin.h. * config/i386/cpuid.h (bit_SM4): New. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SM4__. * config/i386/i386-isa.def (SM4): Add DEF_PTA(SM4). * config/i386/i386-options.cc (isa2_opts): Add -msm4. (ix86_valid_target_attribute_inner_p): Handle sm4. * config/i386/i386.opt: Add option -msm4. * config/i386/immintrin.h: Include sm4intrin.h * config/i386/sse.md (vsm4key4_<mode>): New define insn. (vsm4rnds4_<mode>): Ditto. * doc/extend.texi: Document sm4. * doc/invoke.texi: Document -msm4. * doc/sourcebuild.texi: Document target sm4. * config/i386/sm4intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msm4. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msm4. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sm4. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sm4): New. * gcc.target/i386/sm4-1.c: New test. * gcc.target/i386/sm4-check.h: Ditto. * gcc.target/i386/sm4key4-2.c: Ditto. * gcc.target/i386/sm4rnds4-2.c: Ditto.
2023-07-17Support Intel SHA512Haochen Jiang1-1/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SHA512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET, OPTION_MASK_ISA2_SHA512_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SHA512. (ix86_handle_option): Handle -msha512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SHA512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for sha512. * config.gcc: Add sha512intrin.h. * config/i386/cpuid.h (bit_SHA512): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SHA512__. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle V4DI_FTYPE_V4DI_V4DI_V2DI and V4DI_FTYPE_V4DI_V2DI. * config/i386/i386-isa.def (SHA512): Add DEF_PTA(SHA512). * config/i386/i386-options.cc (isa2_opts): Add -msha512. (ix86_valid_target_attribute_inner_p): Handle sha512. * config/i386/i386.opt: Add option -msha512. * config/i386/immintrin.h: Include sha512intrin.h. * config/i386/sse.md (vsha512msg1): New define insn. (vsha512msg2): Ditto. (vsha512rnds2): Ditto. * doc/extend.texi: Document sha512. * doc/invoke.texi: Document -msha512. * doc/sourcebuild.texi: Document target sha512. * config/i386/sha512intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msha512. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msha512. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sha512. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sha512): New. * gcc.target/i386/sha512-1.c: New test. * gcc.target/i386/sha512-check.h: Ditto. * gcc.target/i386/sha512msg1-2.c: Ditto. * gcc.target/i386/sha512msg2-2.c: Ditto. * gcc.target/i386/sha512rnds2-2.c: Ditto.
2023-07-17Support Intel SM3Haochen Jiang1-1/+2
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SM3. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET, OPTION_MASK_ISA2_SM3_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM3. (ix86_handle_option): Handle -msm3. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SM3. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for SM3. * config.gcc: Add sm3intrin.h * config/i386/cpuid.h (bit_SM3): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SM3__. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle V4SI_FTYPE_V4SI_V4SI_V4SI_INT. * config/i386/i386-isa.def (SM3): Add DEF_PTA(SM3). * config/i386/i386-options.cc (isa2_opts): Add -msm3. (ix86_valid_target_attribute_inner_p): Handle sm3. * config/i386/i386.opt: Add option -msm3. * config/i386/immintrin.h: Include sm3intrin.h. * config/i386/sse.md (vsm3msg1): New define insn. (vsm3msg2): Ditto. (vsm3rnds2): Ditto. * doc/extend.texi: Document sm3. * doc/invoke.texi: Document -msm3. * doc/sourcebuild.texi: Document target sm3. * config/i386/sm3intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msm3. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-1.c: Add new define for immediate. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msm3. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sm3. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sm3): New. * gcc.target/i386/sm3-1.c: New test. * gcc.target/i386/sm3-check.h: Ditto. * gcc.target/i386/sm3msg1-2.c: Ditto. * gcc.target/i386/sm3msg2-2.c: Ditto. * gcc.target/i386/sm3rnds2-2.c: Ditto.
2023-07-17Support Intel AVX-VNNI-INT16Kong Lingling1-1/+1
gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT16_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto. (ix86_handle_option): Handle -mavxvnniint16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNIINT16. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxvnniint16. * config.gcc: Add avxvnniint16.h. * config/i386/avxvnniint16intrin.h: New file. * config/i386/cpuid.h (bit_AVXVNNIINT16): New. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXVNNIINT16__. * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint16. (ix86_valid_target_attribute_inner_p): Handle avxvnniint16intrin.h. * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT16). * config/i386/i386.opt: Add option -mavxvnniint16. * config/i386/immintrin.h: Include avxvnniint16.h. * config/i386/sse.md (vpdp<vpdpwprodtype>_<mode>): New define_insn. * doc/extend.texi: Document avxvnniint16. * doc/invoke.texi: Document -mavxvnniint16. * doc/sourcebuild.texi: Document target avxvnniint16. gcc/testsuite/ChangeLog * g++.dg/other/i386-2.C: Add -mavxvnniint16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-check.h: Add avxvnniint16 check. * gcc.target/i386/sse-12.c: Add -mavxvnniint16. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxvnniint16): New. * gcc.target/i386/avxvnniint16-1.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwusd-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwusds-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwsud-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwsuds-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwuud-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwuuds-2.c: Ditto. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2023-07-12Initial Granite Rapids D SupportMo, Zewei1-1/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Granite Rapids D. * common/config/i386/i386-common.cc: (processor_alias_table): Add graniterapids-d. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add INTEL_COREI7_GRANITERAPIDS_D. * config.gcc: Add -march=graniterapids-d. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle graniterapids-d. * config/i386/i386.h: (PTA_GRANITERAPIDS_D): New. * doc/extend.texi: Add graniterapids-d. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add graniterapids-d. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-05-18gcc: Fix nonportable shell syntax in "test" and "[" commands [PR105831]Jonathan Wakely1-1/+1
POSIX sh does not support the == for string comparisons, use = instead. The gen_directive_tests script uses a bash shebang so == does work, but there's no reason this script can't just use the more portable form anyway. PR bootstrap/105831 gcc/ChangeLog: * config.gcc: Use = operator instead of ==. gcc/testsuite/ChangeLog: * gcc.test-framework/gen_directive_tests: Use = operator instead of ==.
2023-05-03arm: [MVE intrinsics] Add new frameworkChristophe Lyon1-1/+1
This patch introduces the new MVE intrinsics framework, heavily inspired by the SVE one in the aarch64 port. Like the MVE intrinsic types implementation, the intrinsics framework defines functions via a new pragma in arm_mve.h. A boolean parameter is used to pass true when __ARM_MVE_PRESERVE_USER_NAMESPACE is defined, and false when it is not, allowing for non-prefixed intrinsic functions to be conditionally defined. Future patches will build on this framework by adding new intrinsic functions and adding the features needed to support them. Differences compared to the aarch64/SVE port include: - when present, the predicate argument is the last one with MVE (the first one with SVE) - when using merging predicates ("_m" suffix), the "inactive" argument (if any) is inserted in the first position - when using merging predicates ("_m" suffix), some function do not have the "inactive" argument, so we maintain an exception-list - MVE intrinsics dealing with floating-point require the FP extension, while SVE may support different extensions - regarding global state, MVE does not have any prefetch intrinsic, so we do not need a flag for this - intrinsic names can be prefixed with "__arm", depending on whether preserve_user_namespace is true or false - parse_signature: the maximum number of arguments is now a parameter, this helps detecting an overflow with a new assert. - suffixes and overloading can be controlled using explicit_mode_suffix_p and skip_overload_p in addition to explicit_type_suffix_p At this implemtation stage, there are some limitations compared to aarch64/SVE, which are removed later in the series: - "offset" mode is not supported yet - gimple folding is not implemented 2022-09-08 Murray Steele <murray.steele@arm.com> Christophe Lyon <christophe.lyon@arm.com> gcc/ChangeLog: * config.gcc: Add arm-mve-builtins-base.o and arm-mve-builtins-shapes.o to extra_objs. * config/arm/arm-builtins.cc (arm_builtin_decl): Handle MVE builtin numberspace. (arm_expand_builtin): Likewise (arm_check_builtin_call): Likewise (arm_describe_resolver): Likewise. * config/arm/arm-builtins.h (enum resolver_ident): Add arm_mve_resolver. * config/arm/arm-c.cc (arm_pragma_arm): Handle new pragma. (arm_resolve_overloaded_builtin): Handle MVE builtins. (arm_register_target_pragmas): Register arm_check_builtin_call. * config/arm/arm-mve-builtins.cc (class registered_function): New class. (struct registered_function_hasher): New struct. (pred_suffixes): New table. (mode_suffixes): New table. (type_suffix_info): New table. (TYPES_float16): New. (TYPES_all_float): New. (TYPES_integer_8): New. (TYPES_integer_8_16): New. (TYPES_integer_16_32): New. (TYPES_integer_32): New. (TYPES_signed_16_32): New. (TYPES_signed_32): New. (TYPES_all_signed): New. (TYPES_all_unsigned): New. (TYPES_all_integer): New. (TYPES_all_integer_with_64): New. (DEF_VECTOR_TYPE): New. (DEF_DOUBLE_TYPE): New. (DEF_MVE_TYPES_ARRAY): New. (all_integer): New. (all_integer_with_64): New. (float16): New. (all_float): New. (all_signed): New. (all_unsigned): New. (integer_8): New. (integer_8_16): New. (integer_16_32): New. (integer_32): New. (signed_16_32): New. (signed_32): New. (register_vector_type): Use void_type_node for mve.fp-only types when mve.fp is not enabled. (register_builtin_tuple_types): Likewise. (handle_arm_mve_h): New function.. (matches_type_p): Likewise.. (report_out_of_range): Likewise. (report_not_enum): Likewise. (report_missing_float): Likewise. (report_non_ice): Likewise. (check_requires_float): Likewise. (function_instance::hash): Likewise (function_instance::call_properties): Likewise. (function_instance::reads_global_state_p): Likewise. (function_instance::modifies_global_state_p): Likewise. (function_instance::could_trap_p): Likewise. (function_instance::has_inactive_argument): Likewise. (registered_function_hasher::hash): Likewise. (registered_function_hasher::equal): Likewise. (function_builder::function_builder): Likewise. (function_builder::~function_builder): Likewise. (function_builder::append_name): Likewise. (function_builder::finish_name): Likewise. (function_builder::get_name): Likewise. (add_attribute): Likewise. (function_builder::get_attributes): Likewise. (function_builder::add_function): Likewise. (function_builder::add_unique_function): Likewise. (function_builder::add_overloaded_function): Likewise. (function_builder::add_overloaded_functions): Likewise. (function_builder::register_function_group): Likewise. (function_call_info::function_call_info): Likewise. (function_resolver::function_resolver): Likewise. (function_resolver::get_vector_type): Likewise. (function_resolver::get_scalar_type_name): Likewise. (function_resolver::get_argument_type): Likewise. (function_resolver::scalar_argument_p): Likewise. (function_resolver::report_no_such_form): Likewise. (function_resolver::lookup_form): Likewise. (function_resolver::resolve_to): Likewise. (function_resolver::infer_vector_or_tuple_type): Likewise. (function_resolver::infer_vector_type): Likewise. (function_resolver::require_vector_or_scalar_type): Likewise. (function_resolver::require_vector_type): Likewise. (function_resolver::require_matching_vector_type): Likewise. (function_resolver::require_derived_vector_type): Likewise. (function_resolver::require_derived_scalar_type): Likewise. (function_resolver::require_integer_immediate): Likewise. (function_resolver::require_scalar_type): Likewise. (function_resolver::check_num_arguments): Likewise. (function_resolver::check_gp_argument): Likewise. (function_resolver::finish_opt_n_resolution): Likewise. (function_resolver::resolve_unary): Likewise. (function_resolver::resolve_unary_n): Likewise. (function_resolver::resolve_uniform): Likewise. (function_resolver::resolve_uniform_opt_n): Likewise. (function_resolver::resolve): Likewise. (function_checker::function_checker): Likewise. (function_checker::argument_exists_p): Likewise. (function_checker::require_immediate): Likewise. (function_checker::require_immediate_enum): Likewise. (function_checker::require_immediate_range): Likewise. (function_checker::check): Likewise. (gimple_folder::gimple_folder): Likewise. (gimple_folder::fold): Likewise. (function_expander::function_expander): Likewise. (function_expander::direct_optab_handler): Likewise. (function_expander::get_fallback_value): Likewise. (function_expander::get_reg_target): Likewise. (function_expander::add_output_operand): Likewise. (function_expander::add_input_operand): Likewise. (function_expander::add_integer_operand): Likewise. (function_expander::generate_insn): Likewise. (function_expander::use_exact_insn): Likewise. (function_expander::use_unpred_insn): Likewise. (function_expander::use_pred_x_insn): Likewise. (function_expander::use_cond_insn): Likewise. (function_expander::map_to_rtx_codes): Likewise. (function_expander::expand): Likewise. (resolve_overloaded_builtin): Likewise. (check_builtin_call): Likewise. (gimple_fold_builtin): Likewise. (expand_builtin): Likewise. (gt_ggc_mx): Likewise. (gt_pch_nx): Likewise. (gt_pch_nx): Likewise. * config/arm/arm-mve-builtins.def(s8): Define new type suffix. (s16): Likewise. (s32): Likewise. (s64): Likewise. (u8): Likewise. (u16): Likewise. (u32): Likewise. (u64): Likewise. (f16): Likewise. (f32): Likewise. (n): New mode. (offset): New mode. * config/arm/arm-mve-builtins.h (MAX_TUPLE_SIZE): New constant. (CP_READ_FPCR): Likewise. (CP_RAISE_FP_EXCEPTIONS): Likewise. (CP_READ_MEMORY): Likewise. (CP_WRITE_MEMORY): Likewise. (enum units_index): New enum. (enum predication_index): New. (enum type_class_index): New. (enum mode_suffix_index): New enum. (enum type_suffix_index): New. (struct mode_suffix_info): New struct. (struct type_suffix_info): New. (struct function_group_info): Likewise. (class function_instance): Likewise. (class registered_function): Likewise. (class function_builder): Likewise. (class function_call_info): Likewise. (class function_resolver): Likewise. (class function_checker): Likewise. (class gimple_folder): Likewise. (class function_expander): Likewise. (get_mve_pred16_t): Likewise. (find_mode_suffix): New function. (class function_base): Likewise. (class function_shape): Likewise. (function_instance::operator==): New function. (function_instance::operator!=): Likewise. (function_instance::vectors_per_tuple): Likewise. (function_instance::mode_suffix): Likewise. (function_instance::type_suffix): Likewise. (function_instance::scalar_type): Likewise. (function_instance::vector_type): Likewise. (function_instance::tuple_type): Likewise. (function_instance::vector_mode): Likewise. (function_call_info::function_returns_void_p): Likewise. (function_base::call_properties): Likewise. * config/arm/arm-protos.h (enum arm_builtin_class): Add ARM_BUILTIN_MVE. (handle_arm_mve_h): New. (resolve_overloaded_builtin): New. (check_builtin_call): New. (gimple_fold_builtin): New. (expand_builtin): New. * config/arm/arm.cc (TARGET_GIMPLE_FOLD_BUILTIN): Define as arm_gimple_fold_builtin. (arm_gimple_fold_builtin): New function. * config/arm/arm_mve.h: Use new arm_mve.h pragma. * config/arm/predicates.md (arm_any_register_operand): New predicate. * config/arm/t-arm: (arm-mve-builtins.o): Add includes. (arm-mve-builtins-shapes.o): New target. (arm-mve-builtins-base.o): New target. * config/arm/arm-mve-builtins-base.cc: New file. * config/arm/arm-mve-builtins-base.def: New file. * config/arm/arm-mve-builtins-base.h: New file. * config/arm/arm-mve-builtins-functions.h: New file. * config/arm/arm-mve-builtins-shapes.cc: New file. * config/arm/arm-mve-builtins-shapes.h: New file. Co-authored-by: Christophe Lyon <christophe.lyon@arm.com
2023-04-29add glibc-stdint.h to vax and lm32 linux target (PR target/105525)Mikael Pettersson1-2/+2
PR target/105525 is a build regression for the vax and lm32 linux targets present in gcc-12/13/head, where the builds fail due to unsatisfied references to __INTPTR_TYPE__ and __UINTPTR_TYPE__, caused by these two targets failing to provide glibc-stdint.h. Fixed thusly, tested by building crosses, which now succeeds. Ok for trunk? (Note I don't have commit rights.) PR target/105525 gcc/ * config.gcc (vax-*-linux*): Add glibc-stdint.h. (lm32-*-uclinux*): Likewise.
2023-04-10Support Intel AMX-COMPLEXHaochen Jiang1-1/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-COMPLEX. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_COMPLEX_SET, OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New. (ix86_handle_option): Handle -mamx-complex. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_COMPLEX. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-complex. * config.gcc: Add amxcomplexintrin.h. * config/i386/cpuid.h (bit_AMX_COMPLEX): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_COMPLEX__. * config/i386/i386-isa.def (AMX_COMPLEX): Add DEF_PTA(AMX_COMPLEX). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-complex. * config/i386/i386.opt: Add option -mamx-complex. * config/i386/immintrin.h: Include amxcomplexintrin.h. * doc/extend.texi: Document amx-complex. * doc/invoke.texi: Document -mamx-complex. * doc/sourcebuild.texi: Document target amx-complex. * config/i386/amxcomplexintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-complex. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add cpu check for AMX-COMPLEX. * gcc.target/i386/amx-helper.h: Add amx-complex support. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-complex. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-complex. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_complex): New. * gcc.target/i386/amxcomplex-asmatt-1.c: New test. * gcc.target/i386/amxcomplex-asmintel-1.c: Ditto. * gcc.target/i386/amxcomplex-cmmimfp16ps-2.c: Ditto. * gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c: Ditto.
2023-03-15riscv: thead: Add support for the XTheadMemPair ISA extensionChristoph Müllner1-0/+1
The XTheadMemPair ISA extension allows to pair two loads or stores: * th.ldd (2x LD) * th.lwd (2x LW) * th.lwud (2x LWU) * th.sdd (2x SD) * th.swd (2x SW) The displacement of these instructions is quite limited: * Displacement := imm2 << shamt * imm2 is a 2-bit unsigned value {0..3} * shamt is 4 for th.ldd/th.sdd and 3 otherwise But even with this small displacement we can identify many candidates. The merge of the two loads/stores is realized in form of peephole2 passes that support instruction reordering. The CFA expansion (save/restore registers on/from stack) is not processed by the peephole2 pass and, therefore, needs special-treatment. Many ideas of this patch are inspired by similar/equal approaches in other backends. gcc/ChangeLog: * config.gcc: Add thead.o to RISC-V extra_objs. * config/riscv/peephole.md: Add mempair peephole passes. * config/riscv/riscv-protos.h (riscv_split_64bit_move_p): New prototype. (th_mempair_operands_p): Likewise. (th_mempair_order_operands): Likewise. (th_mempair_prepare_save_restore_operands): Likewise. (th_mempair_save_restore_regs): Likewise. (th_mempair_output_move): Likewise. * config/riscv/riscv.cc (riscv_save_reg): Move code. (riscv_restore_reg): Move code. (riscv_for_each_saved_reg): Add code to emit mempair insns. * config/riscv/t-riscv: Add thead.cc. * config/riscv/thead.md (*th_mempair_load_<GPR:mode>2): New insn. (*th_mempair_store_<GPR:mode>2): Likewise. (*th_mempair_load_extendsidi2): Likewise. (*th_mempair_load_zero_extendsidi2): Likewise. * config/riscv/thead.cc: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadmempair-1.c: New test. * gcc.target/riscv/xtheadmempair-2.c: New test. * gcc.target/riscv/xtheadmempair-3.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-03-10cygwin: Don't try to support multilibs [PR107998]Jakub Jelinek1-1/+1
As discussed in the PR, t-cygwin-w64 file has been introduced in 2013 and has one important problem, two different multilib options -m64 and -m32, but MULTILIB_DIRNAMES with just one word in it. Before the genmultilib sanity checking was added, my understanding is that this essentially resulted in effective --disable-multilib, $ gcc -print-multi-lib .; ;@m32 $ gcc -print-multi-directory . $ gcc -print-multi-directory -m64 . $ gcc -print-multi-directory -m32 $ gcc -print-multi-os-directory ../lib $ gcc -print-multi-os-directory -m64 ../lib $ gcc -print-multi-os-directory -m32 ../lib32 and because of the way e.g. config-ml.in operates multidirs= for i in `${CC-gcc} --print-multi-lib 2>/dev/null`; do dir=`echo $i | sed -e 's/;.*$//'` if [ "${dir}" = "." ]; then true else if [ -z "${multidirs}" ]; then multidirs="${dir}" else multidirs="${multidirs} ${dir}" fi fi done dir was . first time (and so nothing was done) and empty second time, multidirs empty too, so multidirs was set to empty like it would be with --disable-multilib. With the added sanity checking the build fails unless --disable-multilib is used in configure (dunno whether people usually configure that way on cygwin). >From what has been said in the PR, multilibs were not meant to be supported and e.g. cygwin headers probably aren't ready for it. So the following patch just removes the file with the (incorrect) multilib stuff instead of fixing it (say by setting MULTILIB_DIRNAMES to 64 32). I have no way to test this though, no Windows around, can anyone please test this? I just would like to get some progress on the P1s we have... 2023-02-22 Jakub Jelinek <jakub@redhat.com> gcc/ChangeLog: PR target/107998 * config.gcc (x86_64-*-cygwin*): Don't add i386/t-cygwin-w64 into $tmake_file. * config/i386/t-cygwin-w64: Remove. Signed-off-by: Jonathan Yong <10walls@gmail.com>
2023-03-02MIPS: Add buildtime option to set msa defaultJunxian Zhu1-2/+17
Add buildtime option to decide whether will compiler build with `-mmsa` option default. gcc/ChangeLog: * config.gcc: add -with-{no-}msa build option. * config/mips/mips.h: Likewise. * doc/install.texi: Likewise. Signed-off-by: Junxian Zhu <zhujunxian@oss.cipunited.com>
2023-02-18LoongArch: Fix multiarch tuple canonizationXi Ruoyao1-7/+7
Multiarch tuple will be coded in file or directory names in multiarch-aware distros, so one ABI should have only one multiarch tuple. For example, "--target=loongarch64-linux-gnu --with-abi=lp64s" and "--target=loongarch64-linux-gnusf" should both set multiarch tuple to "loongarch64-linux-gnusf". Before this commit, "--target=loongarch64-linux-gnu --with-abi=lp64s --disable-multilib" will produce wrong result (loongarch64-linux-gnu). A recent LoongArch psABI revision mandates "loongarch64-linux-gnu" to be used for -mabi=lp64d (instead of "loongarch64-linux-gnuf64") for some non-technical reason [1]. Note that we cannot make "loongarch64-linux-gnuf64" an alias for "loongarch64-linux-gnu" because to implement such an alias, we must create thousands of symlinks in the distro and doing so would be completely unpractical. This commit also aligns GCC with the revision. Tested by building cross compilers with --enable-multiarch and multiple combinations of --target=loongarch64-linux-gnu*, --with-abi=lp64{s,f,d}, and --{enable,disable}-multilib; and run "xgcc --print-multiarch" then manually verify the result with eyesight. [1]: https://github.com/loongson/LoongArch-Documentation/pull/80 gcc/ChangeLog: * config.gcc (triplet_abi): Set its value based on $with_abi, instead of $target. (la_canonical_triplet): Set it after $triplet_abi is set correctly. * config/loongarch/t-linux (MULTILIB_OSDIRNAMES): Make the multiarch tuple for lp64d "loongarch64-linux-gnu" (without "f64" suffix).
2023-02-08arm: Optimize arm-mlib.h header inclusion [pr108505].Srinath Parvathaneni1-1/+2
I have committed a fix [1] into gcc trunk for a build issue mentioned in pr108505 and latter received few upstream comments proposing more robust fix for this issue. In this patch I'm addressing those comments and sending this as a followup patch. gcc/ChangeLog: 2023-01-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com> PR target/108505 * config.gcc (tm_mlib_file): Define new variable.
2023-01-30Add support for x86_64-*-gnu-* targets to build x86_64 gnumach/hurdFlavio Cruz1-1/+4
Tested by building a toolchain and compiling gnumach for x86_64 [1]. This is the basic version without unwind support which I think is only required to implement exceptions. [1] https://github.com/flavioc/cross-hurd/blob/master/bootstrap-kernel.sh. gcc/ChangeLog: * config.gcc: Recognize x86_64-*-gnu* targets and include i386/gnu64.h. * config/i386/gnu64.h: Define configuration for new target including ld.so location. libgcc/ChangeLog: * config.host: Recognize x86_64-*-gnu* targets. * config/i386/gnu-unwind.h: Update to handle __x86_64__ with a TODO for now. Signed-off-by: Flavio Cruz <flaviocruz@gmail.com>
2023-01-30riscv: Enable -fasynchronous-unwind-tables by default on LinuxAndreas Schwab1-0/+1
This follows the example of aarch64. gcc/: * common/config/riscv/riscv-common.cc (riscv_option_optimization_table) [TARGET_DEFAULT_ASYNC_UNWIND_TABLES]: Enable -fasynchronous-unwind-tables and -funwind-tables. * config.gcc (riscv*-*-linux*): Define TARGET_DEFAULT_ASYNC_UNWIND_TABLES.
2023-01-25C-SKY: Fix wrong sysroot suffix when disable multilib.Xianmiao Qu1-1/+6
The SYSROOT_SUFFIX_SPEC works even when multilib is disabled. So when build no-multilib glibc toolchain and the options are not same as MULTILIB_DEFAULTS, the sysroot will specify wrong because the libc will not be installed as such. This bug causes glibc regression test error: https://sourceware.org/pipermail/libc-testresults/2023q1/010706.html The error is: /scratch/jmyers/glibc-bot/install/compilers/csky-linux-gnuabiv2/csky-glibc-linux-gnuabiv2/bin/ld: cannot find -lc: No such file or directory gcc/ * config.gcc(csky-*-linux*): Define CSKY_ENABLE_MULTILIB and only include 'csky/t-csky-linux' when enable multilib. * config/csky/csky-linux-elf.h(SYSROOT_SUFFIX_SPEC): Don't define it when disable multilib.
2023-01-24arm: Fix inclusion of arm-mlib.h header more than once (pr108505).Srinath Parvathaneni1-1/+1
The patch fixes the build issue for arm-none-eabi target configured with --with-multilib-list=aprofile,rmprofile, in which case the header file arm/arm-mlib.h is being included more than once and the toolchain build is failing (PR108505). gcc/ChangeLog: 2023-01-24 Srinath Parvathaneni <srinath.parvathaneni@arm.com> PR target/108505 * config.gcc (tm_file): Move the variable out of loop.
2023-01-23arm: Add pacbti related multilib support for armv8.1-m.main.Srinath Parvathaneni1-0/+1
This patch adds the support for pacbti multlilib linking by making "-mbranch-protection=none" as default multilib option for arm-none-eabi target. Eg 1. If the passed command line flags are (without mbranch-protection): a) -march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto "-mbranch-protection=none" will be used in the multilib matching. Eg 2. If the passed command line flags are (with mbranch-protection): a) -march=armv8.1-m.main+mve+pacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret "-mbranch-protection=standard" will be used in the multilib matching. gcc/ChangeLog: 2023-01-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config.gcc ($tm_file): Update variable. * config/arm/arm-mlib.h: Create new header file. * config/arm/t-rmprofile (MULTI_ARCH_DIRS_RM): Rename mbranch-protection multilib arch directory. (MULTILIB_REUSE): Add multilib reuse rules. (MULTILIB_MATCHES): Add multilib match rules. gcc/testsuite/ChangeLog: 2023-01-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/multilib.exp (multilib_config "rmprofile"): Update tests. * gcc.target/arm/pac-12.c: New test. * gcc.target/arm/pac-13.c: Likewise. * gcc.target/arm/pac-14.c: Likewise.
2023-01-23[PATCH 12/15] arm: implement bti injectionAndrea Corallo1-1/+1
Hi all, this patch enables Branch Target Identification Armv8.1-M Mechanism [1]. This is achieved by using the bti pass made common with Aarch64. The pass iterates through the instructions and adds the necessary BTI instructions at the beginning of every function and at every landing pads targeted by indirect jumps. Best Regards Andrea [1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension> gcc/ChangeLog 2022-04-07 Andrea Corallo <andrea.corallo@arm.com> * config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object. * config/arm/arm-protos.h: Update. * config/arm/aarch-common-protos.h: Declare 'aarch_bti_arch_check'. * config/arm/arm.cc (aarch_bti_enabled) Update. (aarch_bti_j_insn_p, aarch_pac_insn_p, aarch_gen_bti_c) (aarch_gen_bti_j, aarch_bti_arch_check): New functions. * config/arm/arm.md (bti_nop): New insn. * config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'. (aarch-bti-insert.o): New target. * config/arm/unspecs.md (VUNSPEC_BTI_NOP): New unspec. * config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Verify arch compatibility. (gate): Make use of 'aarch_bti_arch_check'. * config/arm/arm-passes.def: New file. * config/aarch64/aarch64.cc (aarch_bti_arch_check): New function. gcc/testsuite/ChangeLog 2022-04-07 Andrea Corallo <andrea.corallo@arm.com> * gcc.target/arm/bti-1.c: New testcase. * gcc.target/arm/bti-2.c: Likewise.
2023-01-23[PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm ↵Andrea Corallo1-1/+1
backend Hi all, this patch splits and restructures the aarch64 bti pass code in order to have it usable by the arm backend as well. These changes have no functional impact. Best Regards Andrea gcc/Changelog * config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into 'aarch-bti-insert.o'. * config/aarch64/aarch64-protos.h: Remove 'aarch64_bti_enabled' proto. * config/aarch64/aarch64.cc (aarch_bti_enabled): Rename. (aarch_bti_j_insn_p, aarch_pac_insn_p): New functions. (aarch64_output_mi_thunk) (aarch64_print_patchable_function_entry) (aarch64_file_end_indicate_exec_stack): Update renamed function calls to renamed functions. * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise. * config/aarch64/t-aarch64 (aarch-bti-insert.o): Update target. * config/aarch64/aarch64-bti-insert.cc: Delete. * config/arm/aarch-bti-insert.cc: New file including and generalizing code from aarch64-bti-insert.cc. * config/arm/aarch-common-protos.h: Update.
2023-01-15C-SKY: Support --with-float=softfp in configuration.Xianmiao Qu1-1/+1
Missed it before, it needs to be used when compiling non-multilib. gcc/ * config.gcc (csky-*-*): Support --with-float=softfp.
2023-01-02Update copyright years.Jakub Jelinek1-1/+1
2022-12-19RISC-V: Support VSETVL PASS for RVV supportJu-Zhe Zhong1-1/+1
This patch is to support VSETVL PASS for RVV support. 1.The optimization and performance is guaranteed LCM (Lazy code motion). 2.Base on RTL_SSA framework to gain better optimization chances. 3.Also we do VL/VTYPE, demand information backward propagation across blocks by RTL_SSA reverse order in CFG. 4.It has been well and fully tested by about 200+ testcases for VLMAX AVL situation (Only for VLMAX since we don't have an intrinsics to test non-VLMAX). 5.Will support AVL model in the next patch. gcc/ChangeLog: * config.gcc: Add riscv-vsetvl.o. * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Add VSETVL PASS location. * config/riscv/riscv-protos.h (make_pass_vsetvl): New function. (enum avl_type): New enum. (get_ta): New function. (get_ma): Ditto. (get_avl_type): Ditto. (calculate_ratio): Ditto. (enum tail_policy): New enum. (enum mask_policy): Ditto. * config/riscv/riscv-v.cc (calculate_ratio): New function. (emit_pred_op): change the VLMAX mov codgen. (get_ta): New function. (get_ma): Ditto. (enum tail_policy): Change enum. (get_prefer_tail_policy): New function. (enum mask_policy): Change enum. (get_prefer_mask_policy): New function. * config/riscv/t-riscv: Add riscv-vsetvl.o * config/riscv/vector.md: Adjust attribute and pattern for VSETVL PASS. (@vlmax_avl<mode>): Ditto. (@vsetvl<mode>_no_side_effects): Delete. (vsetvl_vtype_change_only): New MD pattern. (@vsetvl_discard_result<mode>): Ditto. * config/riscv/riscv-vsetvl.cc: New file. * config/riscv/riscv-vsetvl.h: New file.
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