RISC-V: Support VSETVL PASS for RVV support

This patch is to support VSETVL PASS for RVV support.
1.The optimization and performance is guaranteed LCM (Lazy code motion).
2.Base on RTL_SSA framework to gain better optimization chances.
3.Also we do VL/VTYPE, demand information backward propagation across
  blocks by RTL_SSA reverse order in CFG.
4.It has been well and fully tested by about 200+ testcases for VLMAX
  AVL situation (Only for VLMAX since we don't have an intrinsics to
  test non-VLMAX).
5.Will support AVL model in the next patch.

gcc/ChangeLog:

	* config.gcc: Add riscv-vsetvl.o.
	* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Add VSETVL PASS
	location.
	* config/riscv/riscv-protos.h (make_pass_vsetvl): New function.
	(enum avl_type): New enum.
	(get_ta): New function.
	(get_ma): Ditto.
	(get_avl_type): Ditto.
	(calculate_ratio): Ditto.
	(enum tail_policy): New enum.
	(enum mask_policy): Ditto.
	* config/riscv/riscv-v.cc (calculate_ratio): New function.
	(emit_pred_op): change the VLMAX mov codgen.
	(get_ta): New function.
	(get_ma): Ditto.
	(enum tail_policy): Change enum.
	(get_prefer_tail_policy): New function.
	(enum mask_policy): Change enum.
	(get_prefer_mask_policy): New function.
	* config/riscv/t-riscv: Add riscv-vsetvl.o
	* config/riscv/vector.md: Adjust attribute and pattern for VSETVL
	PASS.
	(@vlmax_avl<mode>): Ditto.
	(@vsetvl<mode>_no_side_effects): Delete.
	(vsetvl_vtype_change_only): New MD pattern.
	(@vsetvl_discard_result<mode>): Ditto.
	* config/riscv/riscv-vsetvl.cc: New file.
	* config/riscv/riscv-vsetvl.h: New file.

1 files changed, 1 insertions, 1 deletions

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 85ec1d8..fa263f2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -529,7 +529,7 @@ pru-*-*)
 	;;
 riscv*)
 	cpu_type=riscv
-	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o"
+	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	d_target_objs="riscv-d.o"
 	extra_headers="riscv_vector.h"