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2023-02-13arc: Don't use millicode thunks unless asked for.Claudiu Zissulescu1-1/+0
ARC has enter_s/leave_s instructions which can save/restore the entire function context. It is not needed the millicode thunks anylonger when compiling for size, thus, make their usage optional. gcc/ * common/config/arc/arc-common.cc (arc_option_optimization_table): Remove millicode from list. gcc/testsuite/ * gcc.target/arc/milli-1.c: Update test.
2023-02-12RISC-V: Add vmulh C/C++ supportJu-Zhe Zhong1-0/+1
Co-authored-by: kito-cheng <kito.cheng@sifive.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add flag for 'V' extension. * config/riscv/riscv-vector-builtins-bases.cc (class vmulh): New class. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vmulh): Add vmulh API support. (vmulhu): Ditto. (vmulhsu): Ditto. * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_FULL_V_I_OPS): New macro. (DEF_RVV_FULL_V_U_OPS): Ditto. (vint8mf8_t): Ditto. (vint8mf4_t): Ditto. (vint8mf2_t): Ditto. (vint8m1_t): Ditto. (vint8m2_t): Ditto. (vint8m4_t): Ditto. (vint8m8_t): Ditto. (vint16mf4_t): Ditto. (vint16mf2_t): Ditto. (vint16m1_t): Ditto. (vint16m2_t): Ditto. (vint16m4_t): Ditto. (vint16m8_t): Ditto. (vint32mf2_t): Ditto. (vint32m1_t): Ditto. (vint32m2_t): Ditto. (vint32m4_t): Ditto. (vint32m8_t): Ditto. (vint64m1_t): Ditto. (vint64m2_t): Ditto. (vint64m4_t): Ditto. (vint64m8_t): Ditto. (vuint8mf8_t): Ditto. (vuint8mf4_t): Ditto. (vuint8mf2_t): Ditto. (vuint8m1_t): Ditto. (vuint8m2_t): Ditto. (vuint8m4_t): Ditto. (vuint8m8_t): Ditto. (vuint16mf4_t): Ditto. (vuint16mf2_t): Ditto. (vuint16m1_t): Ditto. (vuint16m2_t): Ditto. (vuint16m4_t): Ditto. (vuint16m8_t): Ditto. (vuint32mf2_t): Ditto. (vuint32m1_t): Ditto. (vuint32m2_t): Ditto. (vuint32m4_t): Ditto. (vuint32m8_t): Ditto. (vuint64m1_t): Ditto. (vuint64m2_t): Ditto. (vuint64m4_t): Ditto. (vuint64m8_t): Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FULL_V_I_OPS): Ditto. (DEF_RVV_FULL_V_U_OPS): Ditto. (check_required_extensions): Add vmulh support. (rvv_arg_type_info::get_tree_type): Ditto. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_FULL_V): Ditto. (enum rvv_base_type): Ditto. * config/riscv/riscv.opt: Add 'V' extension flag. * config/riscv/vector-iterators.md (su): New iterator. * config/riscv/vector.md (@pred_mulh<v_su><mode>): New pattern. (@pred_mulh<v_su><mode>_scalar): Ditto. (*pred_mulh<v_su><mode>_scalar): Ditto. (*pred_mulh<v_su><mode>_extended_scalar): Ditto.
2023-02-09i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]Jakub Jelinek1-16/+9
get_available_features doesn't depend on cpu_model2->__cpu_{family,model} and just sets stuff up based on CPUID leaf 1, or some extended ones, so I wonder why are we calling it separately for Intel, AMD and Zhaoxin and not for all other CPUs too? I think various programs in the wild which aren't using __builtin_cpu_{is,supports} just check the various CPUID leafs and query bits in there, without blacklisting unknown CPU vendors, so I think even __builtin_cpu_supports ("sse2") etc. should be reliable if those VENDOR_{CENTAUR,CYRIX,NSC,OTHER} CPUs set those bits in CPUID leaf 1 or some extended ones. Calling it for all CPUs also means it can be inlined because there will be just a single caller. I have tested it on Intel and Martin tested it on AMD, but can't test it on non-Intel/AMD; for Intel/AMD/Zhaoxin it should be really no change in behavior. 2023-02-09 Jakub Jelinek <jakub@redhat.com> PR target/100758 * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Formatting fixes. (cpu_indicator_init): Call get_available_features for all CPUs with max_level >= 1, rather than just Intel, AMD or Zhaoxin. Formatting fixes.
2023-02-02RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv.Jin Ma1-1/+4
MAX_MATCH_SCORE is not assigned anywhere except initialized to 0, causing BEST_MATCH_MULTI_LIB to always be 0 or -1, which will cause the result of TARGET_COMPUTE_MULTILIB hook to fail. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_compute_multilib): Fix finding best match score.
2023-02-01AArch64: Fix native detection in the presence of mandatory features which ↵Tamar Christina1-5/+17
don't have midr values aarch64-option-extensions.def explicitly defines the semantics for an empty midr field as being: In that case this field should contain a space (" ") separated list of the strings in 'Features' that are required. Their order is not important. An empty string means do not detect this feature during auto detection. That is to say, an empty string means that we don't know the midr value for this feature and so it just shouldn't be taken into account for native features detection. However this meaning seems to have gotten lost at some point. This results in e.g. -mcpu=native on a Neoverse N2 disabling features it does have. Essentially we disabled any mandatory feature for which there is no midr entry. The rationale for having -mcpu=native being able to disable features at all, is because the kernel is able to disable a mandatory feature for correctness issues. Unfortunately we can't distinguish between "old kernel" and "kernel disabled". This patch adds a new field that indicates whether the midr field has any value at all. If there's no value we skip the extension when determining the "off" flags. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (struct aarch64_option_extension): Add native_detect and document struct a bit more. (all_extensions): Set new field native_detect. * config/aarch64/aarch64.cc (struct aarch64_option_extension): Delete unused struct. gcc/testsuite/ChangeLog: * gcc.target/aarch64/cpunative/info_19: New test. * gcc.target/aarch64/cpunative/info_20: New test. * gcc.target/aarch64/cpunative/info_21: New test. * gcc.target/aarch64/cpunative/info_22: New test. * gcc.target/aarch64/cpunative/native_cpu_19.c: New test. * gcc.target/aarch64/cpunative/native_cpu_20.c: New test. * gcc.target/aarch64/cpunative/native_cpu_21.c: New test. * gcc.target/aarch64/cpunative/native_cpu_22.c: New test.
2023-01-30riscv: Enable -fasynchronous-unwind-tables by default on LinuxAndreas Schwab1-0/+4
This follows the example of aarch64. gcc/: * common/config/riscv/riscv-common.cc (riscv_option_optimization_table) [TARGET_DEFAULT_ASYNC_UNWIND_TABLES]: Enable -fasynchronous-unwind-tables and -funwind-tables. * config.gcc (riscv*-*-linux*): Define TARGET_DEFAULT_ASYNC_UNWIND_TABLES.
2023-01-23[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64Andrea Corallo1-6/+7
Hi all, This change refactors all the mbranch-protection option parsing code and types to make it common to both AArch32 and AArch64 backends. This change also pulls in some supporting types from AArch64 to make it common (aarch_parse_opt_result). The significant changes in this patch are the movement of all branch protection parsing routines from aarch64.c to aarch-common.c and supporting data types and static data structures. This patch also pre-declares variables and types required in the aarch32 back-end for moved variables for function sign scope and key to prepare for the impending series of patches that support parsing the feature mbranch-protection in the aarch32 back-end. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc: Include aarch-common.h. (all_architectures): Fix comment. (aarch64_parse_extension): Rename return type, enum value names. * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Rename factored out aarch_ra_sign_scope and aarch_ra_sign_key variables. Also rename corresponding enum values. * config/aarch64/aarch64-opts.h (aarch64_function_type): Factor out aarch64_function_type and move it to common code as aarch_function_type in aarch-common.h. * config/aarch64/aarch64-protos.h: Include common types header, move out types aarch64_parse_opt_result and aarch64_key_type to aarch-common.h * config/aarch64/aarch64.cc: Move mbranch-protection parsing types and functions out into aarch-common.h and aarch-common.cc. Fix up all the name changes resulting from the move. * config/aarch64/aarch64.md: Fix up aarch64_ra_sign_key type name change and enum value. * config/aarch64/aarch64.opt: Include aarch-common.h to import type move. Fix up name changes from factoring out common code and data. * config/arm/aarch-common-protos.h: Export factored out routines to both backends. * config/arm/aarch-common.cc: Include newly factored out types. Move all mbranch-protection code and data structures from aarch64.cc. * config/arm/aarch-common.h: New header that declares types shared between aarch32 and aarch64 backends. * config/arm/arm-protos.h: Declare types and variables that are made common to aarch64 and aarch32 backends - aarch_ra_sign_key, aarch_ra_sign_scope and aarch_enable_bti. * config/arm/arm.opt (config/arm/aarch-common.h): Include header. (aarch_ra_sign_scope, aarch_enable_bti): Declare variable. * config/arm/arm.cc: Add missing includes. Co-Authored-By: Tejas Belagod <tbelagod@arm.com>
2023-01-16Update copyright years.Jakub Jelinek55-55/+55
2023-01-13arm: Add cde feature support for Cortex-M55 CPU.Srinath Parvathaneni1-9/+12
This patch adds cde feature (optional) support for Cortex-M55 CPU, please refer [1] for more details. To use this feature we need to specify +cdecpN (e.g. -mcpu=cortex-m55+cdecp<N>), where N is the coprocessor number 0 to 7. gcc/ChangeLog: 2023-01-13 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde options for -mlibarch. * config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options. * doc/invoke.texi (CDE): Document options for Cortex-M55 CPU. gcc/testsuite/ChangeLog: 2023-01-13 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/multilib.exp: Add multilib tests for Cortex-M55 CPU.
2023-01-05Add AMD znver4 instruction reservationsTejas Joshi1-1/+1
This adds znver4 automata units and reservations separately from other znver automata, avoiding the insn-automata.cc size blow-up. gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_alias_table): Use CPU_ZNVER4 for znver4. * config/i386/i386.md: Add znver4.md. * config/i386/znver4.md: New.
2023-01-04Initial Emeraldrapids SupportHu, Lin12-0/+4
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Emeraldrapids. * common/config/i386/i386-common.cc: Add Emeraldrapids.
2023-01-04i386: Remove Meteorlake's family_modelHu, Lin11-1/+0
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Remove case 0xb5 for meteorlake.
2022-12-27Fixed typo in RISCVjinma1-1/+1
gcc/ChangeLog: * common/config/riscv/riscv-common.cc:
2022-12-27rs6000: Rework option -mpowerpc64 handling [PR106680]Kewen Lin1-11/+0
PR106680 shows that -m32 -mpowerpc64 is different from -mpowerpc64 -m32, this is determined by the way how we handle option powerpc64 in rs6000_handle_option. Segher pointed out this difference should be taken as a bug and we should ensure that option powerpc64 is independent of -m32/-m64. So this patch removes the handlings in rs6000_handle_option and add some necessary supports in rs6000_option_override_internal instead. With this patch, if users specify -m{no-,}powerpc64, the specified value is honoured, otherwise, for 64bit it always enables OPTION_MASK_POWERPC64; while for 32bit and TARGET_POWERPC64 and OS_MISSING_POWERPC64, it disables OPTION_MASK_POWERPC64. btw, following Segher's suggestion, I did some tries to warn when OPTION_MASK_POWERPC64 is set for OS_MISSING_POWERPC64. If warn for the case that powerpc64 is specified explicitly, there are some TCs using -m32 -mpowerpc64 on ppc64-linux, they need some updates, meanwhile the artificial run with "--target_board=unix'{-m32/-mpowerpc64}'" will have noisy warnings on ppc64-linux. If warn for the case that it's specified implicitly, they can just be initialized by TARGET_DEFAULT (like -m32 on ppc64-linux) or set from the given cpu mask, we have to special case them and not to warn. As Segher's latest comment, I decide not to warn them and keep it consistent with before. Bootstrapped and regress-tested on: - powerpc64-linux-gnu P7 and P8 {-m64,-m32} - powerpc64le-linux-gnu P9 and P10 - powerpc-ibm-aix7.2.0.0 {-maix64,-maix32} - powerpc-darwin9 (with Iain's help) PR target/106680 gcc/ChangeLog: * common/config/rs6000/rs6000-common.cc (rs6000_handle_option): Remove the adjustment for option powerpc64 in -m64 handling, and remove the whole -m32 handling. * config/rs6000/rs6000.cc (rs6000_option_override_internal): When no explicit powerpc64 option is provided, enable it for -m64. For 32 bit and OS_MISSING_POWERPC64, disable powerpc64 if it's enabled but not specified explicitly. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr106680-1.c: New test. * gcc.target/powerpc/pr106680-2.c: New test. * gcc.target/powerpc/pr106680-3.c: New test. * gcc.target/powerpc/pr106680-4.c: New test. 2022-12-27 Kewen Lin <linkw@linux.ibm.com> Iain Sandoe <iain@sandoe.co.uk>
2022-11-24i386: Only enable small loop unrolling in backend [PR 107692]Hongyu Wang1-0/+8
Followed by the discussion in pr107692, -munroll-only-small-loops Does not turns on/off -funroll-loops, and current check in pass_rtl_unroll_loops::gate would cause -fno-unroll-loops do not take effect. Revert the change about targetm.loop_unroll_adjust and apply the backend option change to strictly follow the rule that -funroll-loops takes full control of loop unrolling, and munroll-only-small-loops just change its behavior to unroll small size loops. gcc/ChangeLog: PR target/107692 * common/config/i386/i386-common.cc (ix86_optimization_table): Enable loop unroll O2, disable -fweb and -frename-registers by default. * config/i386/i386-options.cc (ix86_override_options_after_change): Disable small loop unroll when funroll-loops enabled, reset cunroll_grow_size when it is not explicitly enabled. (ix86_option_override_internal): Call ix86_override_options_after_change instead of calling ix86_recompute_optlev_based_flags and ix86_default_align separately. * config/i386/i386.cc (ix86_loop_unroll_adjust): Adjust unroll factor if -munroll-only-small-loops enabled. * loop-init.cc (pass_rtl_unroll_loops::gate): Do not enable loop unrolling for -O2-speed. (pass_rtl_unroll_loops::execute): Rmove targetm.loop_unroll_adjust check. gcc/testsuite/ChangeLog: PR target/107692 * gcc.dg/guality/loop-1.c: Remove additional option for ia32. * gcc.target/i386/pr86270.c: Add -fno-unroll-loops. * gcc.target/i386/pr93002.c: Likewise.
2022-11-14Revert "sphinx: port .def files to RST"Martin Liska1-14/+14
This reverts commit c8874c5e8a7cee2933923c40f4933602da2022fb.
2022-11-14i386: Add AMX-TILE dependency for AMX related ISAsHaochen Jiang1-4/+9
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_INT8_SET): Add AMX-TILE dependency. (OPTION_MASK_ISA2_AMX_BF16_SET): Ditto. (OPTION_MASK_ISA2_AMX_FP16_SET): Ditto. (OPTION_MASK_ISA2_AMX_TILE_UNSET): Disable AMX_{INT8, BF16, FP16} when disable AMX_TILE. gcc/testsuite/ChangeLog: * gcc.target/i386/amxbf16-dpbf16ps-2.c: Remove -amx-tile. * gcc.target/i386/amxfp16-dpfp16ps-2.c: Ditto. * gcc.target/i386/amxint8-dpbssd-2.c: Ditto. * gcc.target/i386/amxint8-dpbsud-2.c: Ditto. * gcc.target/i386/amxint8-dpbusd-2.c: Ditto. * gcc.target/i386/amxint8-dpbuud-2.c: Ditto.
2022-11-14Enable small loop unrolling for O2Hongyu Wang1-0/+1
Modern processors has multiple way instruction decoders For x86, icelake/zen3 has 5 uops, so for small loop with <= 4 instructions (usually has 3 uops with a cmp/jmp pair that can be macro-fused), the decoder would have 2 uops bubble for each iteration and the pipeline could not be fully utilized. Therefore, this patch enables loop unrolling for small size loop at O2 to fullfill the decoder as much as possible. It turns on rtl loop unrolling when targetm.loop_unroll_adjust exists and O2 plus speed only. In x86 backend the default behavior is to unroll small loops with less than 4 insns by 1 time. This improves 548.exchange2 by 9% on icelake and 7.4% on zen3 with 0.9% codesize increment. For other benchmarks the variants are minor and overall codesize increased by 0.2%. The kernel image size increased by 0.06%, and no impact on eembc. gcc/ChangeLog: * common/config/i386/i386-common.cc (ix86_optimization_table): Enable small loop unroll at O2 by default. * config/i386/i386.cc (ix86_loop_unroll_adjust): Adjust unroll factor if -munroll-only-small-loops enabled and -funroll-loops/ -funroll-all-loops are disabled. * config/i386/i386.h (struct processor_costs): Add 2 field small_unroll_ninsns and small_unroll_factor. * config/i386/i386.opt: Add -munroll-only-small-loops. * doc/gcc/gcc-command-options/machine-dependent-options/x86-options.rst: Document -munroll-only-small-loops. * doc/gcc/gcc-command-options/option-summary.rst: Likewise. * loop-init.cc (pass_rtl_unroll_loops::gate): Enable rtl loop unrolling for -O2-speed and above if target hook loop_unroll_adjust exists. (pass_rtl_unroll_loops::execute): Set UAP_UNROLL flag when target hook loop_unroll_adjust exists. * config/i386/x86-tune-costs.h: Update all processor costs with small_unroll_ninsns = 4 and small_unroll_factor = 2. gcc/testsuite/ChangeLog: * gcc.dg/guality/loop-1.c: Add additional option -mno-unroll-only-small-loops. * gcc.target/i386/pr86270.c: Add -mno-unroll-only-small-loops. * gcc.target/i386/pr93002.c: Likewise.
2022-11-09sphinx: port .def files to RSTMartin Liska1-14/+14
gcc/c-family/ChangeLog: * c-target.def: Port to RST. gcc/ChangeLog: * common/common-target.def: Port to RST. * target.def: Port to RST. gcc/d/ChangeLog: * d-target.def: Port to RST.
2022-11-07Initial Grand Ridge supportHu, Lin13-0/+10
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Grand Ridge. * common/config/i386/i386-common.cc (processor_names): Add grandridge. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h: (enum processor_types): Add INTEL_GRANDRIDGE. * config.gcc: Add -march=grandridge. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle grandridge. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (m_GRANDRIDGE): New define. (processor_cost_table): Add grandridge. * config/i386/i386.h (enum processor_type): Add PROCESSOR_GRANDRIDGE. (PTA_GRANDRIDGE): Ditto. * doc/extend.texi: Add grandridge. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add grandridge. * gcc.target/i386/funcspec-56.inc: Handle new march.
2022-11-07Support Intel RAO-INTkonglin14-0/+19
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect raoint. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_RAOINT_SET, OPTION_MASK_ISA2_RAOINT_UNSET): New. (ix86_handle_option): Handle -mraoint. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_RAOINT. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for raoint. * config.gcc: Add raointintrin.h * config/i386/cpuid.h (bit_RAOINT): New. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __RAOINT__. * config/i386/i386-isa.def (RAOINT): Add DEF_PTA(RAOINT). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Add -mraoint. * config/i386/sync.md (rao_a<raointop><mode>): New define insn. * config/i386/i386.opt: Add option -mraoint. * config/i386/x86gprintrin.h: Include raointintrin.h. * doc/extend.texi: Document raoint. * doc/invoke.texi: Document -mraoint. * doc/sourcebuild.texi: Document target raoint. * config/i386/raointintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mraoint. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mraoint. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add raoint target. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: Add check_effective_target_raoint. * gcc.target/i386/rao-helper.h: New test. * gcc.target/i386/raoint-1.c: Ditto. * gcc.target/i386/raoint-aadd-2.c: Ditto. * gcc.target/i386/raoint-aand-2.c: Ditto. * gcc.target/i386/raoint-aor-2.c: Ditto. * gcc.target/i386/raoint-axor-2.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Ditto. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Ditto. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2022-11-07Initial Granite Rapids SupportHaochen Jiang3-0/+13
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Granite Rapids. * common/config/i386/i386-common.cc: (processor_names): Add graniterapids. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add INTEL_GRANTIERAPIDS. * config.gcc: Add -march=graniterapids. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle graniterapids. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (m_GRANITERAPIDS): New. (processor_cost_table): Add graniterapids. * config/i386/i386.h (enum processor_type): Add PROCESSOR_GRANITERAPIDS. (PTA_GRANITERAPIDS): Ditto. * doc/extend.texi: Add graniterapids. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add graniterapids. * gcc.target/i386/funcspec-56.inc: Handle new march.
2022-11-07Support Intel prefetchit0/t1Haochen Jiang4-0/+19
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect PREFETCHI. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_PREFETCHI_SET, OPTION_MASK_ISA2_PREFETCHI_UNSET): New. (ix86_handle_option): Handle -mprefetchi. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_PREFETCHI. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for prefetchi. * config.gcc: Add prfchiintrin.h. * config/i386/cpuid.h (bit_PREFETCHI): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (VOID, PCVOID, INT) and DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __PREFETCHI__. * config/i386/i386-expand.cc: Handle new builtins. * config/i386/i386-isa.def (PREFETCHI): Add DEF_PTA(PREFETCHI). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle prefetchi. * config/i386/i386.md (prefetchi): New define_insn. * config/i386/i386.opt: Add option -mprefetchi. * config/i386/predicates.md (local_func_symbolic_operand): New predicates. * config/i386/x86gprintrin.h: Include prfchiintrin.h. * config/i386/xmmintrin.h (enum _mm_hint): New enum for prefetchi. (_mm_prefetch): Handle the highest bit of enum. * doc/extend.texi: Document prefetchi. * doc/invoke.texi: Document -mprefetchi. * doc/sourcebuild.texi: Document target prefetchi. * config/i386/prfchiintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mprefetchi. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-1.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-13.c: Add -mprefetchi. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Ditto. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Ditto. * gcc.target/i386/x86gprintrin-5.c: Ditto. * gcc.target/i386/prefetchi-1.c: New test. * gcc.target/i386/prefetchi-2.c: Ditto. * gcc.target/i386/prefetchi-3.c: Ditto. * gcc.target/i386/prefetchi-4.c: Ditto. Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
2022-11-04Support Intel AMX-FP16 ISAHongyu Wang4-0/+22
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect amx-fp16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_FP16_SET, OPTION_MASK_ISA2_AMX_FP16_UNSET): New macros. (ix86_handle_option): Handle -mamx-fp16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_FP16. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-fp16. * config.gcc: Add amxfp16intrin.h. * config/i386/cpuid.h (bit_AMX_FP16): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_FP16__. * config/i386/i386-isa.def: Add DEF_PTA for AMX_FP16. * config/i386/i386-options.cc (isa2_opts): Add -mamx-fp16. (ix86_valid_target_attribute_inner_p): Add new ATTR. (ix86_option_override_internal): Handle AMX-FP16. * config/i386/i386.opt: Add -mamx-fp16. * config/i386/immintrin.h: Include amxfp16intrin.h. * doc/extend.texi: Document -mamx-fp16. * doc/invoke.texi: Document amx-fp16. * doc/sourcebuild.texi: Document amx_fp16. * config/i386/amxfp16intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-fp16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: (check_effective_target_amx_fp16): New proc. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: Add AMX_FP16. * gcc.target/i386/amx-helper.h: New file to support amx-fp16. * gcc.target/i386/amxfp16-asmatt-1.c: New test. * gcc.target/i386/amxfp16-asmintel-1.c: Ditto. * gcc.target/i386/amxfp16-dpfp16ps-2.c: Ditto. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-11-04Initial Sierra Forest SupportHaochen Jiang3-0/+10
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Add Sierra Forest. * common/config/i386/i386-common.cc (processor_names): Add Sierra Forest. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add INTEL_SIERRAFOREST. * config.gcc: Add -march=sierraforest. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle Sierra Forest. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (m_SIERRAFOREST): New define. (processor_cost_table): Add sierra forest. * config/i386/i386.h (enum processor_type): Add PROCESSOR_SIERRA_FOREST. (PTA_SIERRAFOREST): Ditto. * doc/extend.texi: Add sierra forest. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add sierra forest. * gcc.target/i386/funcspec-56.inc: Handle new march.
2022-11-04Support Intel CMPccXADDHaochen Jiang4-0/+19
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect cmpccxadd. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_CMPCCXADD_SET, OPTION_MASK_ISA2_CMPCCXADD_UNSET): New. (ix86_handle_option): Handle -mcmpccxadd. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_CMPCCXADD. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for cmpccxadd. * config.gcc: Add cmpccxaddintrin.h. * config/i386/cpuid.h (bit_CMPCCXADD): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE(INT, PINT, INT, INT, INT) and DEF_FUNCTION_TYPE(LONGLONG, PLONGLONG, LONGLONG, LONGLONG, INT). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __CMPCCXADD__. * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Add new parameter to indicate constant position. Handle INT_FTYPE_PINT_INT_INT_INT and LONGLONG_FTYPE_PLONGLONG_LONGLONG_LONGLONG_INT. * config/i386/i386-isa.def (CMPCCXADD): Add DEF_PTA(CMPCCXADD). * config/i386/i386-options.cc (isa2_opts): Add -mcmpccxadd. (ix86_valid_target_attribute_inner_p): Handle cmpccxadd. * config/i386/i386.opt: Add option -mcmpccxadd. * config/i386/sync.md (cmpccxadd_<mode>): New define insn. * config/i386/x86gprintrin.h: Include cmpccxaddintrin.h. * doc/extend.texi: Document cmpccxadd. * doc/invoke.texi: Document -mcmpccxadd. * doc/sourcebuild.texi: Document target cmpccxadd. * config/i386/cmpccxaddintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mcmpccxadd. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-1.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-13.c: Add -mcmpccxadd. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Ditto. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Ditto. * gcc.target/i386/x86gprintrin-5.c: Ditto. * lib/target-supports.exp (check_effective_target_cmpccxadd): New. * gcc.target/i386/cmpccxadd-1.c: New test. * gcc.target/i386/cmpccxadd-2.c: Ditto.
2022-11-02RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+4
This patch adds support for the Zawrs ISA extension. Zawrs has been ratified by the RISC-V BoD on Oct 20th, 2022. Binutils support has been merged as: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=eb668e50036e979fb0a74821df4eee0307b44e66 gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zawrs extension. * config/riscv/riscv-opts.h (MASK_ZAWRS): New. (TARGET_ZAWRS): New. * config/riscv/riscv.opt: New. gcc/testsuite/ChangeLog: * gcc.target/riscv/zawrs.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-10-31Support Intel AVX-NE-CONVERTkonglin14-1/+25
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXNECONVERT_SET, OPTION_MASK_ISA2_AVXNECONVERT_UNSET): New. (ix86_handle_option): Handle -mavxneconvert, unset avxneconvert when avx2 is disabled. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AVXNECONVERT. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxneconvert. * common/config/i386/cpuinfo.h (get_available_features): Detect avxneconvert. * config.gcc: Add avxneconvertintrin.h * config/i386/avxneconvertintrin.h: New. * config/i386/avx512bf16vlintrin.h (_mm256_cvtneps_pbh): Unified builtin with avxneconvert. (_mm_cvtneps_pbh): Ditto. * config/i386/cpuid.h (bit_AVXNECONVERT): New. * config/i386/i386-builtin-types.def: Add DEF_POINTER_TYPE (PCV8HF, V8HF, CONST), DEF_POINTER_TYPE (PCV8BF, V8BF, CONST), DEF_POINTER_TYPE (PCV16HF, V16HF, CONST), DEF_POINTER_TYPE (PCV16BF, V16BF, CONST), DEF_FUNCTION_TYPE (V4SF, PCBFLOAT16), DEF_FUNCTION_TYPE (V4SF, PCFLOAT16), DEF_FUNCTION_TYPE (V8SF, PCBFLOAT16), DEF_FUNCTION_TYPE (V8SF, PCFLOAT16), DEF_FUNCTION_TYPE (V4SF, PCV8BF), DEF_FUNCTION_TYPE (V4SF, PCV8HF), DEF_FUNCTION_TYPE (V8SF, PCV16HF), DEF_FUNCTION_TYPE (V8SF, PCV16BF), * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXNECONVERT__. * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Handle V4SF_FTYPE_PCBFLOAT16,V8SF_FTYPE_PCBFLOAT16, V4SF_FTYPE_PCFLOAT16, V8SF_FTYPE_PCFLOAT16,V4SF_FTYPE_PCV8BF, V4SF_FTYPE_PCV8HF,V8SF_FTYPE_PCV16BF,V8SF_FTYPE_PCV16HF. * config/i386/i386-isa.def : Add DEF_PTA(AVXNECONVERT) New. * config/i386/i386-options.cc (isa2_opts): Add -mavxneconvert. (ix86_valid_target_attribute_inner_p): Handle avxneconvert. * config/i386/i386.md: Add attr avx512bf16vl and avxneconvert. * config/i386/i386.opt: Add option -mavxneconvert. * config/i386/immintrin.h: Inculde avxneconvertintrin.h. * config/i386/sse.md (vbcstnebf162ps_<mode>): New define_insn. (vbcstnesh2ps_<mode>): Ditto. (vcvtnee<bf16_ph>2ps_<mode>):Ditto. (vcvtneo<bf16_ph>2ps_<mode>):Ditto. (vcvtneps2bf16_v4sf): Ditto. (*vcvtneps2bf16_v4sf): Ditto. (vcvtneps2bf16_v8sf): Ditto. * doc/invoke.texi: Document -mavxneconvert. * doc/extend.texi: Document avxneconvert. * doc/sourcebuild.texi: Document target avxneconvert. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-check.h: Add avxneconvert check. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mavxneconvert. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * lib/target-supports.exp:add check_effective_target_avxneconvert. * gcc.target/i386/avx-ne-convert-1.c: New test. * gcc.target/i386/avx-ne-convert-vbcstnebf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vbcstnesh2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneebf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneeph2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneobf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneoph2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneps2bf16-2.c: Ditto. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1.c: Rename.. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1a.c: To this. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1b.c: New test.
2022-10-27RISC-V: Minimal support of z*inx extension.Jiawei1-0/+18
Minimal support of z*inx extension, include 'zfinx'， 'zdinx' and 'zhinx/zhinxmin' corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx' same as 'd' imply 'f', 'zhinx' will aslo imply 'zfinx', all zfinx extension imply 'zicsr'. Co-Authored-By: Sinan Lin <sinan@isrc.iscas.ac.cn> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extensions. * config/riscv/arch-canonicalize: New imply relations. * config/riscv/riscv-opts.h (MASK_ZFINX): New mask. (MASK_ZDINX): Ditto. (MASK_ZHINX): Ditto. (MASK_ZHINXMIN): Ditto. (TARGET_ZFINX): New target. (TARGET_ZDINX): Ditto. (TARGET_ZHINX): Ditto. (TARGET_ZHINXMIN): Ditto. * config/riscv/riscv.opt: New target variable.
2022-10-26i386: add reset_cpu_featureMartin Liska1-5/+33
gcc/ChangeLog: * common/config/i386/cpuinfo.h (has_cpu_feature): Add comment. (reset_cpu_feature): New. (get_zhaoxin_cpu): Use reset_cpu_feature.
2022-10-26RISC-V: Recognized Svinval and Svnapot extensionsMonk Chiang1-0/+6
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Add svinval and svnapot extension. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_SVINVAL): New. (MASK_SVNAPOT): Ditto. (TARGET_SVINVAL): Ditto. (TARGET_SVNAPOT): Ditto. * config/riscv/riscv.opt (riscv_sv_subext): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-24.c:New. * gcc.target/riscv/predef-25.c:New.
2022-10-26RISC-V: Add h extension supportKito Cheng1-15/+8
`h` was the prefix of multi-letter extension name, but it become a extension in later RISC-V isa spec. Fortunately we don't have any extension really defined is prefixed with `h`, so we can just change that. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Add `h`. (riscv_supported_std_ext): Ditto. (multi_letter_subset_rank): Remove `h`. (riscv_subset_list::parse_std_ext): Handle `h` as single letter extension. (riscv_subset_list::parse): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-18.c: New. * gcc.target/riscv/arch-5.c: Remove test for prefixed with `h`. * gcc.target/riscv/predef-23.c: New.
2022-10-25Remove znver4 instruction reservationsTejas Joshi1-1/+1
This reverts the changes made to znver.md in: commit bf3b532b524ecacb3202ab2c8af419ffaaab7cff 2022-10-21 Tejas Joshi <TejasSanjay.Joshi@amd.com> gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_alias_table): Use CPU_ZNVER3 for znver4. * config/i386/znver.md: Remove znver4 reservations.
2022-10-25riscv: fix cross compilerMartin Liska1-4/+4
Move riscv_get_valid_option_values out of Fixes: riscv/riscv-common.cc:1748:40: error: ‘riscv_get_valid_option_values’ was not declared in this scope gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_get_valid_option_values): Get out of ifdef.
2022-10-25i386: fix pedantic warningMartin Liska1-1/+1
PR target/107364 gcc/ChangeLog: * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Fix pedantic warning.
2022-10-24x86: fix VENDOR_MAX enum valueMartin Liska1-1/+3
PR target/107364 gcc/ChangeLog: * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Reorder enum values as BUILTIN_VENDOR_MAX should not point in the middle of the valid enum values.
2022-10-24RISC-V: Support --target-help for -mcpu/-mtuneKito Cheng1-0/+46
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_tunes): New. (riscv_get_valid_option_values): New. (TARGET_GET_VALID_OPTION_VALUES): New. * config/riscv/riscv-cores.def (RISCV_TUNE): New, define options for tune here. (RISCV_CORE): Fix comment. * config/riscv/riscv.cc (riscv_tune_info_table): Move definition to riscv-cores.def.
2022-10-21Enable AMD znver4 support and add instruction reservationsTejas Joshi3-28/+24
2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com> gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver4. * common/config/i386/i386-common.cc (processor_names): Add znver4. (processor_alias_table): Add znver4 and modularize old znvers. * common/config/i386/i386-cpuinfo.h (processor_subtypes): AMDFAM19H_ZNVER4. * config.gcc (x86_64-*-* |...): Likewise. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize znver4 cpus. * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver4. * config/i386/i386-options.cc (m_ZNVER4): New definition. (m_ZNVER): Include m_ZNVER4. (processor_cost_table): Add znver4. * config/i386/i386.cc (ix86_reassociation_width): Likewise. * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER4. (PTA_ZNVER1): New definition. (PTA_ZNVER2): Likewise. (PTA_ZNVER3): Likewise. (PTA_ZNVER4): Likewise. * config/i386/i386.md (define_attr "cpu"): Add znver4 and rename md file. * config/i386/x86-tune-costs.h (znver4_cost): New definition. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver4. (ix86_adjust_cost): Likewise. * config/i386/znver1.md: Rename to znver.md. * config/i386/znver.md: Add new reservations for znver4. * doc/extend.texi: Add details about znver4. * doc/invoke.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv29.C: Likewise.
2022-10-21Support Intel AVX-VNNI-INT8Kong Lingling4-1/+26
gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint8. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT8_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto. (ix86_handle_option): Handle -mavxvnniint8. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNIINT8. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxvnniint8. * config.gcc: Add avxvnniint8intrin.h. * config/i386/avxvnniint8intrin.h: New file. * config/i386/cpuid.h (bit_AVXVNNIINT8): New. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXVNNIINT8__. * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint8. (ix86_valid_target_attribute_inner_p): Handle avxvnniint8. * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT8) New.. * config/i386/i386.opt: Add option -mavxvnniint8. * config/i386/immintrin.h: Include avxvnniint8intrin.h. * config/i386/sse.md (UNSPEC_VPMADDUBSWACCD UNSPEC_VPMADDUBSWACCSSD,UNSPEC_VPMADDWDACCD, UNSPEC_VPMADDWDACCSSD): Rename according to new style. (vpdp<vpdotprodtype>_<mode>): New define_insn. * doc/extend.texi: Document avxvnniint8. * doc/invoke.texi: Document -mavxvnniint8. * doc/sourcebuild.texi: Document target avxvnniint8. gcc/testsuite/ChangeLog * g++.dg/other/i386-2.C: Add -mavxvnniint8. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-check.h: Add avxvnniint8 check. * gcc.target/i386/sse-12.c: Add -mavxvnniint8. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxvnniint8): New. * gcc.target/i386/avxvnniint8-1.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbssd-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbssds-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbsud-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbsuds-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbuud-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbuuds-2.c: Ditto. Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-10-21Support Intel AVX-IFMAHongyu Wang4-1/+23
gcc/ * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVXIFMA_SET, OPTION_MASK_ISA2_AVXIFMA_UNSET, OPTION_MASK_ISA2_AVX2_UNSET): New macro. (ix86_handle_option): Handle -mavxifma. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AVXIFMA. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxifma. * common/config/i386/cpuinfo.h (get_available_features): Detect avxifma. * config.gcc: Add avxifmaintrin.h * config/i386/avx512ifmavlintrin.h: (_mm_madd52lo_epu64): Change to macro. (_mm_madd52hi_epu64): Likewise. (_mm256_madd52lo_epu64): Likewise. (_mm256_madd52hi_epu64): Likewise. * config/i386/avxifmaintrin.h: New header. * config/i386/cpuid.h (bit_AVXIFMA): New. * config/i386/i386-builtin.def: Add new builtins, and correct pattern names for AVX512IFMA. * config/i386/i386-builtins.cc (def_builtin): Handle AVX-IFMA builtins like AVX-VNNI. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXIFMA__. * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Relax ISA masks for AVXIFMA. * config/i386/i386-isa.def: Add AVXIFMA. * config/i386/i386-options.cc (isa2_opts): Add -mavxifma. (ix86_valid_target_attribute_inner_p): Handle avxifma. * config/i386/i386.md (isa): Add attr avxifma and avxifmavl. * config/i386/i386.opt: Add option -mavxifma. * config/i386/immintrin.h: Inculde avxifmaintrin.h. * config/i386/sse.md (avx_vpmadd52<vpmadd52type>_<mode>): Remove. (vpamdd52<vpmadd52type><mode><sd_maskz_name>): Remove. (vpamdd52huq<mode>_maskz): Rename to ... (vpmadd52huq<mode>_maskz): ... this. (vpamdd52luq<mode>_maskz): Rename to ... (vpmadd52luq<mode>_maskz): ... this. (vpmadd52<vpmadd52type><mode>): New define_insn. (vpmadd52<vpmadd52type>v8di): Likewise. (vpmadd52<vpmadd52type><mode>_maskz_1): Likewise. (vpamdd52<vpmadd52type><mode>_mask): Rename to ... (vpmadd52<vpmadd52type><mode>_mask): ... this. * doc/invoke.texi: Document -mavxifma. * doc/extend.texi: Document avxifma. * doc/sourcebuild.texi: Document target avxifma. gcc/testsuite/ * gcc.target/i386/avx-check.h: Add avxifma check. * gcc.target/i386/avx512ifma-vpmaddhuq-1.c: Remane.. * gcc.target/i386/avx512ifma-vpmaddhuq-1a.c: To this. * gcc.target/i386/avx512ifma-vpmaddluq-1.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddluq-1a.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddhuq-1b.c: New Test. * gcc.target/i386/avx512ifma-vpmaddluq-1b.c: Ditto. * gcc.target/i386/avx-ifma-1.c: Ditto. * gcc.target/i386/avx-ifma-2.c: Ditto. * gcc.target/i386/avx-ifma-3.c: Ditto. * gcc.target/i386/avx-ifma-4.c: Ditto. * gcc.target/i386/avx-ifma-5.c: Ditto. * gcc.target/i386/avx-ifma-6.c: Ditto. * gcc.target/i386/avx-ifma-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx-ifma-vpmaddluq-2.c: Ditto. * gcc.target/i386/sse-12.c: Add -mavxifma. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxifma): New.
2022-10-17Enable REE for H8Jeff Law1-0/+2
I was looking at H8 assembly code recently and noticed we had unnecessary extensions. As it turns out we never enabled redundant extension elimination on the H8. This patch fixes that oversight (and was the trigger for the failure fixed my the prior patch). gcc/common * common/config/h8300/h8300-common.cc (h8300_option_optimization_table): Enable redundant extension elimination at -O2 and above.
2022-10-17Initial Meteorlake SupportHu, Lin12-0/+6
gcc/ChangeLog: * common/config/i386/cpuinfo.h: (get_intel_cpu): Handle Meteorlake. * common/config/i386/i386-common.cc: (processor_alias_table): Add Meteorlake.
2022-10-17Initial Raptorlake SupportHaochen Jiang2-0/+4
gcc/ChangeLog: * common/config/i386/cpuinfo.h: (get_intel_cpu): Handle Raptorlake. * common/config/i386/i386-common.cc: (processor_alias_table): Add Raptorlake.
2022-10-10arc: Remove obsolete mRcq and mRcw options.Claudiu Zissulescu1-2/+0
gcc/ * common/config/arc/arc-common.cc (arc_option_optimization_table): Remove Rcq and Rcw options. * config/arc/arc.opt (mRcq): Ignore option, preserve it for backwards compatibility. (mRcw): Likewise. * doc/invoke.texi (mRcw, mRcq): Update document. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2022-09-29aarch64: Tweak handling of -mgeneral-regs-onlyRichard Sandiford1-0/+12
-mgeneral-regs-only is effectively "+nofp for the compiler without changing the assembler's ISA flags". Currently that's implemented by making TARGET_FLOAT, TARGET_SIMD and TARGET_SVE depend on !TARGET_GENERAL_REGS_ONLY and then making any feature that needs FP registers depend (directly or indirectly) on one of those three TARGET macros. The problem is that it's easy to forgot to do the last bit. This patch instead represents the distinction between "assemnbler ISA flags" and "compiler ISA flags" more directly, funnelling all updates through a new function that sets both sets of flags together. gcc/ * config/aarch64/aarch64.opt (aarch64_asm_isa_flags): New variable. * config/aarch64/aarch64.h (aarch64_asm_isa_flags) (aarch64_isa_flags): Redefine as read-only macros. (TARGET_SIMD, TARGET_FLOAT, TARGET_SVE): Don't depend on !TARGET_GENERAL_REGS_ONLY. * common/config/aarch64/aarch64-common.cc (aarch64_set_asm_isa_flags): New function. (aarch64_handle_option): Call it when updating -mgeneral-regs. * config/aarch64/aarch64-protos.h (aarch64_simd_switcher): Replace m_old_isa_flags with m_old_asm_isa_flags. (aarch64_set_asm_isa_flags): Declare. * config/aarch64/aarch64-builtins.cc (aarch64_simd_switcher::aarch64_simd_switcher) (aarch64_simd_switcher::~aarch64_simd_switcher): Save and restore aarch64_asm_isa_flags instead of aarch64_isa_flags. * config/aarch64/aarch64-sve-builtins.cc (check_required_extensions): Use aarch64_asm_isa_flags instead of aarch64_isa_flags. * config/aarch64/aarch64.cc (aarch64_set_asm_isa_flags): New function. (aarch64_override_options, aarch64_handle_attr_arch) (aarch64_handle_attr_cpu, aarch64_handle_attr_isa_flags): Use aarch64_set_asm_isa_flags to set the ISA flags. (aarch64_option_print, aarch64_declare_function_name) (aarch64_start_file): Use aarch64_asm_isa_flags instead of aarch64_isa_flags. (aarch64_can_inline_p): Check aarch64_asm_isa_flags as well as aarch64_isa_flags.
2022-09-29aarch64: Tweak contents of flags_on/off fieldsRichard Sandiford1-8/+6
After previous changes, it's more convenient if the flags_on and flags_off fields of all_extensions include the feature flag itself. gcc/ * common/config/aarch64/aarch64-common.cc (all_extensions): Include the feature flag in flags_on and flags_off. (aarch64_parse_extension): Update accordingly. (aarch64_get_extension_string_for_isa_flags): Likewise.
2022-09-29aarch64: Make more use of aarch64_feature_flagsRichard Sandiford1-9/+10
A previous patch added a aarch64_feature_flags typedef, to abstract the representation of the feature flags. This patch makes existing code use the typedef too. Hope I've caught them all! gcc/ * common/config/aarch64/aarch64-common.cc: Use aarch64_feature_flags for feature flags throughout. * config/aarch64/aarch64-protos.h: Likewise. * config/aarch64/aarch64-sve-builtins.h: Likewise. * config/aarch64/aarch64-sve-builtins.cc: Likewise. * config/aarch64/aarch64.cc: Likewise. * config/aarch64/aarch64.opt: Likewise. * config/aarch64/driver-aarch64.cc: Likewise.
2022-09-29aarch64: Tweak constness of option-related dataRichard Sandiford1-13/+13
Some of the option structures have all-const member variables. That doesn't seem necessary: we can just use const on the objects that are supposed to be read-only. Also, with the new, more C++-heavy option handling, it seems better to use constexpr for the static data, to make sure that we're not adding unexpected overhead. gcc/ * common/config/aarch64/aarch64-common.cc (aarch64_option_extension) (processor_name_to_arch, arch_to_arch_name): Remove const from member variables. (all_extensions, all_cores, all_architectures): Make a constexpr. * config/aarch64/aarch64.cc (processor): Remove const from member variables. (all_architectures): Make a constexpr. * config/aarch64/driver-aarch64.cc (aarch64_core_data) (aarch64_arch_driver_info): Remove const from member variables. (aarch64_cpu_data, aarch64_arches): Make a constexpr. (get_arch_from_id): Return a pointer to const. (host_detect_local_cpu): Update accordingly.
2022-09-29aarch64: Avoid std::string in static dataRichard Sandiford1-2/+2
Just a minor patch to avoid having to construct std::strings in static data. gcc/ * common/config/aarch64/aarch64-common.cc (processor_name_to_arch) (arch_to_arch_name): Use const char * instead of std::string.
2022-09-29aarch64: Simplify generation of .arch stringsRichard Sandiford1-196/+47
aarch64-common.cc has two arrays, one maintaining the original definition order and one sorted by population count. Sorting by population count was a way of ensuring topological ordering, taking advantage of the fact that the entries are partially ordered by the subset relation. However, the sorting is not needed now that the .def file is forced to have topological order from the outset. Other changes are: (1) The population count used: uint64_t total_flags_a = opt_a->flag_canonical & opt_a->flags_on; uint64_t total_flags_b = opt_b->flag_canonical & opt_b->flags_on; int popcnt_a = popcount_hwi ((HOST_WIDE_INT)total_flags_a); int popcnt_b = popcount_hwi ((HOST_WIDE_INT)total_flags_b); where I think the & was supposed to be |. This meant that the counts would always be 1 in practice, since flag_canonical is a single bit. This led us to printing +nofp+nosimd even though GCC "knows" (and GAS agrees) that +nofp disables simd. (2) The .arch output code converts +aes+sha2 to +crypto. I think the main reason for doing this is to support assemblers that predate the individual per-feature crypto flags. It therefore seems more natural to treat it as a special case, rather than as an instance of a general pattern. Hopefully we won't do something similar in future! (There is already special handling of CRC, for different reasons.) (3) Previously, if the /proc/cpuinfo code saw a feature like sve, it would assume the presence of all the features that sve depends on. It would be possible to keep that behaviour if necessary, but it was simpler to assume the presence of fp16 (say) only when fphp is present. There's an argument that that's more conservatively correct too. gcc/ * common/config/aarch64/aarch64-common.cc (TARGET_OPTION_INIT_STRUCT): Delete. (aarch64_option_extension): Remove is_synthetic_flag. (all_extensions): Update accordingly. (all_extensions_by_on, opt_ext, opt_ext_cmp): Delete. (aarch64_option_init_struct, aarch64_contains_opt): Delete. (aarch64_get_extension_string_for_isa_flags): Rewrite to use all_extensions instead of all_extensions_on. gcc/testsuite/ * gcc.target/aarch64/cpunative/info_8: Add all dependencies of sve. * gcc.target/aarch64/cpunative/info_9: Likewise svesm4. * gcc.target/aarch64/cpunative/info_15: Likewise. * gcc.target/aarch64/cpunative/info_16: Likewise sve2. * gcc.target/aarch64/cpunative/info_17: Likewise. * gcc.target/aarch64/cpunative/native_cpu_2.c: Expect just +nofp rather than +nofp+nosimd. * gcc.target/aarch64/cpunative/native_cpu_10.c: Likewise. * gcc.target/aarch64/target_attr_15.c: Likewise.
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