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2018-05-23[AArch64][PR target/84882] Add mno-strict-alignSudakshina Das1-1/+4
*** gcc/ChangeLog *** 2018-05-23 Sudakshina Das <sudi.das@arm.com> PR target/84882 * common/config/aarch64/aarch64-common.c (aarch64_handle_option): Check val before adding MASK_STRICT_ALIGN to opts->x_target_flags. * config/aarch64/aarch64.opt (mstrict-align): Remove RejectNegative. * config/aarch64/aarch64.c (aarch64_attributes): Mark allow_neg as true for strict-align. (aarch64_can_inline_p): Perform checks even when callee has no attributes to check for strict alignment. * doc/extend.texi (AArch64 Function Attributes): Document no-strict-align. * doc/invoke.texi: (AArch64 Options): Likewise. *** gcc/testsuite/ChangeLog *** 2018-05-23 Sudakshina Das <sudi.das@arm.com> PR target/84882 * gcc.target/aarch64/pr84882.c: New test. * gcc.target/aarch64/target_attr_18.c: Likewise. From-SVN: r260604
2018-05-19[NDS32] Add abssi2 pattern.Chung-Ju Wu1-0/+2
gcc/ * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Add MASK_HW_ABS. * config/nds32/nds32.md (abssi2): New pattern. From-SVN: r260398
2018-05-18RISC-V: Add RV32E support.Kito Cheng1-1/+28
Kito Cheng <kito.cheng@gmail.com> Monk Chiang <sh.chiang04@gmail.com> gcc/ * common/config/riscv/riscv-common.c (riscv_parse_arch_string): Add support to parse rv32e*. Clear MASK_RVE for rv32i and rv64i. * config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e. * config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define __riscv_32e when TARGET_RVE. Handle ABI_ILP32E as soft-float ABI. * config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E. * config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE, compute save_libcall_adjustment properly. (riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E. (riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E. * config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E. (STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE. (GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise. (ABI_SPEC): Handle mabi=ilp32e. * config/riscv/riscv.opt (abi_type): Add ABI_ILP32E. (RVE): Add RVE mask. * doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info. <-march>: Add rv32e as an example. gcc/testsuite/ * gcc.dg/stack-usage-1.c: Add support for rv32e. libgcc/ * config/riscv/save-restore.S: Add support for rv32e. Co-Authored-By: Jim Wilson <jimw@sifive.com> Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com> From-SVN: r260384
2018-05-14i386-common.c (OPTION_MASK_ISA_CLDEMOTE_SET, [...]): New defines.Sebastian Peryt1-0/+15
2018-05-14 Sebastian Peryt <sebastian.peryt@intel.com> gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_CLDEMOTE_SET, OPTION_MASK_ISA_CLDEMOTE_UNSET): New defines. (ix86_handle_option): Handle -mcldemote. * config.gcc: New header. * config/i386/cldemoteintrin.h: New file. * config/i386/cpuid.h (bit_CLDEMOTE): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mcldemote. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_CLDEMOTE. * config/i386/i386.c (ix86_target_string): Add -mcldemote. (ix86_valid_target_attribute_inner_p): Ditto. (enum ix86_builtins): Add IX86_BUILTIN_CLDEMOTE. (ix86_init_mmx_sse_builtins): Define __builtin_ia32_cldemote. (ix86_expand_builtin): Expand IX86_BUILTIN_CLDEMOTE. * config/i386/i386.h (TARGET_CLDEMOTE, TARGET_CLDEMOTE_P): New. * config/i386/i386.md (UNSPECV_CLDEMOTE): New. (cldemote): New. * config/i386/i386.opt: Add -mcldemote. * config/i386/x86intrin.h: New header. * doc/invoke.texi: Add -mcldemote. gcc/testsuite/ * gcc.target/i386/cldemote-1.c: New test. From-SVN: r260224
2018-05-11i386-common.c (OPTION_MASK_ISA_WAITPKG_SET, [...]): New defines.Sebastian Peryt1-0/+15
2018-05-11 Sebastian Peryt <sebastian.peryt@intel.com> gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_WAITPKG_SET, OPTION_MASK_ISA_WAITPKG_UNSET): New defines. (ix86_handle_option): Handle -mwaitpkg. * config.gcc: New header. * config/i386/cpuid.h (bit_WAITPKG): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mwaitpkg. * config/i386/i386-builtin-types.def ((UINT8, UNSIGNED, UINT64)): New function type. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_WAITPKG. * config/i386/i386.c (ix86_target_string): Add -mwaitpkg. (ix86_option_override_internal): Add PTA_WAITPKG. (ix86_valid_target_attribute_inner_p): Add -mwaitpkg. (enum ix86_builtins): Add IX86_BUILTIN_UMONITOR, IX86_BUILTIN_UMWAIT, IX86_BUILTIN_TPAUSE. (ix86_init_mmx_sse_builtins): Define __builtin_ia32_umonitor, __builtin_ia32_umwait and __builtin_ia32_tpause. (ix86_expand_builtin): Expand IX86_BUILTIN_UMONITOR, IX86_BUILTIN_UMWAIT, IX86_BUILTIN_TPAUSE. * config/i386/i386.h (TARGET_WAITPKG, TARGET_WAITPKG_P): New. * config/i386/i386.md (UNSPECV_UMWAIT, UNSPECV_UMONITOR, UNSPECV_TPAUSE): New. (umwait, umwait_rex64, umonitor_<mode>, tpause, tpause_rex64): New. * config/i386/i386.opt: Add -mwaitpkg. * config/i386/waitpkgintrin.h: New file. * config/i386/x86intrin.h: New header. * doc/invoke.texi: Add -mwaitpkg. gcc/testsuite/ * gcc.target/i386/tpause-1.c: New test. * gcc.target/i386/umonitor-1.c: New test. From-SVN: r260161
2018-05-04rs6000: Remove Xilinx FPSegher Boessenkool1-58/+0
This removes the special Xilinx FP support. It was deprecated in GCC 8. After this patch all of TARGET_{DOUBLE,SINGLE}_FLOAT, TARGET_{DF,SF}_INSN, and TARGET_{DF,SF}_FPR are replaced by TARGET_HARD_FLOAT. Also the fp_type attribute is deleted. * common/config/rs6000/rs6000-common.c (rs6000_handle_option): Remove Xilinx FP support. * config.gcc (powerpc-xilinx-eabi*): Remove. * config/rs6000/predicates.md (easy_fp_constant): Remove Xilinx FP support. (fusion_addis_mem_combo_load): Ditto. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove Xilinx FP support. (rs6000_cpu_cpp_builtins): Ditto. * config/rs6000/rs6000-linux.c (rs6000_linux_float_exceptions_rounding_supported_p): Ditto. * config/rs6000/rs6000-opts.h (enum fpu_type_t): Delete. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove Xilinx FP support. (rs6000_setup_reg_addr_masks): Ditto. (rs6000_init_hard_regno_mode_ok): Ditto. (rs6000_option_override_internal): Ditto. (legitimate_lo_sum_address_p): Ditto. (rs6000_legitimize_address): Ditto. (rs6000_legitimize_reload_address): Ditto. (rs6000_legitimate_address_p): Ditto. (abi_v4_pass_in_fpr): Ditto. (setup_incoming_varargs): Ditto. (rs6000_gimplify_va_arg): Ditto. (rs6000_split_multireg_move): Ditto. (rs6000_savres_strategy): Ditto. (rs6000_emit_prologue_components): Ditto. (rs6000_emit_epilogue_components): Ditto. (rs6000_emit_prologue): Ditto. (rs6000_emit_epilogue): Ditto. (rs6000_elf_file_end): Ditto. (rs6000_function_value): Ditto. (rs6000_libcall_value): Ditto. * config/rs6000/rs6000.h: Ditto. (TARGET_MINMAX_SF, TARGET_MINMAX_DF): Delete, merge to ... (TARGET_MINMAX): ... this. New. (TARGET_SF_FPR, TARGET_DF_FPR, TARGET_SF_INSN, TARGET_DF_INSN): Delete. * config/rs6000/rs6000.md: Remove Xilinx FP support. (*movsi_internal1_single): Delete. * config/rs6000/rs6000.opt (msingle-float, mdouble-float, msimple-fpu, mfpu=, mxilinx-fpu): Delete. * config/rs6000/singlefp.h: Delete. * config/rs6000/sysv4.h: Remove Xilinx FP support. * config/rs6000/t-rs6000: Ditto. * config/rs6000/t-xilinx: Delete. * gcc/config/rs6000/titan.md: Adjust for fp_type removal. * gcc/config/rs6000/vsx.md: Remove Xilinx FP support. (VStype_simple): Delete. (VSfptype_simple, VSfptype_mul, VSfptype_div, VSfptype_sqrt): Delete. * config/rs6000/xfpu.h: Delete. * config/rs6000/xfpu.md: Delete. * config/rs6000/xilinx.h: Delete. * config/rs6000/xilinx.opt: Delete. * gcc/doc/invoke.texi (RS/6000 and PowerPC Options): Remove -msingle-float, -mdouble-float, -msimple-fpu, -mfpu=, and -mxilinx-fpu. From-SVN: r259929
2018-04-24x86/CET: Remove the -mcet command-lint optionH.J. Lu1-1/+0
With revision 259496: commit b1384095a7c1d06a44b70853372ebe037b2f7867 Author: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Thu Apr 19 15:15:04 2018 +0000 x86: Enable -fcf-protection with multi-byte NOPs -fcf-protection no longer depens on -mcet and with revision 259522: commit d59cfa9a4064339cf2bd2da828c4c133f13e57f0 Author: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Fri Apr 20 13:30:13 2018 +0000 Define __CET__ for -fcf-protection and remove -mibt -mcet becomes an alias for -mshstk. Since all usages of -mcet and -mno-cet have either been removed or replaced, we can remove the -mcet command-lint option. PR target/85485 * common/config/i386/i386-common.c (ix86_handle_option): Don't handle OPT_mcet. * config/i386/i386.opt (mcet): Removed. * doc/install.texi: Remove -mcet documentation. * doc/invoke.texi: Likewise. From-SVN: r259613
2018-04-20Define __CET__ for -fcf-protection and remove -mibtH.J. Lu1-17/+0
With revision 259496: commit b1384095a7c1d06a44b70853372ebe037b2f7867 Author: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Thu Apr 19 15:15:04 2018 +0000 x86: Enable -fcf-protection with multi-byte NOPs -mibt does nothing and can be removed. Define __CET__ to indicate level protection with -fcf-protection: (__CET__ & 1) != 0: -fcf-protection=branch or -fcf-protection=full (__CET__ & 2) != 0: -fcf-protection=return or -fcf-protection=full gcc/ PR target/85469 * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): Removed. (OPTION_MASK_ISA_IBT_UNSET): Likewise. (ix86_handle_option): Don't handle OPT_mibt. * config/i386/cet.h: Check __CET__ instead of __IBT__ and __SHSTK__. * config/i386/driver-i386.c (host_detect_local_cpu): Remove has_ibt and ibt. * config/i386/i386-c.c (ix86_target_macros_internal): Don't check OPTION_MASK_ISA_IBT nor flag_cf_protection. (ix86_target_macros): Define __CET__ with flag_cf_protection for -fcf-protection. * config/i386/i386.c (isa2_opts): Remove -mibt. * config/i386/i386.h (TARGET_IBT): Removed. (TARGET_IBT_P): Likewise. (ix86_valid_target_attribute_inner_p): Don't check OPT_mibt. * config/i386/i386.md (nop_endbr): Don't check TARGET_IBT. * config/i386/i386.opt (mcet): Update help message. (mshstk): Likewise. (mibt): Removed. * doc/invoke.texi: Remove -mibt. Document __CET__. Document -mcet as an alias for -mshstk. gcc/testsuite/ PR target/85469 * gcc.target/i386/pr85044.c (dg-options): Remove -mibt. * gcc.target/i386/sse-26.c (dg-options): Remove -mno-ibt. From-SVN: r259522
2018-04-19i386-common.c (OPTION_MASK_ISA_MOVDIRI_SET, [...]): New defines.Sebastian Peryt1-0/+30
2018-04-19 Sebastian Peryt <sebastian.peryt@intel.com> gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_MOVDIRI_SET, OPTION_MASK_ISA_MOVDIR64B_SET, OPTION_MASK_ISA_MOVDIRI_UNSET, OPTION_MASK_ISA_MOVDIR64B_UNSET): New defines. (ix86_handle_option): Handle -mmovdiri and -mmovdir64b. * config.gcc (movdirintrin.h): New header. * config/i386/cpuid.h (bit_MOVDIRI, bit_MOVDIR64B): New bits. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mmovdiri and -mmvodir64b. * config/i386/i386-builtin-types.def ((VOID, PUNSIGNED, UNSIGNED), (VOID, PVOID, PCVOID)): New function types. * config/i386/i386-builtin.def (__builtin_ia32_directstoreu_u32, __builtin_ia32_directstoreu_u64, __builtin_ia32_movdir64b): New builtins. * config/i386/i386-c.c (__MOVDIRI__, __MOVDIR64B__): New. * config/i386/i386.c (ix86_target_string): Added -mmovdir64b and -mmovdiri. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_expand_special_args_builtin): Added VOID_FTYPE_PUNSIGNED_UNSIGNED and VOID_FTYPE_PUNSIGNED_UNSIGNED. (ix86_expand_builtin): Expand IX86_BUILTIN_MOVDIR64B. * config/i386/i386.h (TARGET_MOVDIRI, TARGET_MOVDIRI_P, TARGET_MOVDIR64B, TARGET_MOVDIR64B_P): New. * config/i386/i386.md (UNSPECV_MOVDIRI, UNSPECV_MOVDIR64B): New. (movdiri<mode>, movdir64b_<mode>): New. * config/i386/i386.opt: Add -mmovdiri and -mmovdir64b. * config/i386/immintrin.h: Include movdirintrin.h. * config/i386/movdirintrin.h: New file. * doc/invoke.texi: Added -mmovdiri and -mmovdir64b. gcc/testsuite/ * gcc.target/i386/movdir-1.c: New test. From-SVN: r259495
2018-04-10rs6000: Enable -fasynchronous-unwind-tables by defaultSegher Boessenkool1-0/+9
To find out where on-entry register values live at any point in a program, GDB currently tries to parse to parse the executable code. This does not work very well, for example it gets confused if some accesses to the stack use the frame pointer (r31) and some use the stack pointer (r1). A symptom is that backtraces can be cut short. This patch enables -fasynchronous-unwind-tables by default for rs6000, which causes us to emit DWARF unwind tables for all functions, solving these problems. This not do anything for sub-targets without DWARF, and only for ELF sub-targets for now. It increases executable size, but only modestly, and does not change memory use, only the disk image. * common/config/rs6000/rs6000-common.c (rs6000_option_init_struct): Enable -fasynchronous-unwind-tables by default if OBJECT_FORMAT_ELF. gcc/testsuite/ * gcc.target/powerpc/dfmode_off.c: Add -fno-asynchronous-unwind-tables. * gcc.target/powerpc/dimode_off.c: Ditto. * gcc.target/powerpc/tfmode_off.c: Ditto. * gcc.target/powerpc/timode_off.c: Ditto. From-SVN: r259298
2018-04-06[NDS32] Add hard float support.Monk Chiang1-0/+2
gcc/ * config.gcc (nds32*-*-*): Add v2j v3f v3s checking. (nds32*-*-*): Add float and fpu_config into supported_defaults. * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Include TARGET_DEFAULT_FPU_ISA and TARGET_DEFAULT_FPU_FMA. * config/nds32/constants.md (unspec_element): Add UNSPEC_COPYSIGN, UNSPEC_FCPYNSD, UNSPEC_FCPYNSS, UNSPEC_FCPYSD and UNSPEC_FCPYSS. * config/nds32/constraints.md: New constraints and checking for hard float configuration. * config/nds32/iterators.md: New mode iterator and attribute for hard float configuration. * config/nds32/nds32-doubleword.md: Use hard float alternatives and patterns. * config/nds32/nds32-fpu.md: New file. * config/nds32/nds32-md-auxiliary.c: New functions and checkings to deal with hard float code generation. * config/nds32/nds32-opts.h (nds32_arch_type): Add ARCH_V3F and ARCH_V3S. (abi_type, float_reg_number): New enum type. * config/nds32/nds32-predicates.c: New predicates for hard float. * config/nds32/nds32-protos.h: Declare functions for hard float. * config/nds32/nds32.c: Implementation for hard float configuration. * config/nds32/nds32.h: Definitions for hard float configuration. * config/nds32/nds32.md: Include hard float machine description and modify patterns for hard float configuration. * config/nds32/nds32.opt: New options for hard float configuration. * config/nds32/predicates.md: New predicates for hard float configuration. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> From-SVN: r259161
2018-04-06[NDS32] Enable relax hint by default.Kuan-Lin Chen1-0/+2
gcc/ * common/config/nds32/nds32-common.c (nds32_option_optimization_table): Enable -mreleax-hint by default. From-SVN: r259160
2018-03-27[Patch AArch64] Turn on -fasynchronous-unwind-tables and -funwind-tables by ↵Ramana Radhakrishnan1-0/+4
default 2018-03-27 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config.gcc (aarch64*-*-linux*): New TARGET_DEFAULT_ASYNC_UNWIND_TABLES * common/config/aarch64/aarch64-common.c (aarch64_optimization_table[]): Turn on fasynchronous-unwind-tables and funwind-tables. From-SVN: r258871
2018-03-09[arm] PR target/83193: Do not print arch/cpu hints twice on invalid -march/-mcpuKyrylo Tkachov1-10/+19
Currently when handling an invalid -march or -mcpu option on a toolchain without an explicit --with-mode configuration and compiling without an explicit -mthumb or -marm the arm specs end up calling arm_target_thumb_only to determine the "thumbness" of the target, which involves parsing the architecture or cpu name. But the functions doing that parsing also emit error messages and hints on invalid arguments. Later when we parse the architecture or cpu string to as part of the canonicalisation process (arm_canon_arch_option) we end up emitting the errors again. The solution in this patch is to silence the errors during the arm_target_thumb_only processing so that they are not emitted twice. arm_canon_arch_option is guaranteed to run as well, so it can emit the errors and hints that it needs. Bootstrapped and tested on arm-none-linux-gnueabihf. Checked that we emit the arch/cpu hints for invalid -march/-mcpu options only once when no "thumbness" options were specified during configuration or invocation. PR target/83193 * common/config/arm/arm-common.c (arm_parse_arch_option_name): Accept complain bool parameter. Only emit errors if it is true. (arm_parse_cpu_option_name): Likewise. (arm_target_thumb_only): Adjust callers of the above. * config/arm/arm-protos.h (arm_parse_cpu_option_name): Adjust prototype to take a default true bool parameter. (arm_parse_arch_option_name): Likewise. From-SVN: r258389
2018-03-05Enable WBOINVD and PCONFIG instructions.Olga Makhotina1-0/+30
2018-03-05 Olga Makhotina <olga.makhotina@intel.com> Enable WBOINVD and PCONFIG instructions. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PCONFIG_SET, OPTION_MASK_ISA_PCONFIG_UNSET, OPTION_MASK_ISA_WBNOINVD_SET, OPTION_MASK_ISA_WBNOINVD_UNSET): New definitions. (ix86_handle_option): Handle -mpconfig and -mwbnoinvd. * config.gcc (pconfigintrin.h, wbnoinvdintrin.h) : Add headers. * config/i386/cpuid.h (bit_PCONFIG, bit_WBNOINVD): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mpconfig and -mwbnoinvd. * config/i386/i386-builtin.def (__builtin_ia32_wbnoinvd, __builtin_ia32_wbinvd): New builtins. (SPECIAL_ARGS2): New. * config/i386/i386-c.c (__WBNOINVD__, __PCONFIG__): New. (SPECIAL_ARGS2): New. * config/i386/i386.c (ix86_target_string): Add -mpconfig and -mwbnoinvd. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_init_mmx_sse_builtins): Add special_args2. * config/i386/i386.h (TARGET_PCONFIG, TARGET_PCONFIG_P, TARGET_WBNOINVD, TARGET_WBNOINVD_P): New. * config/i386/i386.md (UNSPECV_WBINVD, UNSPECV_WBNOINVD): New. (define_insn "wbinvd", define_insn "wbnoinvd"): New. * config/i386/i386.opt: Add -mpconfig and -mwbnoinvd. * config/i386/immintrin.h (_wbinvd): New intrinsic. * config/i386/pconfigintrin.h: New file. * config/i386/wbnoinvdintrin.h: Ditto. * config/i386/x86intrin.h: Add headers pconfigintrin.h and wbnoinvdintrin.h. * doc/invoke.texi (-mpconfig, -mwbnoinvd): New. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mpconfig and -mwbnoinvd. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-23.c: Add pconfig and wbnoinvd. * gcc.target/i386/wbinvd-1.c: New test. * gcc.target/i386/wbnoinvd-1.c: Ditto. * gcc.target/i386/pconfig-1.c: Ditto. From-SVN: r258247
2018-02-26[Patch AArch64] Turn on frame pointer / partial fix for PR84521Ramana Radhakrishnan1-0/+2
This fixes a GCC-8 regression that we accidentally switched off frame pointers in the AArch64 backend when changing the defaults in the common parts of the code. This breaks an ABI decision that was made in GCC at the dawn of the port with respect to having a frame pointer at all times. If we really want to turn this off lets have a discussion around that separately. For now turn this back on and I believe this will leave PR84521 latent again with -fomit-frame-pointer and (hopefully) make the ruby issue go away. I'm asking Sudi to pick that up. Bootstrapped and regression tested on AArch64-none-linux-gnu but I see one regression in gcc.c-torture/execute/960419-2.c which needs to be looked at next (PR84528, thanks Kyrill). Ok to put in and then look at PR84528 ? 2018-02-26 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/84521 * common/config/aarch64/aarch64-common.c (aarch_option_optimization_table[]): Switch off fomit-frame-pointer 2018-02-26 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/84521 * gcc.target/aarch64/lr_free_2.c: Revert changes in r254814 disabling -fomit-frame-pointer by default. * gcc.target/aarch64/spill_1.c: Likewise. * gcc.target/aarch64/test_frame_11.c: Likewise. * gcc.target/aarch64/test_frame_12.c: Likewise. * gcc.target/aarch64/test_frame_13.c: Likewise. * gcc.target/aarch64/test_frame_14.c: Likewise. * gcc.target/aarch64/test_frame_15.c: Likewise. * gcc.target/aarch64/test_frame_3.c: Likewise. * gcc.target/aarch64/test_frame_5.c: Likewise. * gcc.target/aarch64/test_frame_9.c: Likewise. From-SVN: r257984
2018-02-22Add "native" as a valid option value for -mcpu/-mtune= on arm (PR driver/83193).Martin Liska1-0/+6
2018-02-22 Martin Liska <mliska@suse.cz> PR driver/83193 * common/config/arm/arm-common.c (arm_print_hint_for_cpu_option): Add "native" as a possible value. From-SVN: r257900
2018-02-21Add "native" as a valid option value for -march= on arm (PR driver/83193).Martin Liska1-0/+6
2018-02-21 Martin Liska <mliska@suse.cz> PR driver/83193 * common/config/arm/arm-common.c (arm_print_hint_for_arch_option): Add "native" as a possible value. * config/arm/arm.h (HAVE_LOCAL_CPU_DETECT): Define the macro when native cpu detection is available. From-SVN: r257873
2018-02-01avr.c (avr_option_override): Move disabling of -fdelete-null-pointer-checks ↵Georg-Johann Lay1-0/+6
to... gcc/ * config/avr/avr.c (avr_option_override): Move disabling of -fdelete-null-pointer-checks to... * common/config/avr/avr-common.c (avr_option_optimization_table): ...here. testsuite/ * gcc.dg/tree-ssa/vrp111.c (dg-options): Add -fdelete-null-pointer-checks. From-SVN: r257301
2018-01-09Don't save registers in main().Georg-Johann Lay1-0/+1
gcc/ Don't save registers in main(). PR target/83737 * doc/invoke.texi (AVR Options) [-mmain-is-OS_task]: Document it. * config/avr/avr.opt (-mmain-is-OS_task): New target option. * config/avr/avr.c (avr_set_current_function): Don't error if naked, OS_task or OS_main are specified at the same time. (avr_function_ok_for_sibcall): Don't disable sibcalls for OS_task, OS_main. (avr_insert_attributes) [-mmain-is-OS_task] <main>: Add OS_task attribute. * common/config/avr/avr-common.c (avr_option_optimization_table): Switch on -mmain-is-OS_task for optimizing compilations. From-SVN: r256373
2018-01-03Update copyright years.Jakub Jelinek51-51/+51
From-SVN: r256169
2017-12-25re PR target/83488 (ICE on a CET test-case)Jakub Jelinek1-31/+43
PR target/83488 * config/i386/i386.opt (-mavx512vpopcntdq, -mmavx512bitalg): Move from ix86_isa_flags2 to ix86_isa_flags. * config/i386/i386-c.c (ix86_target_macros_internal): Test OPTION_MASK_ISA_AVX512BITALG and OPTION_MASK_ISA_AVX512VPOPCNTDQ in isa_flags rather than isa_flags2. * config/i386/i386.c (ix86_target_string): Move -mavx512vpopcntdq and -mavx512bitalg from isa2_opts to isa_opts. (ix86_option_override_internal): Test OPTION_MASK_ISA_AVX512VPOPCNTDQ in x_ix86_isa_flags_explicit rather than x_ix86_isa_flags2_explicit and set it in x_ix86_isa_flags rather than x_ix86_isa_flags2. Formatting fixes. (def_builtin): Treat OPTION_MASK_ISA_AVX512BW or OPTION_MASK_ISA_AVX512F ored with another option similarly to OPTION_MASK_ISA_AVX512VL. Even for OPTION_MASK_ISA_AVX512VL don't clear it if mask is just OPTION_MASK_ISA_AVX512VL itself. (ix86_expand_builtin): Don't handle OPTION_MASK_ISA_GFNI and OPTION_MASK_ISA_VPCLMULQDQ specially, instead handle OPTION_MASK_ISA_AVX512BW and OPTION_MASK_ISA_AVX512F that way. * config/i386/i386-builtin.def: Move AVX512VPOPCNTDQ and AVX512BITALG builtins from bdesc_args2 to bdesc_args section. (__builtin_ia32_compressstoreuqi512_mask, __builtin_ia32_compressstoreuhi512_mask, __builtin_ia32_compressstoreuqi256_mask, __builtin_ia32_expandloadqi512_mask, __builtin_ia32_expandloadqi512_maskz, __builtin_ia32_expandloadhi512_mask, __builtin_ia32_expandloadhi512_maskz, __builtin_ia32_compressqi512_mask, __builtin_ia32_compresshi512_mask, __builtin_ia32_compressqi256_mask, __builtin_ia32_expandqi512_mask, __builtin_ia32_expandqi512_maskz, __builtin_ia32_expandhi512_mask, __builtin_ia32_expandhi512_maskz, __builtin_ia32_expandqi256_mask, __builtin_ia32_expandqi256_maskz, __builtin_ia32_vpshrd_v32hi_mask, __builtin_ia32_vpshld_v32hi_mask, __builtin_ia32_vpshrdv_v32hi_mask, __builtin_ia32_vpshrdv_v32hi_maskz, __builtin_ia32_vpshldv_v32hi_mask, __builtin_ia32_vpshldv_v32hi_maskz, __builtin_ia32_vpopcountb_v64qi_mask, __builtin_ia32_vpopcountw_v32hi_mask, __builtin_ia32_vpshufbitqmb512_mask, __builtin_ia32_vpshufbitqmb256_mask): Add " | OPTION_MASK_ISA_AVX512BW". (__builtin_ia32_expandloadqi256_mask, __builtin_ia32_expandloadqi256_maskz, __builtin_ia32_vpopcountb_v32qi_mask): Add " | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW". (__builtin_ia32_expandloadhi256_mask, __builtin_ia32_expandloadhi256_maskz, __builtin_ia32_expandloadqi128_mask, __builtin_ia32_expandloadqi128_maskz, __builtin_ia32_expandloadhi128_mask, __builtin_ia32_expandloadhi128_maskz, __builtin_ia32_vpshrd_v16hi, __builtin_ia32_vpshrd_v16hi_mask, __builtin_ia32_vpshrd_v8hi, __builtin_ia32_vpshrd_v8hi_mask, __builtin_ia32_vpshrd_v8si, __builtin_ia32_vpshrd_v8si_mask, __builtin_ia32_vpshrd_v4si, __builtin_ia32_vpshrd_v4si_mask, __builtin_ia32_vpshrd_v4di, __builtin_ia32_vpshrd_v4di_mask, __builtin_ia32_vpshrd_v2di, __builtin_ia32_vpshrd_v2di_mask, __builtin_ia32_vpshld_v16hi, __builtin_ia32_vpshld_v16hi_mask, __builtin_ia32_vpshld_v8hi, __builtin_ia32_vpshld_v8hi_mask, __builtin_ia32_vpshld_v8si, __builtin_ia32_vpshld_v8si_mask, __builtin_ia32_vpshld_v4si, __builtin_ia32_vpshld_v4si_mask, __builtin_ia32_vpshld_v4di, __builtin_ia32_vpshld_v4di_mask, __builtin_ia32_vpshld_v2di, __builtin_ia32_vpshld_v2di_mask, __builtin_ia32_vpshrdv_v16hi, __builtin_ia32_vpshrdv_v16hi_mask, __builtin_ia32_vpshrdv_v16hi_maskz, __builtin_ia32_vpshrdv_v8hi, __builtin_ia32_vpshrdv_v8hi_mask, __builtin_ia32_vpshrdv_v8hi_maskz, __builtin_ia32_vpshrdv_v8si, __builtin_ia32_vpshrdv_v8si_mask, __builtin_ia32_vpshrdv_v8si_maskz, __builtin_ia32_vpshrdv_v4si, __builtin_ia32_vpshrdv_v4si_mask, __builtin_ia32_vpshrdv_v4si_maskz, __builtin_ia32_vpshrdv_v4di, __builtin_ia32_vpshrdv_v4di_mask, __builtin_ia32_vpshrdv_v4di_maskz, __builtin_ia32_vpshrdv_v2di, __builtin_ia32_vpshrdv_v2di_mask, __builtin_ia32_vpshrdv_v2di_maskz, __builtin_ia32_vpshldv_v16hi, __builtin_ia32_vpshldv_v16hi_mask, __builtin_ia32_vpshldv_v16hi_maskz, __builtin_ia32_vpshldv_v8hi, __builtin_ia32_vpshldv_v8hi_mask, __builtin_ia32_vpshldv_v8hi_maskz, __builtin_ia32_vpshldv_v8si, __builtin_ia32_vpshldv_v8si_mask, __builtin_ia32_vpshldv_v8si_maskz, __builtin_ia32_vpshldv_v4si, __builtin_ia32_vpshldv_v4si_mask, __builtin_ia32_vpshldv_v4si_maskz, __builtin_ia32_vpshldv_v4di, __builtin_ia32_vpshldv_v4di_mask, __builtin_ia32_vpshldv_v4di_maskz, __builtin_ia32_vpshldv_v2di, __builtin_ia32_vpshldv_v2di_mask, __builtin_ia32_vpshldv_v2di_maskz, __builtin_ia32_vpopcountb_v32qi, __builtin_ia32_vpopcountb_v16qi, __builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v16hi, __builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi, __builtin_ia32_vpopcountw_v8hi_mask): Add " | OPTION_MASK_ISA_AVX512VL". * config/i386/avx512vbmi2intrin.h (_mm512_shrdi_epi16, _mm512_shrdi_epi32, _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32, _mm512_shrdi_epi64, _mm512_mask_shrdi_epi64, _mm512_maskz_shrdi_epi64, _mm512_shldi_epi16, _mm512_shldi_epi32, _mm512_mask_shldi_epi32, _mm512_maskz_shldi_epi32, _mm512_shldi_epi64, _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64, _mm512_shrdv_epi16, _mm512_shrdv_epi32, _mm512_mask_shrdv_epi32, _mm512_maskz_shrdv_epi32, _mm512_shrdv_epi64, _mm512_mask_shrdv_epi64, _mm512_maskz_shrdv_epi64, _mm512_shldv_epi16, _mm512_shldv_epi32, _mm512_mask_shldv_epi32, _mm512_maskz_shldv_epi32, _mm512_shldv_epi64, _mm512_mask_shldv_epi64, _mm512_maskz_shldv_epi64): Don't require avx512bw for these intrinsics. * config/i386/avx512bitalgintrin.h (_mm_bitshuffle_epi64_mask, _mm_mask_bitshuffle_epi64_mask): Likewise. * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET, OPTION_MASK_ISA_AVX512BITALG_SET): Or in OPTION_MASK_ISA_AVX512F_SET. (OPTION_MASK_ISA_AVX512F_UNSET): Or in OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET and OPTION_MASK_ISA_AVX512BITALG_UNSET. (OPTION_MASK_ISA2_AVX512F_UNSET, OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Define. (ix86_handle_option): For -mno-general-regs-only, clear from ix86_isa_flags2 OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET rather than just OPTION_MASK_ISA_MPX. For -mno-sse{,2,3,4,4.1,4.2,avx,avx2} and -mno-ssse3 clear OPTION_MASK_ISA2_AVX512F_UNSET bits from ix86_isa_flags2. For -mno-avx512f likewise, instead of masking individually listed ISAs. For -m{,no-}avx512{vpopcntdq,bitalg} adjust for moving from ix86_isa_flags2 to ix86_isa_flags. From-SVN: r255997
2017-12-22Enable AVX512BITALGJulia Koval1-3/+27
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BITALG_SET, OPTION_MASK_ISA_AVX512BITALG_UNSET): New. (ix86_handle_option): Handle -mavx512bitalg, fix 4VNNIW formatting. * config.gcc: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h. * config/i386/avx512bitalgintrin.h (_mm512_popcnt_epi8, _mm512_popcnt_epi16, _mm512_mask_popcnt_epi8, _mm512_maskz_popcnt_epi8, _mm512_mask_popcnt_epi16, _mm512_maskz_popcnt_epi16, _mm512_bitshuffle_epi64_mask, _mm256_popcnt_epi8, _mm512_mask_bitshuffle_epi64_mask, _mm256_mask_popcnt_epi8, _mm_popcnt_epi8, _mm256_maskz_popcnt_epi8, _mm_bitshuffle_epi64_mask, _mm256_popcnt_epi16, _mm_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask, _mm256_mask_bitshuffle_epi64_mask, _mm_popcnt_epi16, _mm_maskz_popcnt_epi8, _mm256_mask_popcnt_epi16, _mm256_maskz_popcnt_epi16, _mm_mask_popcnt_epi8, _mm_mask_popcnt_epi16, _mm_maskz_popcnt_epi16): New intrinsics. * config/i386/avx512vpopcntdqvlintrin.h (_mm_popcnt_epi32, _mm_popcnt_epi64, _mm_mask_popcnt_epi32, _mm_maskz_popcnt_epi32, _mm256_popcnt_epi32, _mm256_mask_popcnt_epi32, _mm256_maskz_popcnt_epi32, _mm_mask_popcnt_epi64, _mm_maskz_popcnt_epi64, _mm256_popcnt_epi64, _mm256_mask_popcnt_epi64, _mm256_maskz_popcnt_epi64): New intrinsics. * config/i386/cpuid.h (bit_AVX512BITALG): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mavx512bitalg. * config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI, V64QI_FTYPE_V64QI, V4DI_FTYPE_V4DI, UHI_FTYPE_V2DI_V2DI_UHI, USI_FTYPE_V4DI_V4DI_USI, V4SI_FTYPE_V4SI_V4SI_UHI, V8SI_FTYPE_V8SI_V8SI_UHI): New types. * config/i386/i386-builtin.def (__builtin_ia32_vpopcountq_v4di, __builtin_ia32_vpopcountq_v4di_mask, __builtin_ia32_vpopcountq_v2di, __builtin_ia32_vpopcountq_v2di_mask, __builtin_ia32_vpopcountd_v4si, __builtin_ia32_vpopcountd_v4si_mask, __builtin_ia32_vpopcountd_v8si, __builtin_ia32_vpopcountd_v8si_mask, __builtin_ia32_vpopcountb_v64qi, __builtin_ia32_vpopcountb_v64qi_mask, __builtin_ia32_vpopcountb_v32qi, __builtin_ia32_vpopcountb_v32qi_mask, __builtin_ia32_vpopcountb_v16qi, __builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v32hi, __builtin_ia32_vpopcountw_v32hi_mask, __builtin_ia32_vpopcountw_v16hi, __builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi, __builtin_ia32_vpopcountw_v8hi_mask, __builtin_ia32_vpshufbitqmb128_mask, __builtin_ia32_vpshufbitqmb256_mask, __builtin_ia32_vpshufbitqmb512_mask): New builtins. * config/i386/i386-c.c (__AVX512BITALG__): New. * config/i386/i386.c (isa2_opts): Add -mavx512bitalg. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_expand_args_builtin): Handle new types. * config/i386/i386.h (TARGET_AVX512BITALG, TARGET_AVX512BITALG_P): New. * config/i386/i386.opt: Add -mavx512bitalg. * config/i386/immintrin.h: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h. * config/i386/sse.md (VI48_AVX512VLBW): New iterator. (vpopcount<mode><mask_name>): Add more types. (avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): New. * doc/invoke.texi: Add -mavx512bitalg and -mavx512vpopcntdq. gcc/testsuite/ * g++.dg/other/i386-2.C: Add new options. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx512-check.h: Handle bit_AVX512BITALG. * gcc.target/i386/avx512bitalg-vpopcntb-1.c: New. * gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512vpopcntdqvl-vpopcntd-1.c: Ditto. * gcc.target/i386/avx512vpopcntdqvl-vpopcntq-1.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512bitalg): New. * gcc.target/i386/avx512vpopcntdq-vpopcntd-1.c: Add more types. * gcc.target/i386/avx512vpopcntdq-vpopcntd.c: Handle new intrinsics. * gcc.target/i386/avx512vpopcntdq-vpopcntq-1.c: Ditto. * gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto. Co-Authored-By: Sebastian Peryt <sebastian.peryt@intel.com> From-SVN: r255975
2017-12-22This is a follow up patch for pr83488 to fix an error in setting...Igor Tsimbalist1-8/+8
This is a follow up patch for pr83488 to fix an error in setting OPTION_MASK_ISA_AVX512VNNI_SET and OPTION_MASK_ISA_AVX512F_SET bits. There were both set in ix86_isa_flags2 while being defined in different ISA sets. Additionally move OPTION_MASK_ISA_AVX512VNNI_SET to ix86_isa_flags as it can be used with OPTION_MASK_ISA_AVX512VL_SET. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VNNI_SET): Or in OPTION_MASK_ISA_AVX512F_SET. (OPTION_MASK_ISA_AVX512F_UNSET): Or in OPTION_MASK_ISA_AVX512VNNI_UNSET. (ix86_handle_option): Adjust for OPTION_MASK_ISA_AVX512VNNI_*SET being in ix86_isa_flags. * config/i386/i386-builtin.def: Move VNNI builtins from ARGS2 section to ARGS. * config/i386/i386-c.c: Check for OPTION_MASK_ISA_AVX512VNNI in isa_flag instead of isa_flag2. * config/i386/i386.c (ix86_target_string): Move -mavx512vnni from isa_opts2 to isa_opts. * config/i386/i386.opt (mavx512vnni): Move from ix86_isa_flags2 to ix86_isa_flags. From-SVN: r255974
2017-12-21[arm] Fix assembler option rewrite alphabetical comparisonKyrylo Tkachov1-5/+5
* common/config/arm/arm-common.c (compare_opt_names): Add function comment. Use strcmp instead of manual loop. From-SVN: r255942
2017-12-21re PR target/83488 (ICE on a CET test-case)Jakub Jelinek1-24/+23
PR target/83488 * config/i386/i386.c (ix86_target_string): Move -mavx512vbmi2 and -mshstk entries from isa_opts2 to isa_opts and -mhle, -mmovbe, -mclzero and -mmwaitx entries from isa_opts to isa_opts2. (ix86_option_override_internal): Adjust for OPTION_MASK_ISA_{HLE,MOVBE,CLZERO,MWAITX} moving to ix86_isa_flags2 and OPTION_MASK_ISA_SHSTK moving to ix86_isa_flags. (BDESC_VERIFYS): Remove SPECIAL_ARGS2 related checks. (ix86_init_mmx_sse_builtins): Remove bdesc_special_args2 handling. Use def_builtin2 instead of def_builtin for OPTION_MASK_ISA_MWAITX and OPTION_MASK_ISA_CLZERO builtins. Use def_builtin instead of def_builtin2 for CET builtins. (ix86_expand_builtin): Remove bdesc_special_args2 handling. Fix up formatting in IX86_BUILTIN_RDPID code. * config/i386/i386-builtin.def: Move VBMI2 builtins from SPECIAL_ARGS2 section to SPECIAL_ARGS and from ARGS2 section to ARGS. * config/i386/i386.opt (mavx512vbmi2, mshstk): Move from ix86_isa_flags2 to ix86_isa_flags. (mhle, mmovbe, mclzero, mmwaitx): Move from ix86_isa_flags to ix86_isa_flags2. * config/i386/i386-c.c (ix86_target_macros_internal): Check for OPTION_MASK_ISA_{CLZERO,MWAITX} in isa_flag2 instead of isa_flag. Check for OPTION_MASK_ISA_{SHSTK,AVX512VBMI2} in isa_flag instead of isa_flag2. * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET): Or in OPTION_MASK_ISA_AVX512F_SET. (OPTION_MASK_ISA_AVX512F_UNSET): Or in OPTION_MASK_ISA_AVX512VBMI2_UNSET. (ix86_handle_option): Adjust for OPTION_MASK_ISA_{SHSTK,AVX512VBMI2}_*SET being in ix86_isa_flags and OPTION_MASK_ISA_{MOVBE,MWAITX,CLZERO}_*SET in ix86_isa_flags2. * gcc.target/i386/pr83488.c: New test. From-SVN: r255937
2017-12-20Enable VPCLMULQDQ supportJulia Koval1-4/+19
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_VPCLMULQDQ_SET, OPTION_MASK_ISA_VPCLMULQDQ_UNSET): New. (ix86_handle_option): Handle -mvpclmulqdq, move cx6 to flags2. * config.gcc: Include vpclmulqdqintrin.h. * config/i386/cpuid.h: Handle bit_VPCLMULQDQ. * config/i386/driver-i386.c (host_detect_local_cpu): Handle -mvpclmulqdq. * config/i386/i386-builtin.def (__builtin_ia32_vpclmulqdq_v2di, __builtin_ia32_vpclmulqdq_v4di, __builtin_ia32_vpclmulqdq_v8di): New. * config/i386/i386-c.c (__VPCLMULQDQ__): New. * config/i386/i386.c (isa2_opts): Add -mcx16. (isa_opts): Add -mpclmulqdq, remove -mcx16. (ix86_option_override_internal): Move mcx16 to flags2. (ix86_valid_target_attribute_inner_p): Add vpclmulqdq. (ix86_expand_builtin): Handle OPTION_MASK_ISA_VPCLMULQDQ. * config/i386/i386.h (TARGET_VPCLMULQDQ, TARGET_VPCLMULQDQ_P): New. * config/i386/i386.opt: Add mvpclmulqdq, move mcx16 to flags2. * config/i386/immintrin.h: Include vpclmulqdqintrin.h. * config/i386/sse.md (vpclmulqdq_<mode>): New pattern. * config/i386/vpclmulqdqintrin.h (_mm512_clmulepi64_epi128, _mm_clmulepi64_epi128, _mm256_clmulepi64_epi128): New intrinsics. * doc/invoke.texi: Add -mvpclmulqdq. gcc/testsuite/ * gcc.target/i386/avx-1.c: Handle new intrinsics. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx512-check.h: Handle bit_VPCLMULQDQ. * gcc.target/i386/avx512f-vpclmulqdq-2.c: New test. * gcc.target/i386/avx512vl-vpclmulqdq-2.c: Ditto. * gcc.target/i386/vpclmulqdq.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_vpclmulqdq): New. From-SVN: r255850
2017-12-12Enable VAES support [1/5]Julia Koval1-0/+15
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_VAES_SET, OPTION_MASK_ISA_VAES_UNSET): New. (ix86_handle_option): Handle -mvaes. * config/i386/cpuid.h: Define bit_VAES. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mvaes. * config/i386/i386-c.c (__VAES__): New. * config/i386/i386.c (ix86_target_string): Add -mvaes. (ix86_valid_target_attribute_inner_p): Ditto. * config/i386/i386.h (TARGET_VAES, TARGET_VAES_P): New. * config/i386/i386.opt: Add -mvaes. * doc/invoke.texi: Ditto. From-SVN: r255571
2017-12-08[arm] Don't strip off all architecture features from -march passed to assemblerRichard Earnshaw1-12/+87
When GCC invokes the assembler it generates a sanitized version of the user-specified -march option to pass through, since the assembler does not understand all the new FPU-related architectural options. Unfortunately it goes too far and strips off all the architectural extensions, including some that are unrelated to the -mfpu variant selected. Again, this doesn't really matter when compiling C code because the compiler will override the command-line specified architecture with directives in the assembly file itself, but when using the compiler driver to invoke the assembler the only indiciation of the desired architecture might come from the command line. We fix this by adjusting the canonicalization pass to remove any option that only specifies features that can be expressed by -mfpu (any that go beyond that are already supported by the assembler). We do have to take care to re-order the options, though as the assembler expects feature options to be in a canonical order (unlike the compiler, where ordering is handled left-to-right: there's only a difference if there are negation options, but a canonicalized architecture string shouldn't have any of those). We do this by recording which options we need and then sorting the final list alphabetically. * common/config/arm/arm-common.c: Include <algorithm>. (INCLUDE_VECTOR): Define. (compare_opt_names): New function. (arm_rewrite_selected_arch): Only strip out extensions that can be expressed through -mfpu. Sort the remaining extensions alphabetically. From-SVN: r255503
2017-12-08[arm] Generate a -mfpu= option for passing to the assemblerRichard Earnshaw1-0/+80
When gcc runs with the new -mfpu=auto option (either explicitly or when that's the default behaviour) then this option is not passed through to the assembler as we cannot rely on the assembler understanding it (currently it doesn't understand it at all, but in future that might change). That means that the assembler falls back to its builtin default, which may not correspond to what the user expected based on the command-line options they passed. Normally that wouldn't matter because assembler files generated by the compiler will contain explicit directives that set the FPU type directly and override any internal defaults; but when the compiler driver is used to invoke the assembler directly (because the source file ends in .s or .S) then this might cause a problem if that assumes the FPU matches the compiler. To address this, this patch makes the driver construct a -mfpu= option for the assembler in the same way as the compiler generates an internal .fpu directive. As mentioned, this makes no difference if the assembler file explicitly overrides the command line options, but helps in the case where this is implicit. * config/arm/arm.h (arm_asm_auto_mfpu): Declare. (ASM_CPU_SPEC_FUNCTIONS): Add new rule asm_auto_mfpu. (ASM_CPU_SPEC): Use it if -mfpu is set to auto. * common/config/arm/arm-common.c (arm_asm_auto_mfpu): New function. -- This line, and those below, will be ignored-- M gcc/ChangeLog M gcc/common/config/arm/arm-common.c M gcc/config/arm/arm.h From-SVN: r255502
2017-12-05Enable VNNI support [1/5]Julia Koval1-0/+17
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VNNI_SET, OPTION_MASK_ISA_AVX512VNNI_UNSET): New. (ix86_handle_option): Handle -mavx512vnni. * config/i386/cpuid.h (bit_AVX512VNNI): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Handle new bit. * config/i386/i386-c (__AVX512VNNI__): New. * config/i386/i386.c (ix86_target_string): Handle new option. (ix86_valid_target_attribute_inner_p): Handle new option. * config/i386/i386.h (TARGET_AVX512VNNI, TARGET_AVX512VNNI_P): New. * config/i386/i386.opt (mavx512vnni): New option. From-SVN: r255401
2017-11-16Set default to -fomit-frame-pointerWilco Dijkstra35-168/+0
Almost all targets add an explict -fomit-frame-pointer in the target specific options. Rather than doing this in a target-specific way, do this in the generic options so it works identically across all targets. In many cases the target no longer needs to define TARGET_OPTION_OPTIMIZATION_TABLE, reducing the amount of target code. gcc/ * opts.c (default_options_table): Add OPT_fomit_frame_pointer entry. * common/config/alpha/alpha-common.c (TARGET_OPTION_OPTIMIZATION_TABLE): Remove OPT_fomit_frame_pointer entry. * common/config/arc/arc-common.c: Likewise. * common/config/arm/arm-common.c: Likewise. * common/config/avr/avr-common.c: Likewise. * common/config/c6x/c6x-common.c: Likewise. * common/config/cr16/cr16-common.c: Likewise. * common/config/cris/cris-common.c: Likewise. * common/config/epiphany/epiphany-common.c: Likewise. * common/config/fr30/fr30-common.c: Likewise. * common/config/frv/frv-common.c: Likewise. * common/config/ia64/ia64-common.c: Likewise. * common/config/iq2000/iq2000-common.c: Likewise. * common/config/lm32/lm32-common.c: Likewise. * common/config/m32r/m32r-common.c: Likewise. * common/config/mcore/mcore-common.c: Likewise. * common/config/microblaze/microblaze-common.c: Likewise. * common/config/mips/mips-common.c: Likewise. * common/config/mmix/mmix-common.c: Likewise. * common/config/mn10300/mn10300-common.c: Likewise. * common/config/nios2/nios2-common.c: Likewise. * common/config/pa/pa-common.c: Likewise. * common/config/pdp11/pdp11-common.c: Likewise. * common/config/powerpcspe/powerpcspe-common.c: Likewise. * common/config/riscv/riscv-common.c: Likewise. * common/config/rs6000/rs6000-common.c: Likewise. * common/config/rx/rx-common.c: Likewise. * common/config/s390/s390-common.c: Likewise. * common/config/sh/sh-common.c: Likewise. * common/config/sparc/sparc-common.c: Likewise. * common/config/tilegx/tilegx-common.c: Likewise. * common/config/tilepro/tilepro-common.c: Likewise. * common/config/v850/v850-common.c: Likewise. * common/config/visium/visium-common.c: Likewise. * common/config/xstormy16/xstormy16-common.c: Likewise. * common/config/xtensa/xtensa-common.c: Likewise. doc/ * invoke.texi (-fomit-frame-pointer): Update documentation. From-SVN: r254815
2017-11-16Add new options: -mext-perf, -mext-perf2, -mext-string.Chung-Ju Wu1-4/+8
gcc/ * config/nds32/nds32.opt: Add mext-perf, mext-perf2, mext-string. * config/nds32/nds32.opt: Refine the layout. * config/nds32/nds32.c (TARGET_EXT_PERF, TARGET_EXT_PERF2, TARGET_EXT_STRING): Support new options. * config/nds32/nds32.h: Likewise. * config/nds32/nds32.md: Likewise. * config/nds32/nds32-predicates.c: Likewise. * config/nds32/constraints.md: Likewise. * common/config/nds32/nds32-common.c: Likewise. Co-Authored-By: Kito Cheng <kito.cheng@gmail.com> From-SVN: r254798
2017-11-16Enable VBMI2 support [1/7]Julia Koval1-0/+17
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET, OPTION_MASK_ISA_AVX512VBMI2_UNSET): New. (ix86_handle_option): Handle -mavx512vbmi2. * config/i386/cpuid.h: Add bit_AVX512VBMI2. * config/i386/driver-i386.c (host_detect_local_cpu): Handle new bit. * config/i386/i386-c.c (__AVX512VBMI2__): New. * config/i386/i386.c (ix86_target_string): Handle -mavx512vbmi2. (ix86_valid_target_attribute_inner_p): Ditto. * config/i386/i386.h (TARGET_AVX512VBMI2, TARGET_AVX512VBMI2_P): New. * config/i386/i386.opt (mavx512vbmi2): New option. * doc/invoke.texi: Add new option. From-SVN: r254796
2017-11-07Fix SSE bits dependencies.Julia Koval1-6/+9
gcc/ PR target/82812 * common/config/i386/i386-common.c (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): Remove MPX from flag. (ix86_handle_option): Move MPX to isa_flags2 and GFNI to isa_flags. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto. * config/i386/i386.opt: Ditto. * config/i386/i386.c (ix86_target_string): Ditto. (ix86_option_override_internal): Ditto. (ix86_init_mpx_builtins): Move MPX to args2. (ix86_expand_builtin): Special handling for OPTION_MASK_ISA_GFNI. * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineinvqb_v64qi, __builtin_ia32_vgf2p8affineinvqb_v64qi_mask, __builtin_ia32_vgf2p8affineinvqb_v32qi, __builtin_ia32_vgf2p8affineinvqb_v32qi_mask, __builtin_ia32_vgf2p8affineinvqb_v16qi, __builtin_ia32_vgf2p8affineinvqb_v16qi_mask): Move to ARGS array. From-SVN: r254507
2017-10-21Update x86 backend to enable Intel CET.Igor Tsimbalist1-0/+33
All platforms except i386 will report the error and do no instrumentation with -finstrument-control-flow option. i386 will provide the implementation based on a specification published by Intel for a new technology called Control-flow Enforcement Technology (CET). The spec is available at https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf The implementation in this patch: 1) enables Control-flow Enforcement Technology (CET), published by Intel. This part introduces i386 specific options -mcet, -mibt and -mshstk, new instructions and intrinsics; 2) provides support for -fcf-protection option and 'nocf_check' attribute by doing needed code instrumentation, which is based on CET features. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New. (OPTION_MASK_ISA_SHSTK_SET): Likewise. (OPTION_MASK_ISA_IBT_UNSET): Likewise. (OPTION_MASK_ISA_SHSTK_UNSET): Likewise. (ix86_handle_option): Add -mibt, -mshstk, -mcet handling. * config.gcc (extra_headers): Add cetintrin.h for x86 targets. (extra_objs): Add cet.o for Linux/x86 targets. (tmake_file): Add i386/t-cet for Linux/x86 targets. * config/i386/cet.c: New file. * config/i386/cetintrin.h: Likewise. * config/i386/t-cet: Likewise. * config/i386/cpuid.h (bit_SHSTK): New. (bit_IBT): Likewise. * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass IBT and SHSTK bits. * config/i386/i386-builtin-types.def (VOID_FTYPE_UNSIGNED_PVOID): New. (VOID_FTYPE_UINT64_PVOID): Likewise. * config/i386/i386-builtin.def: Add CET intrinsics. * config/i386/i386-c.c (ix86_target_macros_internal): Add OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling. * config/i386/i386-passes.def: Add pass_insert_endbranch pass. * config/i386/i386-protos.h (make_pass_insert_endbranch): New prototype. * config/i386/i386.c (rest_of_insert_endbranch): New. (pass_data_insert_endbranch): Likewise. (pass_insert_endbranch): Likewise. (make_pass_insert_endbranch): Likewise. (ix86_notrack_prefixed_insn_p): Likewise. (ix86_target_string): Add -mibt, -mshstk flags. (ix86_option_override_internal): Add flag_cf_protection processing. (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk. (ix86_print_operand): Add 'notrack' prefix output. (ix86_init_mmx_sse_builtins): Add CET intrinsics. (ix86_expand_builtin): Expand CET intrinsics. (x86_output_mi_thunk): Add 'endbranch' instruction. * config/i386/i386.h (TARGET_IBT): New. (TARGET_IBT_P): Likewise. (TARGET_SHSTK): Likewise. (TARGET_SHSTK_P): Likewise. * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP, UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP, UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY. (builtin_setjmp_setup): New pattern. (builtin_longjmp): Likewise. (rdssp<mode>): Likewise. (incssp<mode>): Likewise. (saveprevssp): Likewise. (rstorssp): Likewise. (wrss<mode>): Likewise. (wruss<mode>): Likewise. (setssbsy): Likewise. (clrssbsy): Likewise. (nop_endbr): Likewise. * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch options. * config/i386/immintrin.h: Include <cetintrin.h>. * config/i386/linux-common.h (file_end_indicate_exec_stack_and_cet): New prototype. (TARGET_ASM_FILE_END): New. From-SVN: r253977
2017-10-20Add GFNI command line options and macrosJulia Koval1-0/+15
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_GFNI_SET, (OPTION_MASK_ISA_GFNI_UNSET): New. (ix86_handle_option): Handle OPT_mgfni. * config/i386/cpuid.h (bit_GFNI): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect gfni. * config/i386/i386-c.c (ix86_target_macros_internal): Define __GFNI__. * config/i386/i386.c (ix86_target_string): Add -mgfni. (ix86_valid_target_attribute_inner_p): Add OPT_mgfni. * config/i386/i386.h (TARGET_GFNI, TARGET_GFNI_P): New. * config/i386/i386.opt: Add mgfni. From-SVN: r253922
2017-10-08arm-common.c (arm_except_unwind_info): Handle DWARF2_UNWIND_INFO.Olivier Hainque1-1/+7
2017-10-08 Olivier Hainque <hainque@adacore.com> * common/config/arm/arm-common.c (arm_except_unwind_info): Handle DWARF2_UNWIND_INFO. From-SVN: r253521
2017-09-22[arm] auto-generate arm-isa.h from CPU descriptionsRichard Earnshaw1-5/+5
This patch autogenerates arm-isa.h from new entries in arm-cpus.in. This has the primary advantage that it makes the description file more self-contained, but it also solves the 'array dimensioning' problem that Tamar recently encountered. It adds two new constructs to arm-cpus.in: features and fgroups. Fgroups are simply a way of naming a group of feature bits so that they can be referenced together. We follow the convention that feature bits are all lower case, while fgroups are (predominantly) upper case. This is helpful as in some contexts they share the same namespace. Most of the minor changes in this patch are related to adopting this new naming convention. 2017-09-22 Richard Earnshaw <richard.earnshaw@arm.com> * config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file. * config/arm/arm-isa.h: Delete. Move definitions to ... * arm-cpus.in: ... here. Use new feature and fgroup values. * config/arm/arm.c (arm_option_override): Use lower case for feature bit names. * config/arm/arm.h (TARGET_HARD_FLOAT): Likewise. (TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise. * config/arm/parsecpu.awk (END): Add new command 'isa'. (isa_pfx): Delete. (print_isa_bits_for): New function. (gen_isa): New function. (gen_comm_data): Use print_isa_bits_for. (define feature): New keyword. (define fgroup): New keyword. * config/arm/t-arm (TM_H): Remove. (GTM_H): Add arm-isa.h. (arm-isa.h): Add rule to generate file. * common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower case for feature bit names. From-SVN: r253097
2017-09-16Use -fsched-pressure and -fomit-frame-pointerChung-Ju Wu1-4/+6
in nds32_option_optimization_table. gcc/ * common/config/nds32/nds32-common.c (nds32_option_optimization_table): Refine formatting. (nds32_option_optimization_table): Use -fsched-pressure and -fomit-frame-pointer for specific optimization level. From-SVN: r252876
2017-09-112017-09-11 Vidya Praveen <vidyapraveen@arm.com>Vidya Praveen1-5/+5
Revert r251800 and r251799. From-SVN: r251980
2017-09-06[arm] auto-generate arm-isa.h from CPU descriptionsRichard Earnshaw1-5/+5
This patch autogenerates arm-isa.h from new entries in arm-cpus.in. This has the primary advantage that it makes the description file more self-contained, but it also solves the 'array dimensioning' problem that Tamar recently encountered. It adds two new constructs to arm-cpus.in: features and fgroups. Fgroups are simply a way of naming a group of feature bits so that they can be referenced together. We follow the convention that feature bits are all lower case, while fgroups are (predominantly) upper case. This is helpful as in some contexts they share the same namespace. Most of the minor changes in this patch are related to adopting this new naming convention. * config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file. * config/arm/arm-isa.h: Delete. Move definitions to ... * arm-cpus.in: ... here. Use new feature and fgroup values. * config/arm/arm.c (arm_option_override): Use lower case for feature bit names. * config/arm/arm.h (TARGET_HARD_FLOAT): Likewise. (TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise. * config/arm/parsecpu.awk (END): Add new command 'isa'. (isa_pfx): Delete. (print_isa_bits_for): New function. (gen_isa): New function. (gen_comm_data): Use print_isa_bits_for. (define feature): New keyword. (define fgroup): New keyword. * config/arm/t-arm (OPTIONS_H_EXTRA): Add arm-isa.h (arm-isa.h): Add rule to generate file. * common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower case for feature bit names. From-SVN: r251799
2017-07-10Better ISR prologues by supporting GASes __gcc_isr pseudo insn.Georg-Johann Lay1-0/+1
gcc/ Better ISR prologues by supporting GASes __gcc_isr pseudo insn. PR target/20296 PR target/81268 * configure.ac [target=avr]: Add GAS check for -mgcc-isr. (HAVE_AS_AVR_MGCCISR_OPTION): If so, AC_DEFINE it. * config.in: Regenerate. * configure: Regenerate. * doc/extend.texi (AVR Function Attributes) <no_gccisr>: Document it. * doc/invoke.texi (AVR Options) <-mgas-isr-prologues>: Document it. * config/avr/avr.opt (-mgas-isr-prologues): New option and... (TARGET_GASISR_PROLOGUES): ...target mask. * common/config/avr/avr-common.c (avr_option_optimization_table) [OPT_LEVELS_1_PLUS_NOT_DEBUG]: Set -mgas-isr-prologues. * config/avr/avr-passes.def (avr_pass_pre_proep): Add INSERT_PASS_BEFORE for it. * config/avr/avr-protos.h (make_avr_pass_pre_proep): New proto. * config/avr/avr.c (avr_option_override) [!HAVE_AS_AVR_MGCCISR_OPTION]: Unset TARGET_GASISR_PROLOGUES. (avr_no_gccisr_function_p, avr_hregs_split_reg): New static functions. (avr_attribute_table) <no_gccisr>: Add new function attribute. (avr_set_current_function) <is_no_gccisr>: Init machine field. (avr_pass_data_pre_proep, avr_pass_pre_proep): New pass data and rtl_opt_pass. (make_avr_pass_pre_proep): New function. (emit_push_sfr) <treg>: Add argument to function and use it instead of TMP_REG. (avr_expand_prologue) [machine->gasisr.maybe]: Emit gasisr insn and set machine->gasisr.yes. (avr_expand_epilogue) [machine->gasisr.yes]: Similar. (avr_asm_function_end_prologue) [machine->gasisr.yes]: Add __gcc_isr.n_pushed to .L__stack_usage. (TARGET_ASM_FINAL_POSTSCAN_INSN): Define to... (avr_asm_final_postscan_insn): ...this new static function. * config/avr/avr.h (machine_function) <is_no_gccisr, use_L__stack_usage>: New fields. <gasisr, gasisr.yes, gasisr.maybe, gasisr.regno>: New fields. * config/avr/avr.md (UNSPECV_GASISR): Add unspecv enum. (GASISR_Prologue, GASISR_Epilogue, GASISR_Done): New define_constants. (gasisr, *gasisr): New expander and insn. * config/avr/gen-avr-mmcu-specs.c (print_mcu) [HAVE_AS_AVR_MGCCISR_OPTION]: Print asm_gccisr spec. * config/avr/specs.h (ASM_SPEC) <asm_gccisr>: Add sub spec. From-SVN: r250093
2017-07-04[arm] Move some generated files out of the source treeRichard Earnshaw1-1/+1
When I originally started work on the new options framework for ARM I'd worked on the assumption that AWK might not be available on every build machine (only on developer's machines). However, looking again I notice that all the options framework relies on it being present for every build. This means that some of the generated files that come from running parsecpu.awk do not need to be kept under revision control. Unfortunately, it's not _all_ generated files. The build infrastructure assumes that all .md fragments are in the source tree and similarly that all .opt fragments are there as well. Still, eliminating the very big .h files is a step forward as they are very regular in structure and diff/patch/merge tools can sometimes make mistakes when resolving conflicts. So this patch removes the generated .h files from the source tree and tweaks the make rules accordingly. I've also changed the build rules to use the stamp technique to eliminate some false dependencies in a rebuild. Top-level: * contrib/gcc_update (files_and_dependencies): Remove stamp rules for arm-specific auto-generated header files. gcc: * common/config/arm/arm-common.c: Adjust include path for arm-cpu-cdata.h * t-arm (TM_H): Adjust path for arm-cpu.h. (arm-cpu.h): Create in build directory. Adjust dependency rules. (arm-cpu-data.h): Likewise. (arm-cpu-cdata.h): Likewise. * config/arm/arm-cpu.h: Delete. * config/arm/arm-cpu-cdata.h: Delete. * config/arm/arm-cpu-data.h: Delete. From-SVN: r249971
2017-07-03[arm] Clean up generation of BE8 format images.Richard Earnshaw1-0/+57
The existing code in arm/bpabi.h was quite fragile and relied on matching specific CPU and/or architecture names. The introduction of the option format for -mcpu and -march broke that in a way that would be non-trivial to fix by updating the list. The hook in that file was always a pain as it required every new CPU being added to be add an update here as well (easy to miss). I've fixed that problem once and for all by adding a new callback into the driver to select the correct BE8 behaviour. This uses features in the ISA capabilities list to select whether or not to use BE8 format during linking. I also noticed that if the user happened to pass both -mbig-endian and -mlittle-endian on the command line then the linker spec rules would get somewhat confused and potentially do the wrong thing. I've fixed that by marking these options as opposites in the option descriptions. The driver will now automatically suppress overridden options leading to the correct desired behavior. Whilst fixing this I noticed a couple of anomolus cases in the existing BE8 support: we were not generating BE8 format for ARMv6 or ARMv7-R targets. While the ARMv6 status was probably deliberate at the time, this is probably not a good idea in the long term as the alternative, BE32, has been deprecated by ARM. After discussion with a couple of colleagues I've decided to change this, but to then add an option to restore the existing behaviour at the user's option. So this patch introduces two new options (opposites) -mbe8 and -mbe32. This is a quiet behavior change, so I'll add a comment to the release notes shortly. * common/config/arm/arm-common.c (arm_be8_option): New function. * config/arm/arm-isa.h (isa_feature): Add new feature bit isa_bit_be8. (ISA_ARMv6): Add isa_bit_be8. * config/arm/arm.h (arm_be8_option): Add prototype. (BE8_SPEC_FUNCTION): New define. (EXTRA_SPEC_FUNCTIONS): Add BE8_SPEC_FUNCTION. * config/arm/arm.opt (mbig-endian): Mark as Negative of mlittle-endian. (mlittle-endian): Similarly. (mbe8, mbe32): New options. * config/arm/bpabi.h (BE8_LINK_SPEC): Call arm_be8_option. * doc/invoke.texi (ARM Options): Document -mbe8 and -mbe32. From-SVN: r249909
2017-06-16[arm] Rewrite t-aprofile using new selector methodologyRichard Earnshaw1-1/+3
Now that the default FPU is 'auto' we can finally rewrite (and simplify) the rules for mapping compiler options to multilibs. We no-longer need to know the specific CPU, since the driver will construct a suitable -march flag for us; this greatly simplifies the overall logic. This patch rewrites the library list for A-profile cores. We use various Make extention rules to simplify the logic even further. A couple of minor tweaks to the configure script and to the main driver ensures that we always know the setting of -mfloat-abi and -marm/-mthumb. Again, this helps simplify the logic further. The change to arm_target_thumb_only relies on the fact that this routine is only called if neither -marm nor -mthumb has been previously selected or specified by the user. A new testsuite module is added to check the libraries generated. The new tests are only run if the compiler is configured with the relevant multilibs enabled. gcc: * config.gcc: (arm*-*-*): When building a-profile libraries, force the driver to pass through the default setting of -mfloat-abi. * common/config/arm/arm-common.c (arm_target_thumb_only): Return -marm rather than NULL. * config/arm/t-multilib (MULTILIB_REUSE): Initialize to empty. (all_feat_combs): New rule. (MULTILIB_OPTIONS): Use explicit ARM and Thumb directories. Rework default libraries. * config/arm/t-aprofile: Rewrite. gcc/testsuite: * gcc.target/arm/multilibs.exp: New file. From-SVN: r249296
2017-06-16[arm] Make 'auto' the default FPU selection option.Richard Earnshaw1-1/+1
Finally, we can make 'auto' the default choice for the FPU option. It's still possible to override this during configure, but we will eventually deprecate that, moving to the new cpu/architecture selection mechanism. * config/arm/arm.h (FPUTYPE_AUTO): Define. * config/arm/arm.c (arm_option_override): Use FPUTYPE_AUTO if the fpu is not specified by the user/command-line. * config/arm/bpabi.h (FPUTYPE_DEFAULT): Delete. * config/arm/netbsd-elf.h (FPUTYPE_DEFAULT): Delete. * config/arm/linux-elf.h (FPUTYPE_DEFAULT): Delete. * config/arm/vxworks.h (FPUTYPE_DEFAULT): Delete. * common/config/arm/arm-common.c (arm_canon_arch_option): Use FPUTYPE_AUTO insted of FPUTYPE_DEFAULT. From-SVN: r249295
2017-06-16[arm] Generate a canonical form for -marchRichard Earnshaw1-0/+354
This patch uses the driver and some spec rewrite rules to generate a canonicalized form of the -march= option. We want to do this for several reasons, all relating to making multi-lib selection sane. 1) It can remove redundant extension options to produce a minimal list. 2) The general syntax of the option permits a plethora of features, these are permitted in any order. Canonicalization ensures that there is a single ordering of the options that are needed. 3) It can use additional options to remove extensions that aren't relevant, such as removing all features that relate to the FPU when use of that is disabled. Once we have this information in a sensible form the multilib rules can be vastly simplified making for much more understandable Makefile fragments. * common/config/arm/arm-common.c: Define INCLUDE_LIST. (configargs.h): Include it. (arm_print_hint_for_fpu_option): New function. (arm_parse_fpu_option): New function. (candidate_extension): New class. (arm_canon_for_multilib): New function. * config/arm/arm.h (CANON_ARCH_SPEC_FUNCTION): New macro. (EXTRA_SPEC_FUNCTIONS): Add CANON_ARCH_SPEC_FUNCTION. (ARCH_CANONICAL_SPECS): New macro. (DRIVER_SELF_SPECS): Add ARCH_CANONICAL_SPECS. From-SVN: r249292
2017-06-16[arm] Use standard option parsing code for detectingRichard Earnshaw1-19/+47
Now that the standard CPU and architecture option parsing code is available in the driver we can use the main CPU and architecture data tables for driving the automatic enabling of Thumb code. Doing this requires that the driver script tell the parser whether or not the target string is a CPU name or an architecture, but beyond that it is just standard use of the new capabilities. We do, however, now get some error checking if the target isn't recognized, when previously we just ignored unknown targets and hoped that a later pass would pick up on this. * config/arm/arm.h (TARGET_MODE_SPECS): Add additional parameter to call to target_mode_check describing the type of option passed. * common/config/arm/arm-common.c (arm_arch_core_flag): Delete. (arm_target_thumb_only): Use arm_parse_arch_option_name or arm_parse_cpu_option_name to match parameters against list of available targets. * config/arm/parsecpu.awk (gen_comm_data): Don't generate arm_arch_core_flags data structure. * config/arm/arm-cpu_cdata.h: Regenerated. From-SVN: r249288
2017-06-16[arm] Move cpu and architecture option name parsingRichard Earnshaw1-0/+190
This patch has no functional change. The code used for parsing -mcpu, -mtune and -march options is simply moved from arm.c arm-common.c. The list of FPU options is also moved. Subsequent patches will make use of this within the driver. Some small adjustments are needed as a consequence of moving the definitions of the data objects to another object file, in that we no-longer have direct access to the size of the object. * common/config/arm/arm-common.c (arm_initialize_isa): Moved here from config/arm/arm.c. (arm_print_hint_for_cpu_option): Likewise. (arm_print_hint_for_arch_option): Likewise. (arm_parse_cpu_option_name): Likewise. (arm_parse_arch_option_name): Likewise. * config/arm/arm.c (arm_identify_fpu_from_isa): Use the computed number of entries in the all_fpus list. * config/arm/arm-protos.h (all_architectures, all_cores): Declare. (arm_parse_cpu_option_name): Declare. (arm_parse_arch_option_name): Declare. (arm_parse_option_features): Declare. (arm_intialize_isa): Declare. * config/arm/parsecpu.awk (gen_data): Move CPU and architecture data tables to ... (gen_comm_data): ... here. Make definitions non-static. * config/arm/arm-cpu-data.h: Regenerated. * config/arm/arm-cpu-cdata.h: Regenerated. From-SVN: r249287
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