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5 dayss390: Support z17 processor nameStefan Schulze Frielinghaus1-2/+2
The recently announced IBM z17 processor implements the architecture already supported as arch15. This patch adds support for z17 as an alternative architecture name for arch15. gcc/ChangeLog: * common/config/s390/s390-common.cc: Rename arch15 to z17. * config.gcc: Add z17. * config/s390/driver-native.cc: Detect z17 machine. * config/s390/s390-builtins.def (B_VXE3): Rename arch15 to z17. * config/s390/s390-c.cc (s390_resolve_overloaded_builtin): Ditto. * config/s390/s390-opts.h (enum processor_type): Ditto. * config/s390/s390.cc: Ditto. * config/s390/s390.h: Ditto. * config/s390/s390.md: Ditto. * config/s390/s390.opt: Add z17. * doc/invoke.texi: Ditto.
2025-04-01target/119549 - fixup handling of -mno-sse4 in target attributeRichard Biener1-0/+2
The following fixes ix86_valid_target_attribute_inner_p to properly handle target("no-sse4") via OPT_mno_sse4 rather than as unset OPT_msse4. I've added asserts to ix86_handle_option that RejectNegative is honored for both. PR target/119549 * common/config/i386/i386-common.cc (ix86_handle_option): Assert that both OPT_msse4 and OPT_mno_sse4 are never unset. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Process negated OPT_msse4 as OPT_mno_sse4. * gcc.target/i386/pr119549.c: New testcase.
2025-03-24i386: Raise deprecate warning for -mavx10.1-256/512 and -mevex512 while add ↵Haochen Jiang4-16/+17
-mavx10.1 back with 512 bit alias When AVX10.1 options are added into GCC 14, E-core is supposed to support up to 256 bit vector width, while P-core up to 512 bit vector width. Therefore, we added avx10.1-256 and avx10.1-512 options into compiler since there will be real platforms with 256 bit only support. At the same time, for old platforms could also compile a 256 bit only binary, we introduced -mno-evex512 to disable 512 bit vector. However, all the future platforms will now support 512 bit vector width, including P-core and E-core. It will result in no need for split the option for vector width. Therefore, we will remove them in this patch. Unlike AVX10.2 options, AVX10.1 options has been there in a major release, so we have to raise a deprecate warning in GCC 15 and remove them in GCC 16. At the same time, to align with avx10.2 options, we will add just removed avx10.1 option back with warning to mention its behavior change. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Change to FEATURE_AVX10_1. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_512_SET): Renamed to ... (OPTION_MASK_ISA2_AVX10_1_SET): ... this. (OPTION_MASK_ISA2_AVX10_2_SET): Use renamed macro. (OPTION_MASK_ISA2_AVX10_1_UNSET): Ditto. (ix86_handle_option): Ditto. (processor_alias_table): Use P_PROC_AVX10_1. * common/config/i386/i386-cpuinfo.h (enum feature_priority): Rename from AVX10_1_512 to AVX10_1. (enum processor_features): Ditto. * common/config/i386/i386-isas.h: Add avx10.1. * config/i386/driver-i386.cc (host_detect_local_cpu): Use renamed enum. * config/i386/i386-c.cc (ix86_target_macros_internal): Rename to avx10.1. * config/i386/i386-isa.def (AVX10_1_512): Rename to ... (AVX10_1): ... this. * config/i386/i386-options.cc (isa2_opts): Rename to avx10.1. (ix86_valid_target_attribute_inner_p): Add avx10.1. (ix86_option_override_internal): Rename to AVX10_1. Revise warnings to mention behavior change for option combination in GCC 16. * config/i386/i386.h (PTA_DIAMONDRAPIDS): Use AVX10_1. * config/i386/i386.opt: Add avx10.1. Add deprecate warnings for mevex512 and mavx10.1-256/512. * config/i386/i386.opt.urls: Add avx10.1. * doc/extend.texi: Ditto. * doc/sourcebuild.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10-check.h: Change to avx10.1. * gcc.target/i386/avx10_1-1.c: Add warning check. * gcc.target/i386/avx10_1-10.c: Ditto. * gcc.target/i386/avx10_1-11.c: Ditto. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-15.c: Ditto. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-20.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-26.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/avx10_1-7.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-9.c: Ditto. * gcc.target/i386/noevex512-1.c: Ditto. * gcc.target/i386/noevex512-2.c: Ditto. * gcc.target/i386/pr111068.c: Ditto. * gcc.target/i386/pr111907.c: Ditto. * gcc.target/i386/pr117240_avx512f.c: Ditto. * gcc.target/i386/pr117304-1.c: Ditto. * gcc.target/i386/pr117946.c: Ditto. * gcc.target/i386/avx10_1-24.c: Removed. * gcc.target/i386/avx10_1-25.c: Removed. * gcc.target/i386/avx10_1-5.c: Removed. * gcc.target/i386/avx10_1-6.c: Removed.
2025-03-24i386: Remove avx10.2-256 and avx10.2-512 optionsHaochen Jiang4-51/+22
When AVX10.2 options are added into GCC 15, E-core is supposed to support up to 256 bit vector width, while P-core up to 512 bit vector width. Therefore, we added avx10.2-256 and avx10.2-512 options into compiler since there will be real platforms with 256 bit only support. However, all the future platforms will now support 512 bit vector width, including P-core and E-core. It will result in no need for split the option for vector width. Therefore, we will remove them in this patch. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Revise the logic AVX10 version. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_2_256_SET): Removed. (OPTION_MASK_ISA2_AVX10_2_512_SET): Ditto. (OPTION_MASK_ISA2_AVX10_2_SET): New. (OPTION_MASK_ISA2_AMX_AVX512_SET): Use AVX10.2 macro. (OPTION_MASK_ISA2_AVX10_2_UNSET): Ditto. (ix86_handle_option): Remove avx10.2-256 part. Adjust avx10.2. * common/config/i386/i386-cpuinfo.h (enum processor_features): Remove FEATURE_AVX10_2_256 and skip the value for it. Change the name from FEATURE_AVX10_2_512 to FEATURE_AVX10_2. * common/config/i386/i386-isas.h: Remove avx10.2-256/512. * config/i386/avx10_2-512bf16intrin.h: Use avx10.2 instead of avx10.2-256/512. * config/i386/avx10_2-512convertintrin.h: Ditto. * config/i386/avx10_2-512mediaintrin.h: Ditto. * config/i386/avx10_2-512minmaxintrin.h: Ditto. * config/i386/avx10_2-512satcvtintrin.h: Ditto. * config/i386/avx10_2bf16intrin.h: Ditto. * config/i386/avx10_2convertintrin.h: Ditto. * config/i386/avx10_2mediaintrin.h: Ditto. * config/i386/avx10_2minmaxintrin.h: Ditto. * config/i386/avx10_2satcvtintrin.h: Ditto. * config/i386/movrsintrin.h: Ditto. * config/i386/sm4intrin.h: Ditto. * config/i386/cpuid.h (bit_AVX10_256): Removed. (bit_AVX10_512): Ditto. * config/i386/driver-i386.cc (host_detect_local_cpu): Adjust Diamond Rapids and -march=native condition. * config/i386/i386-builtin.def (BDESC): Use AVX10.2 macro instead of AVX10.2-256/512. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-expand.cc (ix86_expand_branch): Use TARGET_AVX10_2 instead of specifying vector size. (ix86_prepare_fp_compare_args): Ditto. (ix86_expand_fp_compare): Ditto. (ix86_ssecom_setcc): Ditto. (ix86_expand_sse_comi): Ditto. (ix86_expand_sse_comi_round): Ditto. (ix86_check_builtin_isa_match): Ditto. * config/i386/i386.cc (ix86_fp_compare_code_to_integer): Ditto. (ix86_get_mask_mode): Ditto. * config/i386/i386.h (SSE_FLOAT_MODE_SSEMATH_OR_HFBF_P): Ditto. * config/i386/i386.md: Ditto. * config/i386/mmx.md: Ditto. * config/i386/sse.md: Ditto. * config/i386/predicates.md: Ditto. * config/i386/i386-isa.def (AVX10_2_256): Removed. (AVX10_2_512): Removed. (AVX10_2): New. * config/i386/i386-options.cc (isa2_opts): Remove avx10.2-256/512. (ix86_valid_target_attribute_inner_p): Ditto. (PTA_DIAMONDRAPIDS): Use PTA_AVX10_2. * config/i386/i386.opt: Remove avx10.2-256/512. * config/i386/i386.opt.urls: Ditto. * doc/extend.texi: Ditto. * doc/invoke.texi: Ditto. * doc/sourcebuild.texi: Ditto.
2025-03-22AVR: target/119421 Better optimize some bit operations.Georg-Johann Lay1-0/+1
There are occasions where knowledge about nonzero bits makes some optimizations possible. For example, Rd |= Rn << Off can be implemented as SBRC Rn, 0 ORI Rd, 1 << Off when Rn in { 0, 1 }, i.e. nonzero_bits (Rn) == 1. This patch adds some patterns that exploit nonzero_bits() in some combiner patterns. As insn conditions are not supposed to contain nonzero_bits(), the patch splits such insns right after pass insn combine. PR target/119421 gcc/ * config/avr/avr.opt (-muse-nonzero-bits): New option. * config/avr/avr-protos.h (avr_nonzero_bits_lsr_operands_p): New. (make_avr_pass_split_nzb): New. * config/avr/avr.cc (avr_nonzero_bits_lsr_operands_p): New function. (avr_rtx_costs_1): Return costs for the new insns. * config/avr/avr.md (nzb): New insn attribute. (*nzb=1.<code>...): New insns to better support some bit operations for <code> in AND, IOR, XOR. * config/avr/avr-passes.def (avr_pass_split_nzb): Insert pass atfer combine. * config/avr/avr-passes.cc (avr_pass_data_split_nzb). New pass data. (avr_pass_split_nzb): New pass. (make_avr_pass_split_nzb): New function. * common/config/avr/avr-common.cc (avr_option_optimization_table): Enable -muse-nonzero-bits for -O2 and higher. * doc/invoke.texi (AVR Options): Document -muse-nonzero-bits. gcc/testsuite/ * gcc.target/avr/torture/pr119421-sreg.c: New test.
2025-03-13libgcc: Remove PREDRES and LS64 from AArch64 cpuinfoWilco Dijkstra1-4/+4
Change AArch64 cpuinfo to follow the latest updates to the FMV spec [1]: Remove FEAT_PREDRES and FEAT_LS64*. Preserve the ordering in enum CPUFeatures. [1] https://github.com/ARM-software/acle/pull/382 gcc: * common/config/aarch64/cpuinfo.h: Remove FEAT_PREDRES and FEAT_LS64*. * config/aarch64/aarch64-option-extensions.def: Remove FMV support for PREDRES. libgcc: * config/aarch64/cpuinfo.c (__init_cpu_features_constructor): Remove FEAT_PREDRES and FEAT_LS64* support.
2025-03-06AArch64: Enable early scheduling for -O3 and higher (PR118351)Wilco Dijkstra1-1/+3
Enable the early scheduler on AArch64 for O3/Ofast. This means GCC15 benefits from much faster build times with -O2, but avoids the regressions in lbm which is very sensitive to minor scheduling changes due to long FMA chains. gcc: PR target/118351 PR other/38768 * common/config/aarch64/aarch64-common.cc: Enable early scheduling with -O3 and higher. * doc/invoke.texi (-fschedule-insns): Update comment.
2025-03-03aarch64: Ignore target pragmas while defining intrinsicsAndrew Carlotti1-2/+17
Refactor the switcher classes into two separate classes: - sve_alignment_switcher takes the alignment switching functionality, and is used only for ABI correctness when defining sve structure types. - aarch64_target_switcher takes the rest of the functionality of aarch64_simd_switcher and sve_switcher, and gates simd/sve specific parts upon the specified feature flags. Additionally, aarch64_target_switcher now adds dependencies of the specified flags (which adds +fcma and +bf16 to some intrinsic declarations), and unsets current_target_pragma. This last change fixes an internal bug where we would sometimes add a user specified target pragma (stored in current_target_pragma) on top of an internally specified target architecture while initialising intrinsics with `#pragma GCC aarch64 "arm_*.h"`. As far as I can tell, this has no visible impact at the moment. However, the unintended target feature combinations lead to unwanted behaviour in an under-development patch. This also fixes a missing Makefile dependency, which was due to aarch64-sve-builtins.o incorrectly depending on the undefined $(REG_H). The correct $(REGS_H) dependency is added to the switcher's new source location. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (struct aarch64_extension_info): Add field. (aarch64_get_required_features): New. * config/aarch64/aarch64-builtins.cc (aarch64_simd_switcher::aarch64_simd_switcher): Rename to... (aarch64_target_switcher::aarch64_target_switcher): ...this, and extend to handle sve, nosimd and target pragmas. (aarch64_simd_switcher::~aarch64_simd_switcher): Rename to... (aarch64_target_switcher::~aarch64_target_switcher): ...this, and extend to handle sve, nosimd and target pragmas. (handle_arm_acle_h): Use aarch64_target_switcher. (handle_arm_neon_h): Rename switcher and pass explicit flags. (aarch64_general_init_builtins): Ditto. * config/aarch64/aarch64-protos.h (class aarch64_simd_switcher): Rename to... (class aarch64_target_switcher): ...this, and add new members. (aarch64_get_required_features): New prototype. * config/aarch64/aarch64-sve-builtins.cc (sve_switcher::sve_switcher): Delete (sve_switcher::~sve_switcher): Delete (sve_alignment_switcher::sve_alignment_switcher): New (sve_alignment_switcher::~sve_alignment_switcher): New (register_builtin_types): Use alignment switcher (init_builtins): Rename switcher. (handle_arm_neon_sve_bridge_h): Ditto. (handle_arm_sme_h): Ditto. (handle_arm_sve_h): Ditto, and use alignment switcher. * config/aarch64/aarch64-sve-builtins.h (class sve_switcher): Delete. (class sme_switcher): Delete. (class sve_alignment_switcher): New. * config/aarch64/t-aarch64 (aarch64-builtins.o): Add $(REGS_H). (aarch64-sve-builtins.o): Remove $(REG_H).
2025-03-01[PR target/118906] [PATCH v2] RISC-V: Fix a typo in zce to zcf implicationYuriy Kolerov1-1/+1
zce must imply zcf but this rule was corrupted after refactoring in 9e12010b5e724277ea. This may be observed ater generating an .s file from any source code file with -mriscv-attribute -march=rv32if_zce -mabi=ilp32 -S options. A full march will be presented in arch attribute: rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0 As you see, zcf is not presented here though f_zce pair is passed in -march. According to The RISC-V Instruction Set Manual: Specifying Zce on RV32 with F includes Zca, Zcb, Zcmp, Zcmt and Zcf. PR target/118906 gcc/ChangeLog: * common/config/riscv/riscv-common.cc: fix zce to zcf implication. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-zce-1.c: New test. * gcc.target/riscv/attribute-zce-2.c: New test. * gcc.target/riscv/attribute-zce-3.c: New test. * gcc.target/riscv/attribute-zce-4.c: New test.
2025-02-17i386: Re-alias avx10.2 to 512 bit and deprecate -mno-avx10.2-[256,512]Haochen Jiang2-14/+9
As mentioned in avx10.1 option deprecate patch, based on the feedback we got, we would like to re-alias avx10.x to 512 bit. For -mno- options, also mentioned in the previous patch, it is confusing what it is disabling when it comes to avx10. So we will only provide -mno-avx10.x options from AVX10.2, disabling the whole AVX10.x. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_UNSET): Adjust macro. (OPTION_MASK_ISA2_AVX10_2_256_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_2_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_2_UNSET): New. (ix86_handle_option): Remove disable part for avx10.2-256. Rename avx10.2-512 switch case to avx10.2 and adjust disable part macro. * common/config/i386/i386-isas.h: Adjust avx10.2 and avx10.2-512. * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10.x-256 for -march=native. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Adjust avx10.2 and avx10.2-512. * config/i386/i386.opt: Reject Negative for mavx10.2-256. Alias mavx10.2-512 to mavx10.2. Reject Negative for mavx10.2-512. * doc/extend.texi: Adjust documentation. * doc/sourcebuild.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_2-512-vminmaxbf16-2.c: Add missing avx10_2_512 check. * gcc.target/i386/avx10_2-512-vminmaxpd-2.c: Ditto. * gcc.target/i386/avx10_2-512-vminmaxph-2.c: Ditto. * gcc.target/i386/avx10_2-512-vminmaxps-2.c: Ditto. * gcc.target/i386/avx10-check.h: Change avx10.2 to avx10.2-256. * gcc.target/i386/avx10_2-bf16-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-cmp-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-fma-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-operations-1.c: Ditto. * gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c: Ditto. * gcc.target/i386/avx10_2-builtin-1.c: Ditto. * gcc.target/i386/avx10_2-builtin-2.c: Ditto. * gcc.target/i386/avx10_2-comibf-1.c: Ditto. * gcc.target/i386/avx10_2-comibf-2.c: Ditto. * gcc.target/i386/avx10_2-comibf-3.c: Ditto. * gcc.target/i386/avx10_2-comibf-4.c: Ditto. * gcc.target/i386/avx10_2-compare-1.c: Ditto. * gcc.target/i386/avx10_2-compare-1b.c: Ditto. * gcc.target/i386/avx10_2-convert-1.c: Ditto. * gcc.target/i386/avx10_2-media-1.c: Ditto. * gcc.target/i386/avx10_2-minmax-1.c: Ditto. * gcc.target/i386/avx10_2-movrs-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-fast-math-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-fma-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-operations-1.c: Ditto. * gcc.target/i386/avx10_2-partial-bf16-vector-smaxmin-1.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Ditto. * gcc.target/i386/avx10_2-rounding-2.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: Ditto. * gcc.target/i386/avx10_2-satcvt-1.c: Ditto. * gcc.target/i386/avx10_2-vaddbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcmpbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcomisbf16-1.c: Ditto. * gcc.target/i386/avx10_2-vcomisbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvt2ps2phx-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbf162ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbf162iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtbiasph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvthf82ph-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2bf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2bf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2hf8-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2hf8s-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtph2iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvtps2ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttbf162ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttbf162iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttpd2dqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttpd2qqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttpd2udqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttph2ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttph2iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2dqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2ibs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2iubs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2qqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2udqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttps2uqqs-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttsd2sis-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttsd2usis-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttss2sis-2.c: Ditto. * gcc.target/i386/avx10_2-vcvttss2usis-2.c: Ditto. * gcc.target/i386/avx10_2-vdivbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vdpphps-2.c: Ditto. * gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vfpclassbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vgetexpbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vgetmantbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vmaxbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vminbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxpd-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxph-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxps-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxsd-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxsh-2.c: Ditto. * gcc.target/i386/avx10_2-vminmaxss-2.c: Ditto. * gcc.target/i386/avx10_2-vmovd-1.c: Ditto. * gcc.target/i386/avx10_2-vmovd-2.c: Ditto. * gcc.target/i386/avx10_2-vmovw-1.c: Ditto. * gcc.target/i386/avx10_2-vmovw-2.c: Ditto. * gcc.target/i386/avx10_2-vmpsadbw-2.c: Ditto. * gcc.target/i386/avx10_2-vmulbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbssd-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbssds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbsud-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbsuds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbuud-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpbuuds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwsud-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwsuds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwusd-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwusds-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwuud-2.c: Ditto. * gcc.target/i386/avx10_2-vpdpwuuds-2.c: Ditto. * gcc.target/i386/avx10_2-vrcpbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vreducebf16-2.c: Ditto. * gcc.target/i386/avx10_2-vrndscalebf16-2.c: Ditto. * gcc.target/i386/avx10_2-vrsqrtbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vscalefbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vsqrtbf16-2.c: Ditto. * gcc.target/i386/avx10_2-vsubbf16-2.c: Ditto. * gcc.target/i386/funcspec-56.inc: Ditto. * gcc.target/i386/part-vect-vec_cmpbf.c: Ditto. * gcc.target/i386/pr117495.c: Ditto. * gcc.target/i386/sm4-avx10_2-1.c: Ditto. * gcc.target/i386/sm4-check.h: Ditto. * gcc.target/i386/vnniint16-auto-vectorize-3.c: Ditto. * gcc.target/i386/vnniint8-auto-vectorize-3.c: Ditto. * lib/target-supports.exp: Ditto.
2025-02-17i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the ↵Haochen Jiang2-11/+8
whole AVX10.1 Based on the feedback we got, we would like to re-alias avx10.x to 512 bit in the future. This leaves the current avx10.1 alias to 256 bit inconsistent. Since it has been there for GCC 14.1 and GCC 14.2, we decide to deprecate avx10.1 alias. The current proposal is not adding it back in the future, but it might change if necessary. For -mno- options, it is confusing what it is disabling when it comes to avx10. Since there is barely usage enabling AVX10 with 512 bit then disabling it, we will only provide -mno-avx10.x options in the future, disabling the whole AVX10.x. If someone really wants to disable 512 bit after enabling it, -mavx10.x-512 -mno-avx10.x -mavx10.x-256 is the only way to do that since we also do not want to break the usual expression on -m- options enabling everything mentioned. However, for avx10.1, since we deprecated avx10.1, there is no reason we should have -mno-avx10.1. Thus, we need to keep -mno-avx10.1-[256,512]. To avoid confusion, we will make -mno-avx10.1-512 to disable the whole AVX10.1 set to match the future -mno-avx10.x. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX2_UNSET): Change AVX10.1 unset macro. (OPTION_MASK_ISA2_AVX10_1_256_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_UNSET): New. (ix86_handle_option): Adjust AVX10.1 unset macro. * common/config/i386/i386-isas.h: Remove avx10.1. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Ditto. (ix86_option_override_internal): Adjust warning message. * config/i386/i386.opt: Remove mavx10.1. * doc/extend.texi: Remove avx10.1 and adjust doc. * doc/sourcebuild.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10-check.h: Change to avx10.1-256. * gcc.target/i386/avx10_1-1.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-24.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/pr117946.c: Ditto. * gcc.target/i386/avx10_1-12.c: Adjust warning message. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-17.c: Adjust to no-avx10.1-512.
2025-02-14GCN: Set 'UI_TARGET' for 'TARGET_EXCEPT_UNWIND_INFO' [PR94282, PR113331]Thomas Schwinge1-1/+1
In commit 7f1989249e25af6fc0f124452efa24b3796b767a "[gcn] Set 'UI_NONE' for 'TARGET_EXCEPT_UNWIND_INFO' [PR94282]", we've copied the 'UI_NONE' idea from nvptx to GCN. I understand the intention of using 'UI_NONE' like this, and it happens to work in a lot of cases, but there are ICEs elsewhere: code paths where we run into 'internal compiler error: in get_personality_function, at expr.cc:13512': 13494 /* Extracts the personality function of DECL and returns the corresponding 13495 libfunc. */ 13496 13497 rtx 13498 get_personality_function (tree decl) 13499 { 13500 tree personality = DECL_FUNCTION_PERSONALITY (decl); 13501 enum eh_personality_kind pk; 13502 13503 pk = function_needs_eh_personality (DECL_STRUCT_FUNCTION (decl)); 13504 if (pk == eh_personality_none) 13505 return NULL; 13506 13507 if (!personality 13508 && pk == eh_personality_any) 13509 personality = lang_hooks.eh_personality (); 13510 13511 if (pk == eh_personality_lang) 13512 gcc_assert (personality != NULL_TREE); 13513 13514 return XEXP (DECL_RTL (personality), 0); 13515 } ..., where 'lang_hooks.eh_personality ()' ends up calling 'gcc/expr.cc:build_personality_function', and we 'return NULL;' for 'UI_NONE': 13448 /* Build a decl for a personality function given a language prefix. */ 13449 13450 tree 13451 build_personality_function (const char *lang) 13452 { 13453 const char *unwind_and_version; 13454 tree decl, type; 13455 char *name; 13456 13457 switch (targetm_common.except_unwind_info (&global_options)) 13458 { 13459 case UI_NONE: 13460 return NULL; [...] (Comparing to nvptx' current use of 'UI_NONE', this problem (ICEs mentioned above) is way more prevalent for GCN.) The GCC internals documentation indeed states, 'gcc/doc/tm.texi': @deftypefn {Common Target Hook} {enum unwind_info_type} TARGET_EXCEPT_UNWIND_INFO (struct gcc_options *@var{opts}) This hook defines the mechanism that will be used for exception handling by the target. If the target has ABI specified unwind tables, the hook should return @code{UI_TARGET}. If the target is to use the @code{setjmp}/@code{longjmp}-based exception handling scheme, the hook should return @code{UI_SJLJ}. If the target supports DWARF 2 frame unwind information, the hook should return @code{UI_DWARF2}. A target may, if exceptions are disabled, choose to return @code{UI_NONE}. This may end up simplifying other parts of target-specific code. [...] Here, note: "if exceptions are disabled" (meaning: '-fno-exceptions' etc.) may "return @code{UI_NONE}". That's what other back ends do with code like: /* For simplicity elsewhere in this file, indicate that all unwind info is disabled if we're not emitting unwind tables. */ if (!opts->x_flag_exceptions && !opts->x_flag_unwind_tables) return UI_NONE; else return UI_TARGET; The corresponding "simplifying other parts of target-specific code"/ "simplicity elsewhere" would then be the early returns from 'TARGET_ASM_UNWIND_EMIT', 'ARM_OUTPUT_FN_UNWIND', etc. for 'TARGET_EXCEPT_UNWIND_INFO != UI_TARGET' (that is, for 'UI_NONE'). From the documentation (and implementation), however, it does *not* follow that if a target doesn't implement support for exception handling, it may just set 'UI_NONE' for 'TARGET_EXCEPT_UNWIND_INFO'. Therefore, switch to 'UI_TARGET', allocating a "fake" 'exception_section'. With that, all these 'internal compiler error: in get_personality_function' test cases turn into PASS, or UNSUPPORTED ('exception handling not supported'), or re-classify into a few other, already known issues. And, this change also happens to resolve the class of errors identified in GCC PR113331 "AMDGCN: Compilation failure due to duplicate .LEHB<n>/.LEHE<n> symbols". (In case that use of 'UI_NONE' like originally intended really makes sense, and is preferable over this 'UI_TARGET' solution, then more work will be necessary for implementing the missing parts, where 'UI_NONE' currently isn't handled.) PR target/94282 PR target/113331 gcc/ * common/config/gcn/gcn-common.cc (gcn_except_unwind_info): 'return UI_TARGET;'. * config/gcn/gcn.cc (gcn_asm_init_sections): New function. (TARGET_ASM_INIT_SECTIONS): '#define'.
2025-02-14nvptx: Set 'UI_TARGET' for 'TARGET_EXCEPT_UNWIND_INFO' [PR86660]Thomas Schwinge1-1/+1
Subversion r263265 (Git commit 77e0a97acf7b00c1e68e4738fdf275a4cffc2e50) "[nvptx] Ignore c++ exceptions", originally had set 'UI_TARGET', but as part of Subversion r263287 (Git commit d989dba8ef02c2406b7c9e62b352197dffc6b880) "[c++] Don't emit exception tables for UI_NONE", then switched to 'UI_NONE'. I understand the intention of using 'UI_NONE' like this, and it happens to work in a lot of cases, but there are ICEs elsewhere: code paths where we run into 'internal compiler error: in get_personality_function, at expr.cc:13512': 13494 /* Extracts the personality function of DECL and returns the corresponding 13495 libfunc. */ 13496 13497 rtx 13498 get_personality_function (tree decl) 13499 { 13500 tree personality = DECL_FUNCTION_PERSONALITY (decl); 13501 enum eh_personality_kind pk; 13502 13503 pk = function_needs_eh_personality (DECL_STRUCT_FUNCTION (decl)); 13504 if (pk == eh_personality_none) 13505 return NULL; 13506 13507 if (!personality 13508 && pk == eh_personality_any) 13509 personality = lang_hooks.eh_personality (); 13510 13511 if (pk == eh_personality_lang) 13512 gcc_assert (personality != NULL_TREE); 13513 13514 return XEXP (DECL_RTL (personality), 0); 13515 } ..., where 'lang_hooks.eh_personality ()' ends up calling 'gcc/expr.cc:build_personality_function', and we 'return NULL;' for 'UI_NONE': 13448 /* Build a decl for a personality function given a language prefix. */ 13449 13450 tree 13451 build_personality_function (const char *lang) 13452 { 13453 const char *unwind_and_version; 13454 tree decl, type; 13455 char *name; 13456 13457 switch (targetm_common.except_unwind_info (&global_options)) 13458 { 13459 case UI_NONE: 13460 return NULL; [...] (Comparing to nvptx' current use of 'UI_NONE', this problem (ICEs mentioned above) is way more prevalent for GCN.) The GCC internals documentation indeed states, 'gcc/doc/tm.texi': @deftypefn {Common Target Hook} {enum unwind_info_type} TARGET_EXCEPT_UNWIND_INFO (struct gcc_options *@var{opts}) This hook defines the mechanism that will be used for exception handling by the target. If the target has ABI specified unwind tables, the hook should return @code{UI_TARGET}. If the target is to use the @code{setjmp}/@code{longjmp}-based exception handling scheme, the hook should return @code{UI_SJLJ}. If the target supports DWARF 2 frame unwind information, the hook should return @code{UI_DWARF2}. A target may, if exceptions are disabled, choose to return @code{UI_NONE}. This may end up simplifying other parts of target-specific code. [...] Here, note: "if exceptions are disabled" (meaning: '-fno-exceptions' etc.) may "return @code{UI_NONE}". That's what other back ends do with code like: /* For simplicity elsewhere in this file, indicate that all unwind info is disabled if we're not emitting unwind tables. */ if (!opts->x_flag_exceptions && !opts->x_flag_unwind_tables) return UI_NONE; else return UI_TARGET; The corresponding "simplifying other parts of target-specific code"/ "simplicity elsewhere" would then be the early returns from 'TARGET_ASM_UNWIND_EMIT', 'ARM_OUTPUT_FN_UNWIND', etc. for 'TARGET_EXCEPT_UNWIND_INFO != UI_TARGET' (that is, for 'UI_NONE'). From the documentation (and implementation), however, it does *not* follow that if a target doesn't implement support for exception handling, it may just set 'UI_NONE' for 'TARGET_EXCEPT_UNWIND_INFO'. Therefore, switch (back) to 'UI_TARGET', implementing some basic support for 'exception_section': discard (via a PTX comment block) whatever GCC writes into it. With that, all these 'internal compiler error: in get_personality_function' test cases turn into PASS, or UNSUPPORTED ('exception handling not supported'), or re-classify into a few other, already known issues. (In case that use of 'UI_NONE' like originally intended really makes sense, and is preferable over this 'UI_TARGET' solution, then more work will be necessary for implementing the missing parts, where 'UI_NONE' currently isn't handled.) PR target/86660 gcc/ * common/config/nvptx/nvptx-common.cc (nvptx_except_unwind_info): 'return UI_TARGET;'. * config/nvptx/nvptx.cc (nvptx_assemble_integer): Handle 'exception_section'. (nvptx_output_section_asm_op, nvptx_asm_init_sections): New functions. (TARGET_ASM_INIT_SECTIONS): '#define'. * config/nvptx/nvptx.h (TEXT_SECTION_ASM_OP, DATA_SECTION_ASM_OP): Don't '#define'. (ASM_OUTPUT_DWARF_DELTA): '#define'.
2025-01-24aarch64: Make AARCH64_FL_CRYPTO always unsetAndrew Carlotti1-0/+4
This feature flag bit only exists to support the +crypto alias. Outside of option processing this bit needs to be set or unset consistently. This patch goes with the latter option. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc: Assert that CRYPTO bit is not set. * config/aarch64/aarch64-feature-deps.h (info<FEAT>.explicit_on): Unset CRYPTO bit. (cpu_##CORE_IDENT): Ditto. gcc/testsuite/ChangeLog: * gcc.target/aarch64/crypto-alias-1.c: New test.
2025-01-24aarch64: Refactor aarch64_rewrite_mcpuAndrew Carlotti1-61/+17
Use aarch64_validate_cpu instead of the existing duplicate (and worse) version of the -mcpu parsing code. The original code used fatal_error; I'm guessing that using error instead should be ok. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_rewrite_selected_cpu): Refactor and inline into... (aarch64_rewrite_mcpu): this. * config/aarch64/aarch64-protos.h (aarch64_rewrite_selected_cpu): Delete.
2025-01-24aarch64: Rewrite architecture strings for assemblerAndrew Carlotti1-4/+45
Add infrastructure to allow rewriting the architecture strings passed to the assembler (either as -march options or .arch directives). There was already canonicalisation everywhere except for an -march driver option passed directly to the compiler; this patch applies the same canonicalisation there as well. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_get_arch_string_for_assembler): New. (aarch64_rewrite_march): New. (aarch64_rewrite_selected_cpu): Call new function. * config/aarch64/aarch64-elf.h (ASM_SPEC): Remove identity mapping. * config/aarch64/aarch64-protos.h (aarch64_get_arch_string_for_assembler): New. * config/aarch64/aarch64.cc (aarch64_declare_function_name): Call new function. (aarch64_start_file): Ditto. * config/aarch64/aarch64.h (EXTRA_SPEC_FUNCTIONS): Use new macro name. (MCPU_TO_MARCH_SPEC): Rename to... (MARCH_REWRITE_SPEC): ...this, and extend the spec rule. (aarch64_rewrite_march): New declaration. (MCPU_TO_MARCH_SPEC_FUNCTIONS): Rename to... (AARCH64_BASE_SPEC_FUNCTIONS): ...this, and add new function. (ASM_CPU_SPEC): Use new macro name.
2025-01-24aarch64: Inline aarch64_get_all_extension_candidatesAndrew Carlotti1-11/+4
gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_get_all_extension_candidates): Inline into... (aarch64_print_hint_for_extensions): ...this.
2025-01-24aarch64: Move arch/cpu parsing to aarch64-common.ccAndrew Carlotti1-6/+328
Aside from moving the functions, the only changes are to make them non-static, and to use the existing info arrays within aarch64-common.cc instead of the info arrays remaining in aarch64.cc. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_get_all_extension_candidates): Move within file. (aarch64_print_hint_candidates): Move from aarch64.cc. (aarch64_print_hint_for_extensions): Ditto. (aarch64_print_hint_for_arch): Ditto. (aarch64_print_hint_for_core): Ditto. (enum aarch_parse_opt_result): Ditto. (aarch64_parse_arch): Ditto. (aarch64_parse_cpu): Ditto. (aarch64_parse_tune): Ditto. (aarch64_validate_march): Ditto. (aarch64_validate_mcpu): Ditto. (aarch64_validate_mtune): Ditto. * config/aarch64/aarch64-protos.h (aarch64_rewrite_selected_cpu): Move within file. (aarch64_print_hint_for_extensions): Share function prototype. (aarch64_print_hint_for_arch): Ditto. (aarch64_print_hint_for_core): Ditto. (enum aarch_parse_opt_result): Ditto. (aarch64_validate_march): Ditto. (aarch64_validate_mcpu): Ditto. (aarch64_validate_mtune): Ditto. (aarch64_get_all_extension_candidates): Unshare prototype. * config/aarch64/aarch64.cc (aarch64_parse_arch): Move to aarch64-common.cc. (aarch64_parse_cpu): Ditto. (aarch64_parse_tune): Ditto. (aarch64_print_hint_candidates): Ditto. (aarch64_print_hint_for_core): Ditto. (aarch64_print_hint_for_arch): Ditto. (aarch64_print_hint_for_extensions): Ditto. (aarch64_validate_mcpu): Ditto. (aarch64_validate_march): Ditto. (aarch64_validate_mtune): Ditto.
2025-01-24aarch64: Rename info structs in aarch64-common.ccAndrew Carlotti1-23/+27
Also add a (currently unused) processor field to aarch64_processor_info, and change name from "" to NULL for the terminating array entries. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (struct aarch64_option_extension): Rename to.. (struct aarch64_extension_info): ...this. (all_extensions): Update type name. (struct arch_to_arch_name): Rename to... (struct aarch64_arch_info): ...this, and rename name field. (all_architectures): Update type names, and move before... (struct processor_name_to_arch): ...this. Rename to... (struct aarch64_processor_info): ...this, rename name field and add cpu field. (all_cores): Update type name, and set new field. (aarch64_parse_extension): Update names. (aarch64_get_all_extension_candidates): Ditto. (aarch64_rewrite_selected_cpu): Ditto.
2025-01-24aarch64: Remove redundant generic cpu entryAndrew Carlotti1-1/+0
The list of cores in aarch64-common.cc included an explicit "generic" entry, despite this entry also being present in aarch64-cores.def. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (all_cores): Remove explicit generic entry.
2025-01-20s390: arch15: Prepare for a future architectureStefan Schulze Frielinghaus1-1/+5
gcc/ChangeLog: * common/config/s390/s390-common.cc: Add arch15 processor flags. * config.gcc: Add arch15 for options --with-{arch,mtune}. * config/s390/driver-native.cc (s390_host_detect_local_cpu): Default to arch15. * config/s390/s390-opts.h (enum processor_type): Add PROCESSOR_ARCH15. * config/s390/s390.cc (processor_table,s390_issue_rate, s390_get_sched_attrmask,s390_get_unit_mask): Add arch15. * config/s390/s390.h (enum processor_flags): Add processor flags for VXE3 and ARCH15. (TARGET_CPU_VXE3): Define. (TARGET_CPU_VXE3_P): Define. (TARGET_CPU_ARCH15): Define. (TARGET_CPU_ARCH15_P): Define. (TARGET_VXE3): Define. (TARGET_VXE3_P): Define. (TARGET_ARCH15): Define. (TARGET_ARCH15_P): Define. * config/s390/s390.md: Add VXE3 and ARCH15 to cpu_facility, and let attribute "enabled" deal with them. * config/s390/s390.opt: Add arch15. gcc/testsuite/ChangeLog: * gcc.target/s390/s390.exp: Set compiler flags for the vxe3 subdirectory of the testsuite as done e.g. for vxe2.
2025-01-17RISC-V: Add Zicfilp ISA extension.Monk Chiang1-0/+3
This patch only support landing pad value is 0. The next version will implement function signature based labeling scheme. RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add ZICFILP ISA string. * config.gcc: Add riscv-zicfilp.o * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Insert landing pad instructions. * config/riscv/riscv-protos.h (make_pass_insert_landing_pad): Declare. * config/riscv/riscv-zicfilp.cc: New file. * config/riscv/riscv.cc (riscv_trampoline_init): Add landing pad instructions. (riscv_legitimize_call_address): Likewise. (riscv_output_mi_thunk): Likewise. * config/riscv/riscv.h: Update. * config/riscv/riscv.md: Add landing pad patterns. * config/riscv/riscv.opt (TARGET_ZICFILP): Define. * config/riscv/t-riscv: Add build rule for riscv-zicfilp.o gcc/testsuite/ChangeLog: * gcc.target/riscv/interrupt-no-lpad.c: New test. * gcc.target/riscv/zicfilp-call.c: New test. Co-Developed-by: Greg McGary <gkm@rivosinc.com>, Kito Cheng <kito.cheng@gmail.com>
2025-01-17RISC-V: Add Zicfiss ISA extension.Monk Chiang1-0/+7
This patch is implemented according to the RISC-V CFI specification. It supports the generation of shadow stack instructions in the prologue, epilogue, non-local gotos, and unwinding. RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add ZICFISS ISA string. * config/riscv/predicates.md: New predicate x1x5_operand. * config/riscv/riscv.cc (riscv_expand_prologue): Insert shadow stack instructions. (riscv_expand_epilogue): Likewise. (riscv_for_each_saved_reg): Assign t0 or ra register for sspopchk instruction. (need_shadow_stack_push_pop_p): New function. Omit shadow stack operation on leaf function. * config/riscv/riscv.h (need_shadow_stack_push_pop_p): Define. * config/riscv/riscv.md: Add shadow stack patterns. (save_stack_nonlocal): Add shadow stack instructions for setjump. (restore_stack_nonlocal): Add shadow stack instructions for longjump. * config/riscv/riscv.opt (TARGET_ZICFISS): Define. libgcc/ChangeLog: * config/riscv/linux-unwind.h: Include shadow-stack-unwind.h. * config/riscv/shadow-stack-unwind.h (_Unwind_Frames_Extra): Define. (_Unwind_Frames_Increment): Define. gcc/testsuite/ChangeLog: * gcc.target/riscv/ssp-1.c: New test. * gcc.target/riscv/ssp-2.c: New test. Co-Developed-by: Greg McGary <gkm@rivosinc.com>, Kito Cheng <kito.cheng@gmail.com>
2025-01-09i386: Remove not used model number for Diamond RapidsHaochen Jiang1-1/+0
In ISE, The model number for Diamond Rapids is 13_01H. Remove 0x00 since it is unused. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Remove 0x00.
2025-01-07AArch64: Switch off early schedulingWilco Dijkstra1-0/+2
The early scheduler takes up ~33% of the total build time, however it doesn't provide a meaningful performance gain. This is partly because modern OoO cores need far less scheduling, partly because the scheduler tends to create many unnecessary spills by increasing register pressure. Building applications 56% faster is far more useful than ~0.1% improvement on SPEC, so switch off early scheduling on AArch64. Codesize reduces by ~0.2%. Fix various tests that depend on scheduling by explicitly adding -fschedule-insns. gcc: * common/config/aarch64/aarch64-common.cc: Switch off fschedule_insns. gcc/testsuite: * gcc.dg/guality/pr36728-3.c: Remove XFAIL. * gcc.dg/guality/pr68860-1.c: Likewise. * gcc.dg/guality/pr68860-2.c: Likewise. * gcc.target/aarch64/ldp_aligned.c: Fix test. * gcc.target/aarch64/ldp_always.c: Likewise. * gcc.target/aarch64/ldp_stp_10.c: Add -fschedule-insns. * gcc.target/aarch64/ldp_stp_12.c: Likewise. * gcc.target/aarch64/ldp_stp_13.c: Remove test. * gcc.target/aarch64/ldp_stp_21.c: Add -fschedule-insns. * gcc.target/aarch64/ldp_stp_8.c: Likewise. * gcc.target/aarch64/ldp_vec_v2sf.c: Likewise. * gcc.target/aarch64/ldp_vec_v2si.c: Likewise. * gcc.target/aarch64/test_frame_16.c: Fix test. * gcc.target/aarch64/sve/vcond_12.c: Add -fschedule-insns. * gcc.target/aarch64/sve/acle/general/ldff1_3.c: Likewise.
2025-01-02Update copyright years.Jakub Jelinek51-51/+51
2024-12-20RISC-V: List valid -mtune options only onceChristoph Müllner1-1/+13
This patch ensures that the list of valid -mtune options does not contain entries more than once. The -mtune option accepts CPU identifiers as well as tuning identifiers and there are cases where a CPU and its tuning have the same identifier. PR116347 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_get_valid_option_values): Skip adding mtune entries that are already in the list. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-12-17RISC-V: Remove svvptc from riscv-ext-bitmask.defYangyu Chen1-1/+0
There should be no svvptc in the riscv-ext-bitmask.def file since it has not yet been added to the RISC-V C API Specification or the Linux hwprobe. And there is no need for userspace software to know that this extension exists. So remove it from the riscv-ext-bitmask.def file. Fixes: e4f4b2dc08 ("RISC-V: Minimal support for svvptc extension.") Signed-off-by: Yangyu Chen <cyy@cyyself.name> gcc/ChangeLog: * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Remove svvptc.
2024-12-06AVR: Disable generation of CRC lookup tables.Georg-Johann Lay1-0/+2
With -foptimize-crc, large lookup tables may be generated which are places in .rodata (RAM). This patch disables such tables. gcc/ * common/config/avr/avr-common.cc (avr_option_optimization_table): Default to -fno-optimize-crc.
2024-12-05AVR: target/107957 - Split multi-byte loads and stores.Georg-Johann Lay1-0/+1
This patch splits multi-byte loads and stores into single-byte ones provided: - New option -msplit-ldst is on (e.g. -O2 and higher), and - The memory is non-volatile, and - The address space is generic, and - The split addresses are natively supported by the hardware. gcc/ PR target/107957 * config/avr/avr.opt (-msplit-ldst, avropt_split_ldst): New option and associated var. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_2_PLUS]: Turn on -msplit_ldst. * config/avr/avr-passes.cc (splittable_address_p) (avr_byte_maybe_mem, avr_split_ldst): New functions. * config/avr/avr-protos.h (avr_split_ldst): New proto. * config/avr/avr.md (define_split) [avropt_split_ldst]: Run avr_split_ldst().
2024-11-29AArch64: Suppress default options when march or mcpu used is not affected by it.Tamar Christina1-0/+27
This patch makes it so that when you use any of the Cortex-A53 errata workarounds but have specified an -march or -mcpu we know is not affected by it that we suppress the errata workaround. This is a driver only patch as the linker invocation needs to be changed as well. The linker and cc SPECs are different because for the linker we didn't seem to add an inversion flag for the option. That said, it's also not possible to configure the linker with it on by default. So not passing the flag is sufficient to turn it off. For the compilers however we have an inversion flag using -mno-, which is needed to disable the workarounds when the compiler has been configured with it by default. In case it's unclear how the patch does what it does (it took me a while to figure out the syntax): * Early matching will replace any -march=native or -mcpu=native with their expanded forms and erases the native arguments from the buffer. * Due to the above if we ensure we handle the new code after this erasure then we only have to handle the expanded form. * The expanded form needs to handle -march=<arch>+extensions and -mcpu=<cpu>+extensions and so we can't use normal string matching but instead use strstr with a custom driver function that's common between native and non-native builds. * For the compilers we output -mno-<workaround> and for the linker we just erase the --fix-<workaround> option. * The extra internal matching, e.g. the duplicate match of mcpu inside: mcpu=*:%{%:is_local_not_armv8_base(%{mcpu=*:%*}) is so we can extract the glob using %* because the outer match would otherwise reset at the %{. The reason for the outer glob at all is to skip the block early if no matches are found. The workaround has the effect of suppressing certain inlining and multiply-add formation which leads to about ~1% SPECCPU 2017 Intrate regression on modern cores. This patch is needed because most distros configure GCC with the workaround enabled by default. Expected output: > gcc -mcpu=neoverse-v1 -mfix-cortex-a53-835769 -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-mfix" | wc -l 0 > gcc -mfix-cortex-a53-835769 -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-mfix" | wc -l 5 > gcc -mfix-cortex-a53-835769 -march=armv8-a -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-mfix" | wc -l 5 > gcc -mfix-cortex-a53-835769 -march=armv8.1-a -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-mfix" | wc -l 0 > gcc -mfix-cortex-a53-835769 -march=armv8.1-a -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-\-fix" | wc -l 0 > gcc -mfix-cortex-a53-835769 -march=armv8-a -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-\-fix" | wc -l 1 > -gcc -mfix-cortex-a53-835769 -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-\-fix" | wc -l 1 gcc/ChangeLog: * config/aarch64/aarch64-errata.h (TARGET_SUPPRESS_OPT_SPEC, TARGET_TURN_OFF_OPT_SPEC, CA53_ERR_835769_COMPILE_SPEC, CA53_ERR_843419_COMPILE_SPEC): New. (CA53_ERR_835769_SPEC, CA53_ERR_843419_SPEC): Use them. * config/aarch64/aarch64-elf-raw.h (CC1_SPEC, CC1PLUS_SPEC): Add AARCH64_ERRATA_COMPILE_SPEC. * config/aarch64/aarch64-freebsd.h (CC1_SPEC, CC1PLUS_SPEC): Likewise. * config/aarch64/aarch64-gnu.h (CC1_SPEC, CC1PLUS_SPEC): Likewise. * config/aarch64/aarch64-linux.h (CC1_SPEC, CC1PLUS_SPEC): Likewise. * config/aarch64/aarch64-netbsd.h (CC1_SPEC, CC1PLUS_SPEC): Likewise. * common/config/aarch64/aarch64-common.cc (is_host_cpu_not_armv8_base): New. * config/aarch64/driver-aarch64.cc: Remove extra newline * config/aarch64/aarch64.h (is_host_cpu_not_armv8_base): New. (MCPU_TO_MARCH_SPEC_FUNCTIONS): Add is_local_not_armv8_base. (EXTRA_SPEC_FUNCTIONS): Add is_local_cpu_armv8_base. * doc/invoke.texi: Document it. gcc/testsuite/ChangeLog: * gcc.target/aarch64/cpunative/info_30: New test. * gcc.target/aarch64/cpunative/info_31: New test. * gcc.target/aarch64/cpunative/info_32: New test. * gcc.target/aarch64/cpunative/info_33: New test. * gcc.target/aarch64/cpunative/native_cpu_30.c: New test. * gcc.target/aarch64/cpunative/native_cpu_31.c: New test. * gcc.target/aarch64/cpunative/native_cpu_32.c: New test. * gcc.target/aarch64/cpunative/native_cpu_33.c: New test. * gcc.target/aarch64/erratas_opt_0.c: New test. * gcc.target/aarch64/erratas_opt_1.c: New test. * gcc.target/aarch64/erratas_opt_10.c: New test. * gcc.target/aarch64/erratas_opt_11.c: New test. * gcc.target/aarch64/erratas_opt_12.c: New test. * gcc.target/aarch64/erratas_opt_13.c: New test. * gcc.target/aarch64/erratas_opt_14.c: New test. * gcc.target/aarch64/erratas_opt_15.c: New test. * gcc.target/aarch64/erratas_opt_2.c: New test. * gcc.target/aarch64/erratas_opt_3.c: New test. * gcc.target/aarch64/erratas_opt_4.c: New test. * gcc.target/aarch64/erratas_opt_5.c: New test. * gcc.target/aarch64/erratas_opt_6.c: New test. * gcc.target/aarch64/erratas_opt_7.c: New test. * gcc.target/aarch64/erratas_opt_8.c: New test. * gcc.target/aarch64/erratas_opt_9.c: New test.
2024-11-27diagnostics: replace %<%s%> with %qs [PR104896]David Malcolm2-2/+2
No functional change intended. gcc/analyzer/ChangeLog: PR c/104896 * sm-malloc.cc: Replace "%<%s%>" with "%qs" in message wording. gcc/c-family/ChangeLog: PR c/104896 * c-lex.cc (c_common_lex_availability_macro): Replace "%<%s%>" with "%qs" in message wording. * c-opts.cc (c_common_handle_option): Likewise. * c-warn.cc (warn_parm_array_mismatch): Likewise. gcc/ChangeLog: PR c/104896 * common/config/ia64/ia64-common.cc (ia64_handle_option): Replace "%<%s%>" with "%qs" in message wording. * common/config/rs6000/rs6000-common.cc (rs6000_handle_option): Likewise. * config/aarch64/aarch64.cc (aarch64_validate_sls_mitigation): Likewise. (aarch64_override_options): Likewise. (aarch64_process_target_attr): Likewise. * config/arm/aarch-common.cc (aarch_validate_mbranch_protection): Likewise. * config/pru/pru.cc (pru_insert_attributes): Likewise. * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Likewise. * omp-general.cc (oacc_verify_routine_clauses): Likewise. * tree-ssa-uninit.cc (maybe_warn_read_write_only): Likewise. (maybe_warn_pass_by_reference): Likewise. gcc/cp/ChangeLog: PR c/104896 * cvt.cc (maybe_warn_nodiscard): Replace "%<%s%>" with "%qs" in message wording. gcc/fortran/ChangeLog: PR c/104896 * resolve.cc (resolve_operator): Replace "%<%s%>" with "%qs" in message wording. gcc/go/ChangeLog: PR c/104896 * gofrontend/embed.cc (Gogo::initializer_for_embeds): Replace "%<%s%>" with "%qs" in message wording. * gofrontend/expressions.cc (Selector_expression::lower_method_expression): Likewise. * gofrontend/gogo.cc (Gogo::set_package_name): Likewise. (Named_object::export_named_object): Likewise. * gofrontend/parse.cc (Parse::struct_type): Likewise. (Parse::parameter_list): Likewise. gcc/rust/ChangeLog: PR c/104896 * backend/rust-compile-expr.cc (CompileExpr::compile_integer_literal): Replace "%<%s%>" with "%qs" in message wording. (CompileExpr::compile_float_literal): Likewise. * backend/rust-compile-intrinsic.cc (Intrinsics::compile): Likewise. * backend/rust-tree.cc (maybe_warn_nodiscard): Likewise. * checks/lints/rust-lint-scan-deadcode.h: Likewise. * lex/rust-lex.cc (Lexer::parse_partial_unicode_escape): Likewise. (Lexer::parse_raw_byte_string): Likewise. * lex/rust-token.cc (Token::get_str): Likewise. * metadata/rust-export-metadata.cc (PublicInterface::write_to_path): Likewise. * parse/rust-parse.cc (peculiar_fragment_match_compatible_fragment): Likewise. (peculiar_fragment_match_compatible): Likewise. * resolve/rust-ast-resolve-path.cc (ResolvePath::resolve_path): Likewise. * resolve/rust-ast-resolve-toplevel.h: Likewise. * resolve/rust-ast-resolve-type.cc (ResolveRelativeTypePath::go): Likewise. * rust-session-manager.cc (validate_crate_name): Likewise. (Session::load_extern_crate): Likewise. * typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): Likewise. (TypeCheckExpr::resolve_fn_trait_call): Likewise. * typecheck/rust-hir-type-check-implitem.cc (TypeCheckImplItemWithTrait::visit): Likewise. * typecheck/rust-hir-type-check-item.cc (TypeCheckItem::validate_trait_impl_block): Likewise. * typecheck/rust-hir-type-check-struct.cc (TypeCheckStructExpr::visit): Likewise. * typecheck/rust-tyty-call.cc (TypeCheckCallExpr::visit): Likewise. * typecheck/rust-tyty.cc (BaseType::bounds_compatible): Likewise. * typecheck/rust-unify.cc (UnifyRules::emit_abi_mismatch): Likewise. * util/rust-attributes.cc (AttributeChecker::visit): Likewise. libcpp/ChangeLog: PR c/104896 * pch.cc (cpp_valid_state): Replace "%<%s%>" with "%qs" in message wording. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-11-25nios2: Remove all support for Nios II target.Sandra Loosemore1-43/+0
nios2 target support in GCC was deprecated in GCC 14 as the architecture has been EOL'ed by the vendor. This patch removes the entire port for GCC 15 There are still references to "nios2" in libffi and libgo. Since those libraries are imported into the gcc sources from master copies maintained by other projects, those will need to be addressed elsewhere. ChangeLog: * MAINTAINERS: Remove references to nios2. * configure.ac: Likewise. * configure: Regenerated. config/ChangeLog: * mt-nios2-elf: Deleted. contrib/ChangeLog: * config-list.mk: Remove references to Nios II. gcc/ChangeLog: * common/config/nios2/*: Delete entire directory. * config/nios2/*: Delete entire directory. * config.gcc: Remove references to nios2. * configure.ac: Likewise. * doc/extend.texi: Likewise. * doc/install.texi: Likewise. * doc/invoke.texi: Likewise. * doc/md.texi: Likewise. * regenerate-opt-urls.py: Likewise. * config.in: Regenerated. * configure: Regenerated. gcc/testsuite/ChangeLog: * g++.target/nios2/*: Delete entire directory. * gcc.target/nios2/*: Delete entire directory. * g++.dg/cpp0x/constexpr-rom.C: Remove refences to nios2. * g++.old-deja/g++.jason/thunk3.C: Likewise. * gcc.c-torture/execute/20101011-1.c: Likewise. * gcc.c-torture/execute/pr47237.c: Likewise. * gcc.dg/20020312-2.c: Likewise. * gcc.dg/20021029-1.c: Likewise. * gcc.dg/debug/btf/btf-datasec-1.c: Likewise. * gcc.dg/ifcvt-4.c: Likewise. * gcc.dg/stack-usage-1.c: Likewise. * gcc.dg/struct-by-value-1.c: Likewise. * gcc.dg/tree-ssa/reassoc-33.c: Likewise. * gcc.dg/tree-ssa/reassoc-34.c: Likewise. * gcc.dg/tree-ssa/reassoc-35.c: Likewise. * gcc.dg/tree-ssa/reassoc-36.c: Likewise. * lib/target-supports.exp: Likewise. libgcc/ChangeLog: * config/nios2/*: Delete entire directory. * config.host: Remove refences to nios2. * unwind-dw2-fde-dip.c: Likewise.
2024-11-25RISC-V: Minimal support for svvptc extension.Dongyan Chen2-0/+3
This patch support svvptc extension[1]. To enable GCC to recognize and process svvptc extension correctly at compile time. [1] https://github.com/riscv/riscv-svvptc gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto. * config/riscv/riscv.opt: New mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-44.c: New test.
2024-11-22build: Remove INCLUDE_MEMORY [PR117737]Andrew Pinski3-3/+0
Since diagnostic.h is included in over half of the sources, requiring to `#define INCLUDE_MEMORY` does not make sense. Instead lets unconditionally include memory in system.h. The majority of this patch is just removing `#define INCLUDE_MEMORY` from the sources which currently have it. This should also fix the mingw build issue but I have not tried it. Bootstrapped and tested on x86_64-linux-gnu. PR bootstrap/117737 gcc/ada/ChangeLog: * gcc-interface/misc.cc (INCLUDE_MEMORY): Remove. * gcc-interface/trans.cc (INCLUDE_MEMORY): Remove. * gcc-interface/utils.cc (INCLUDE_MEMORY): Remove. gcc/analyzer/ChangeLog: * access-diagram.cc (INCLUDE_MEMORY): Remove. * analysis-plan.cc (INCLUDE_MEMORY): Remove. * analyzer-language.cc (INCLUDE_MEMORY): Remove. * analyzer-logging.cc (INCLUDE_MEMORY): Remove. * analyzer-pass.cc (INCLUDE_MEMORY): Remove. * analyzer-selftests.cc (INCLUDE_MEMORY): Remove. * analyzer.cc (INCLUDE_MEMORY): Remove. * bar-chart.cc (INCLUDE_MEMORY): Remove. * bounds-checking.cc (INCLUDE_MEMORY): Remove. * call-details.cc (INCLUDE_MEMORY): Remove. * call-info.cc (INCLUDE_MEMORY): Remove. * call-string.cc (INCLUDE_MEMORY): Remove. * call-summary.cc (INCLUDE_MEMORY): Remove. * checker-event.cc (INCLUDE_MEMORY): Remove. * checker-path.cc (INCLUDE_MEMORY): Remove. * complexity.cc (INCLUDE_MEMORY): Remove. * constraint-manager.cc (INCLUDE_MEMORY): Remove. * diagnostic-manager.cc (INCLUDE_MEMORY): Remove. * engine.cc (INCLUDE_MEMORY): Remove. * feasible-graph.cc (INCLUDE_MEMORY): Remove. * infinite-loop.cc (INCLUDE_MEMORY): Remove. * infinite-recursion.cc (INCLUDE_MEMORY): Remove. * kf-analyzer.cc (INCLUDE_MEMORY): Remove. * kf-lang-cp.cc (INCLUDE_MEMORY): Remove. * kf.cc (INCLUDE_MEMORY): Remove. * known-function-manager.cc (INCLUDE_MEMORY): Remove. * pending-diagnostic.cc (INCLUDE_MEMORY): Remove. * program-point.cc (INCLUDE_MEMORY): Remove. * program-state.cc (INCLUDE_MEMORY): Remove. * ranges.cc (INCLUDE_MEMORY): Remove. * record-layout.cc (INCLUDE_MEMORY): Remove. * region-model-asm.cc (INCLUDE_MEMORY): Remove. * region-model-manager.cc (INCLUDE_MEMORY): Remove. * region-model-reachability.cc (INCLUDE_MEMORY): Remove. * region-model.cc (INCLUDE_MEMORY): Remove. * region.cc (INCLUDE_MEMORY): Remove. * sm-fd.cc (INCLUDE_MEMORY): Remove. * sm-file.cc (INCLUDE_MEMORY): Remove. * sm-malloc.cc (INCLUDE_MEMORY): Remove. * sm-pattern-test.cc (INCLUDE_MEMORY): Remove. * sm-sensitive.cc (INCLUDE_MEMORY): Remove. * sm-signal.cc (INCLUDE_MEMORY): Remove. * sm-taint.cc (INCLUDE_MEMORY): Remove. * sm.cc (INCLUDE_MEMORY): Remove. * state-purge.cc (INCLUDE_MEMORY): Remove. * store.cc (INCLUDE_MEMORY): Remove. * supergraph.cc (INCLUDE_MEMORY): Remove. * svalue.cc (INCLUDE_MEMORY): Remove. * symbol.cc (INCLUDE_MEMORY): Remove. * trimmed-graph.cc (INCLUDE_MEMORY): Remove. * varargs.cc (INCLUDE_MEMORY): Remove. gcc/ChangeLog: * asan.cc (INCLUDE_MEMORY): Remove. * attribs.cc (INCLUDE_MEMORY): Remove. * auto-profile.cc (INCLUDE_MEMORY): Remove. * calls.cc (INCLUDE_MEMORY): Remove. * cfganal.cc (INCLUDE_MEMORY): Remove. * cfgexpand.cc (INCLUDE_MEMORY): Remove. * cfghooks.cc (INCLUDE_MEMORY): Remove. * cfgloop.cc (INCLUDE_MEMORY): Remove. * cgraph.cc (INCLUDE_MEMORY): Remove. * cgraphclones.cc (INCLUDE_MEMORY): Remove. * cgraphunit.cc (INCLUDE_MEMORY): Remove. * collect-utils.cc (INCLUDE_MEMORY): Remove. * collect2.cc (INCLUDE_MEMORY): Remove. * common/config/aarch64/aarch64-common.cc (INCLUDE_MEMORY): Remove. * common/config/arm/arm-common.cc (INCLUDE_MEMORY): Remove. * common/config/avr/avr-common.cc (INCLUDE_MEMORY): Remove. * config/aarch64/aarch64-cc-fusion.cc (INCLUDE_MEMORY): Remove. * config/aarch64/aarch64-early-ra.cc (INCLUDE_MEMORY): Remove. * config/aarch64/aarch64-sve-builtins.cc (INCLUDE_MEMORY): Remove. * config/aarch64/aarch64.cc (INCLUDE_MEMORY): Remove. * config/arc/arc.cc (INCLUDE_MEMORY): Remove. * config/arm/aarch-common.cc (INCLUDE_MEMORY) Remove.: * config/arm/arm-mve-builtins.cc (INCLUDE_MEMORY): Remove. * config/arm/arm.cc (INCLUDE_MEMORY): Remove. * config/avr/avr-devices.cc (INCLUDE_MEMORY): Remove. * config/avr/driver-avr.cc (INCLUDE_MEMORY): Remove. * config/bpf/bpf.cc (INCLUDE_MEMORY): Remove. * config/bpf/btfext-out.cc (INCLUDE_MEMORY): Remove. * config/bpf/core-builtins.cc (INCLUDE_MEMORY): Remove. * config/darwin.cc (INCLUDE_MEMORY): Remove. * config/gcn/mkoffload.cc (INCLUDE_MEMORY): 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Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-11-22AVR: Tabify avr-common.cc according to coding rules.Georg-Johann Lay1-26/+26
gcc/ * common/config/avr/avr-common.cc: Tabify.
2024-11-22AVR: Use Var(avropt_xxx) for option variables in avr.opt.Georg-Johann Lay1-4/+4
This is a no-op refactoring that uses a prefix of avropt_ (formerly: avr_) for variables defined qua Var() directives in avr.opt. This makes it easier to spot values that come directly from avr.opt in the rest of the backend. gcc/ * config/avr/avr.opt (avr_bits_e, avr_lra_p, avr_mmcu) (avr_gasisr_prologues, avr_n_flash, avr_log_details) (avr_branch_cost, avr_split_bit_shift, avr_strict_X) (avr_flmap, avr_rodata_in_ram, avr_sp8, avr_fuse_add) (avr_warn_addr_space_convert, avr_warn_misspelled_isr) (avr_fuse_move, avr_double, avr_long_double): Rename to respectively: avropt_bits_e, avropt_lra_p, avropt_mmcu, avropt_gasisr_prologues, avropt_n_flash, avropt_log_details, avropt_branch_cost, avropt_split_bit_shift, avropt_strict_X, avropt_flmap, avropt_rodata_in_ram, avropt_sp8, avropt_fuse_add, avropt_warn_addr_space_convert, avropt_warn_misspelled_isr, avropt_fuse_move, avropt_double, avropt_long_double. * config/avr/avr.h: Same. * config/avr/avr.cc: Same. * config/avr/avr.md: Same. * config/avr/avr-passes.cc * config/avr/avr-log.cc: Same. * common/config/avr/avr-common.cc: Same.
2024-11-21AVR: target/117726 - Better optimizations of ASHIFT:SI insns.Georg-Johann Lay1-0/+1
This patch improves the 4-byte ASHIFT insns. 1) It adds a "r,r,C15" alternative for improved long << 15. 2) It adds 3-operand alternatives (depending on options) and splits them after peephole2 / before avr-fuse-move into a 3-operand byte shift and a 2-operand residual bit shift. For better control, it introduces new option -msplit-bit-shift that's activated at -O2 and higher per default. 2) is even performed with -Os, but not with -Oz. PR target/117726 gcc/ * config/avr/avr.opt (-msplit-bit-shift): Add new optimization option. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_2_PLUS]: Turn on -msplit-bit-shift. * config/avr/avr.h (machine_function.n_avr_fuse_add_executed): New bool component. * config/avr/avr.md (attr "isa") <2op, 3op>: Add new values. (attr "enabled"): Handle them. (ashlsi3, *ashlsi3, *ashlsi3_const): Add "r,r,C15" alternative. Add "r,0,C4l" and "r,r,C4l" alternatives (depending on 2op / 3op). (define_split) [avr_split_bit_shift]: Add 2 new ashift:ALL4 splitters. (define_peephole2) [ashift:ALL4]: Add (match_dup 3) so that the scratch won't overlap with the output operand of the matched insn. (*ashl<mode>3_const_split): Remove unused ashift:ALL4 splitter. * config/avr/avr-passes.cc (emit_valid_insn) (emit_valid_move_clobbercc): Move out of anonymous namespace. (make_avr_pass_fuse_add) <gate>: Don't override. <execute>: Set n_avr_fuse_add_executed according to func->machine->n_avr_fuse_add_executed. (pass_data avr_pass_data_split_after_peephole2): New object. (avr_pass_split_after_peephole2): New rtl_opt_pass. (avr_emit_shift): New static function. (avr_shift_is_3op, avr_split_shift_p, avr_split_shift) (make_avr_pass_split_after_peephole2): New functions. * config/avr/avr-passes.def (avr_pass_split_after_peephole2): Insert new pass after pass_peephole2. * config/avr/avr-protos.h (n_avr_fuse_add_executed, avr_shift_is_3op, avr_split_shift_p) (avr_split_shift, avr_optimize_size_level) (make_avr_pass_split_after_peephole2): New prototypes. * config/avr/avr.cc (n_avr_fuse_add_executed): New global variable. (avr_optimize_size_level): New function. (avr_set_current_function): Set n_avr_fuse_add_executed according to cfun->machine->n_avr_fuse_add_executed. (ashlsi3_out) [case 15]: Output optimized code for this offset. (avr_rtx_costs_1) [ASHIFT, SImode]: Adjust costs of oggsets 15, 16. * config/avr/constraints.md (C4a, C4r, C4r): New constraints. * pass_manager.h (pass_manager): Adjust comments.
2024-11-20RISC-V: Add the mini support for SiFive extensions.yulong1-0/+6
This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and xsfvfnrclipxfqf extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New. * config/riscv/riscv.opt: New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-sf-3.c: New test. * gcc.target/riscv/predef-sf-4.c: New test. * gcc.target/riscv/predef-sf-5.c: New test.
2024-11-18AVR: target/84211 - Add a post reload register optimization pass.Georg-Johann Lay1-0/+2
This introduces a new post reload pass that tracks known values held in registers and performs optimizations based on that knowledge. It runs between the two instances of the RTL peephole pass. The optimizations are activated by new option -mfuse-move=<0,23> which provides a 3:2:2:2 mixed radix value: Digit 0: Activates try_fuse: Tries to use a MOVW instead of two LDIs. Digit 1: Activates try_bin_arg1: Simplify the 2nd operand of a binary operation, for example X xor Y can be simplified to X when Y = 0. When Y is an expensive constant that's already held in some register R, then the expression can be replaced by X xor R. Digit 2: Activates try_split_any: Split multi-byte operations like shifts into 8-bit instructions. Digit 3: Activates try_split_ldi: Decompose LDI-like insns into a sequence of instructions with better performance. For example, R2[4] = 0x1ff may be performed as: CLR R5 CLR R4 MOVW R2, R4 INC R3 DEC R2 Digit 3 can have a value of 0, 1 or 2, where value=2 may come up with code that performs better than with value=1 at the expense of reduced traceability of the generated assembly code. Here are some examples: Without optimization | With optimization ==================== | ================= long long fn_zero (void) { return 0; } ldi r18, 0 ; movqi_insn | ldi r18, 0 ; movqi_insn ldi r19, 0 ; movqi_insn | ldi r19, 0 ; movqi_insn ldi r20, 0 ; movqi_insn | movw r20, r18 ; *movhi ldi r21, 0 ; movqi_insn | ldi r22, 0 ; movqi_insn | movw r22, r18 ; *movhi ldi r23, 0 ; movqi_insn | ldi r24, 0 ; movqi_insn | movw r24, r18 ; *movhi ldi r25, 0 ; movqi_insn | ret | ret int fn_eq0 (char c) { return c == 0; } mov r18, r24 ; movqi_insn | mov r18, r24 ; movqi_insn ldi r24, 1 ; *movhi | ldi r24, 1 ; *movhi ldi r25, 0 | ldi r25, 0 cp r18, ZERO ; cmpqi3 | cpse r18, ZERO ; peephole breq .+4 ; branch | ldi r24, 0 ; *movhi | ldi r24, 0 ; movqi_insn ldi r25, 0 | ret | ret unsigned fn_crc (unsigned x, unsigned y) { for (char i = 8; i--; x <<= 1) y ^= (x ^ y) & 0x80 ? 79u : 0u; return y; } movw r18, r24 ; *movhi | movw r18, r24 ; *movhi movw r24, r22 ; *movhi | movw r24, r22 ; *movhi ldi r22, 8 ; movqi_insn | ldi r22, 8 ; movqi_insn .L13: | .L13: movw r30, r18 ; *movhi | movw r30, r18 ; *movhi eor r30, r24 ; *xorqi3 | eor r30, r24 ; *xorqi3 eor r31, r25 ; *xorqi3 | eor r31, r25 ; *xorqi3 mov r20, r30 ; *andhi3 | mov r20, r30 ; *andqi3 andi r20, 1<<7 | andi r20, 1<<7 clr r21 | sbrs r30, 7 ; *sbrx_branchhi | sbrc r30, 7 ; *sbrx_branchhi rjmp .+4 | ldi r20, 79 ; movqi_insn | ldi r20, 79 ; movqi_insn ldi r21, 0 ; movqi_insn | eor r24, r20 ; *xorqi3 | eor r24, r20 ; *xorqi3 eor r25, r21 ; *xorqi3 | lsl r18 ; *ashlhi3_const | lsl r18 ; *ashlhi3_const rol r19 | rol r19 subi r22, 1 ; *op8.for.cczn.p| subi r22, 1 ; *op8.for.cczn.plus brne .L13 ; branch_ZN | brne .L13 ; branch_ZN ret | ret #define SPDR (*(uint8_t volatile*) 0x2c) void fn_PR49807 (long big) { SPDR = big >> 24; SPDR = big >> 16; SPDR = big >> 8; SPDR = big; } movw r20, r22 ; *movhi | movw r20, r22 ; *movhi movw r22, r24 ; *movhi | movw r22, r24 ; *movhi mov r24, r23 ; *ashrsi3_const | clr r27 | sbrc r24,7 | com r27 | mov r25, r27 | mov r26, r27 | out 0xc, r24 ; movqi_insn | out 0xc, r23 ; movqi_insn movw r24, r22 ; *ashrsi3_const | clr r27 | sbrc r25, 7 | com r27 | mov r26, r27 | out 0xc, r24 ; movqi_insn | out 0xc, r24 ; movqi_insn clr r27 ; *ashrsi3_const | sbrc r23, 7 | dec r27 | mov r26, r23 | mov r25, r22 | mov r24, r21 | out 0xc, r24 ; movqi_insn | out 0xc, r21 ; movqi_insn out 0xc, r20 ; movqi_insn | out 0xc, r20 ; movqi_insn ret | ret PR target/84211 gcc/ * doc/invoke.texi (AVR Options) [-mfuse-move]: Document new option. * common/config/avr/avr-common.cc (avr_option_optimization_table): Set -mfuse-move= depending on optimization level. * config/avr/avr.opt (-mfuse-move, -mfuse-move=): New options. * config/avr/t-avr (avr-passes.o): Depend on avr-passes-fuse-move.h. * config/avr/avr-passes-fuse-move.h: New file, used by avr-passes.cc. * config/avr/avr-passes.def (avr_pass_fuse_move): Insert new pass. * config/avr/avr-passes.cc (INCLUDE_ARRAY): Define it. (insn-attr.h): Include it. (avr_pass_data_fuse_move): New const pass_data. (avr_pass_fuse_move): New public rtl_opt_pass class. (make_avr_pass_fuse_move): New function. (gprmask_t): New typedef. (next_nondebug_insn_bb, prev_nondebug_insn_bb) (single_set_with_scratch, size_to_mask, size_to_mode) (emit_valid_insn, emit_valid_move_clobbercc) (gpr_regno_p, regmask, has_bits_in) (find_arith, find_arith2, any_shift_p): New local functions. (AVRasm): New namespace. (FUSE_MOVE_MAX_MODESIZE): New define. (avr-passes-fuse-move.h): New include. (memento_t, absint_t, absins_byte_t, absint_val_t) (optimize_data_t, insn_optimizedata_t, find_plies_data_t) (insninfo_t, bbinfo_t, ply_t, plies_t): New structs / classes. * config/avr/avr-protos.h (avr_chunk, avr_byte, avr_word, avr_int8) (avr_uint8, avr_int16, avr_uint16) (avr_out_set_some, avr_set_some_operation) (output_reload_in_const, make_avr_pass_fuse_move): New protos. (avr_dump): Depend macro definition on GCC_DUMPFILE_H. * config/avr/avr.cc (avr_option_override): Insert after pass "avr-fuse-move" instead of after "peephole2". (avr_chunk, avr_byte, avr_word, avr_int8, avr_uint8, avr_int16) (avr_uint16, output_reload_in_const): Functions are no more static. (avr_out_set_some, avr_set_some_operation): New functions. (ashrqi3_out, ashlqi3_out) [offset=7]: Handle "r,r,C07" alternative. (avr_out_insert_notbit): Comment also allows QImode. (avr_adjust_insn_length) [ADJUST_LEN_SET_SOME]: Handle case. * config/avr/avr.md (adjust_len) <set_some>: New attribute value. (set_some): New insn. (andqi3, *andqi3): Add "r,r,Cb1" alternative. (ashrqi3, *ashrqi3 ashlqi3, *ashlqi3): Add a "r,r,C07" alternative. (gen_move_clobbercc_scratch): New emit helper. * config/avr/constraints.md (Cb1): New constraint. * config/avr/predicates.md (dreg_or_0_operand, set_some_operation): New. * config/avr/avr-log.cc (avr_forward_to_printf): New static func. (avr_log_vadump): Use it to recognize more formats. gcc/testsuite/ * gcc.target/avr/torture/test-gprs.h: New file. * gcc.target/avr/torture/pr84211-fuse-move-1.c: New test. * gcc.target/avr/torture/pr84211-fuse-move-2.c: New test.
2024-11-13RISC-V: Implement riscv_minimal_hwprobe_feature_bitsYangyu Chen2-0/+177
This patch implements the riscv_minimal_hwprobe_feature_bits feature for the RISC-V target. The feature bits are defined in the libgcc/config/riscv/feature_bits.c to provide bitmasks of ISA extensions that defined in RISC-V C-API. Thus, we need a function to generate the feature bits for IFUNC resolver to dispatch between different functions based on the hardware features. The minimal feature bits means to use the earliest extension appeard in the Linux hwprobe to cover the given ISA string. To allow older kernels without some implied extensions probe to run the FMV dispatcher correctly. For example, V implies Zve32x, but Zve32x appears in the Linux kernel since v6.11. If we use isa string directly to generate FMV dispatcher with functions with "arch=+v" extension, since we have V implied the Zve32x, FMV dispatcher will check if the Zve32x extension is supported by the host. If the Linux kernel is older than v6.11, the FMV dispatcher will fail to detect the Zve32x extension even it already implies by the V extension, thus making the FMV dispatcher fail to dispatch the correct function. Thus, we need to generate the minimal feature bits to cover the given ISA string to allow the FMV dispatcher to work correctly on older kernels. Signed-off-by: Yangyu Chen <cyy@cyyself.name> gcc/ChangeLog: * common/config/riscv/riscv-common.cc (RISCV_EXT_BITMASK): New macro. (struct riscv_ext_bitmask_table_t): New struct. (riscv_minimal_hwprobe_feature_bits): New function. * common/config/riscv/riscv-ext-bitmask.def: New file. * config/riscv/riscv-subset.h (GCC_RISCV_SUBSET_H): Include riscv-feature-bits.h. (riscv_minimal_hwprobe_feature_bits): Declare the function. * config/riscv/riscv-feature-bits.h: New file.
2024-11-11Initial Diamond Rapids SupportHaochen Jiang3-0/+20
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Diamond Rapids. * common/config/i386/i386-common.cc (processor_name): Add Diamond Rapids. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add INTEL_COREI7_DIAMONDRAPIDS. * config.gcc: Add -march=diamondrapids. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle diamondrapids. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (processor_cost_table): Ditto. (m_DIAMONDRAPIDS): New. (m_CORE_AVX512): Add diamondrapids. * config/i386/i386.h (enum processor_type): Ditto. * doc/extend.texi: Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Ditto. * gcc.target/i386/funcspec-56.inc: Handle new march.
2024-11-11i386: Add new model number for Arrow LakeHaochen Jiang1-0/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Add new model number for Arrow Lake.
2024-11-01Support Intel AMX-MOVRSHu, Lin14-1/+22
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-MOVRS. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_MOVRS_SET): New. (OPTION_MASK_ISA2_AMX_MOVRS_UNSET): Ditto. (ix86_handle_option): Handle -mamx-movrs. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_MOVRS. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-movrs. * config.gcc: Add amxmovrsintrin.h. * config/i386/cpuid.h (bit_AMX_MOVRS): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_MOVRS__. * config/i386/i386-isa.def (AMX_MOVRS): Add DEF_PTA(AMX_MOVRS). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-movrs. * config/i386/i386.opt: Add option -mamx-movrs. * config/i386/i386.opt.urls: Regenerated. * config/i386/immintrin.h: Include amxmovrsintrin.h * doc/extend.texi: Document amx-movrs. * doc/invoke.texi: Document -mamx-movrs. * doc/sourcebuild.texi: Document target amx-movrs. * config/i386/amxmovrsintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-movrs. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add new check for amx-movrs. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-movrs. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-movrs. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_movrs): New. * gcc.target/i386/amxmovrs-asmatt-1.c: New test. * gcc.target/i386/amxmovrs-asmintel-1.c: Ditto. * gcc.target/i386/amxmovrs-t2rpntlvw-2.c: Ditto. * gcc.target/i386/amxmovrs-tileloaddrs-2.c: Ditto.
2024-11-01Support Intel MOVRSHu, Lin14-0/+20
gcc/ChangeLog: * builtins.cc (expand_builtin_prefetch): Expand for prefetchrst2. * common/config/i386/cpuinfo.h (get_available_features): Detect movrs. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_MOVRS_SET): New. (OPTION_MASK_ISA2_MOVRS_UNSET): Ditto. (ix86_handle_option): Handle -mmovrs. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_MOVRS. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for movrs. * config.gcc: Add movrsintrin.h * config/i386/cpuid.h (bit_MOVRS): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (CHAR, PCCHAR), (SHORT, PCSHORT), (INT, PCINT), (INT64, PCINT64). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Add __MOVRS__. * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Define __MOVRS__. * config/i386/i386-isa.def (MOVRS): Add DEF_PTA(MOVRS) * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle movrs. * config/i386/i386.md (movrs<mode>): New. * config/i386/i386.opt: Add option -mmovrs. * config/i386/i386.opt.urls: Regenerated. * config/i386/immintrin.h: Include movrsintrin.h * config/i386/sse.md (unspecv): Add UNSPEC_VMOVRS. (VI1248_AVX10_2): New. (avx10_2_movrs_vmovrs<ssemodesuffix><mode><mask_name>): New define_insn. * config/i386/xmmintrin.h: Add prefetchrst2. * doc/extend.texi: Document movrs. * doc/invoke.texi: Document -mmovrs. * doc/rtl.texi: Document extension of prefetchrst2. * doc/sourcebuild.texi: Document target movrs. * config/i386/movrsintrin.h: New. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mmovrs. * g++.dg/other/i386-3.C: Ditto. * gcc.c-torture/execute/builtin-prefetch-1.c: Expand rws. * gcc.dg/builtin-prefetch-1.c: Ditto. * gcc.target/i386/avx-1.c: Ditto. * gcc.target/i386/avx-2.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mmovrs. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add movrs. * gcc.target/i386/sse-23.c: Ditto * gcc.target/i386/avx10_2-512-movrs-1.c: New test. * gcc.target/i386/avx10_2-movrs-1.c: Ditto. * gcc.target/i386/movrs-1.c: Ditto. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2024-11-01Support Intel AMX-FP8Liwei Xu4-1/+22
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect amx-fp8. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_FP8_SET): New macros. (OPTION_MASK_ISA2_AMX_FP8_UNSET): Ditto. (ix86_handle_option): Handle -mamx-fp8. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_FP8. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-fp8. * config.gcc: Add amxfp8intrin.h. * config/i386/cpuid.h (bit_AMX_FP8): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_FP8__. * config/i386/i386-isa.def (AMX_FP8): Add DEF_PTA for AMX_FP8. * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Add new ATTR. * config/i386/i386.opt: Add -mamx-fp8. * config/i386/i386.opt.urls: Regenerated. * config/i386/immintrin.h: Include amxfp8intrin.h. * doc/extend.texi: Document -mamx-fp8. * doc/invoke.texi: Document -mamx-fp8. * doc/sourcebuild.texi: Document -mamx-fp8. * config/i386/amxfp8intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-fp8. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Check for amx-fp8. * gcc.target/i386/amx-helper.h: Ditto. * gcc.target/i386/fp8-helper.h: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-fp8. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: New proc. * gcc.target/i386/amxfp8-asmatt-1.c: New test. * gcc.target/i386/amxfp8-asmintel-1.c: Ditto. * gcc.target/i386/amxfp8-dpbf8ps-2.c: Ditto. * gcc.target/i386/amxfp8-dpbhf8ps-2.c: Ditto. * gcc.target/i386/amxfp8-dphbf8ps-2.c: Ditto. * gcc.target/i386/amxfp8-dphf8ps-2.c: Ditto. * gcc.target/i386/fp-emulation.h: Emulates NaN behaviour. Co-authored-by: Hu, Lin1 <lin1.hu@intel.com>
2024-11-01Support Intel AMX-TRANSPOSEHaochen Jiang4-1/+23
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-TRANSPOSE. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_TRANSPOSE_SET, OPTION_MASK_ISA2_AMX_TRANSPOSE_UNSET): New. (ix86_handle_option): Handle -mamx-transpose. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_TRANSPOSE. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-transpose. * config.gcc: Add amxtransposeintrin.h. * config/i386/cpuid.h (bit_AMX_TRANSPOSE): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_TRANSPOSE__. * config/i386/i386-isa.def (AMX_TRANSPOSE): Add DEF_PTA(AMX_TRANSPOSE). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-transpose. * config/i386/i386.opt: Add option -mamx-transpose. * config/i386/i386.opt.urls: Regenerated. * config/i386/immintrin.h: Include amxtransposeintrin.h. * doc/extend.texi: Document amx-transpose. * doc/invoke.texi: Document -mamx-transpose. * doc/sourcebuild.texi: Document target amx-transpose. * config/i386/amxtransposeintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-transpose. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add new check for amx-transpose. (__tilepair): New. (zero_pair_tile_src): New. (check_pair_tile_register): New. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-helper.h: Add amx-transpose support. (init_pair_tile_src): New function. * gcc.target/i386/sse-12.c: Add -mamx-tranpose. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-transpose. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_transposed): New. * gcc.target/i386/amxtranspose-asmatt-1.c: New test. * gcc.target/i386/amxtranspose-asmintel-1.c: Ditto. * gcc.target/i386/amxtranspose-2rpntlvw-2.c: Ditto. * gcc.target/i386/amxtranspose-conjtcmmimfp16ps-2.c: Ditto. * gcc.target/i386/amxtranspose-conjtfp16-2.c: Ditto. * gcc.target/i386/amxtranspose-tcmmimfp16ps-2.c: Ditto. * gcc.target/i386/amxtranspose-tcmmrlfp16ps-2.c: Ditto. * gcc.target/i386/amxtranspose-tdpbf16ps-2.c: Ditto. * gcc.target/i386/amxtranspose-tdpfp16ps-2.c: Ditto. * gcc.target/i386/amxtranspose-tmmultf32ps-2.c: Ditto. * gcc.target/i386/amxtranspose-transposed-2.c: Ditto.
2024-11-01Support Intel AMX-TF32Haochen Jiang4-1/+22
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-TF32. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_TF32_SET, OPTION_MASK_ISA2_AMX_TF32_UNSET): New. (ix86_handle_option): Handle -mamx-tf32. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_TF32. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-tf32. * config.gcc: Add amxtf32intrin.h * config/i386/cpuid.h (bit_AMX_TF32): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle amx-tf32. * config/i386/i386-isa.def (AMX_TF32): Add DEF_PTA(AMX_TF32). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-tf32. * config/i386/i386.opt: Add option -mamx-tf32. * config/i386/i386.opt.urls: Regenerated. * config/i386/immintrin.h: Include amxtf32intrin.h. * doc/extend.texi: Document amx-tf32. * doc/invoke.texi: Document -mamx-tf32. * doc/sourcebuild.texi: Document target amx-tf32. * config/i386/amxtf32intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-tf32. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add cpu check for AMX-TF32. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-tf32. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-tf32. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_tf32): New. * gcc.target/i386/amx-helper.h: New file for tf32 support. * gcc.target/i386/amxtf32-asmatt-1.c: New test. * gcc.target/i386/amxtf32-asmintel-1.c: Ditto. * gcc.target/i386/amxtf32-mmultf32ps-2.c: Ditto.
2024-11-01Support Intel AMX-AVX512Haochen Jiang4-2/+36
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-AVX512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_AVX512_SET, OPTION_MASK_ISA2_AMX_AVX512_UNSET): New. (ix86_handle_option): Handle -mamx-avx512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_AVX512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-avx512. * config.gcc: Add amxavx512intrin.h * config/i386/cpuid.h (bit_AMX_AVX512): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle amx-avx512. * config/i386/i386-isa.def (AMX_AVX512): Add DEF_PTA(AMX_AVX512). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-avx512. * config/i386/i386.opt: Add option -mamx-avx512. * config/i386/i386.opt.urls: Regenerated. * config/i386/immintrin.h: Include amxavx512intrin.h * doc/extend.texi: Document amx-avx512. * doc/invoke.texi: Document -mamx-avx512. * doc/sourcebuild.texi: Document target amx-avx512. * config/i386/amxavx512intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-avx512. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add cpu check for AMX-AVX512. * gcc.target/i386/amx-helper.h: Support amx-avx512. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-avx512. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-avx512. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_avx512): New. * gcc.target/i386/amxavx512-asmatt-1.c: New test. * gcc.target/i386/amxavx512-asmintel-1.c: Ditto. * gcc.target/i386/amxavx512-cvtrowd2ps-2.c: Ditto. * gcc.target/i386/amxavx512-cvtrowps2pbf16-2.c: Ditto. * gcc.target/i386/amxavx512-cvtrowps2ph-2.c: Ditto. * gcc.target/i386/amxavx512-movrow-2.c: Ditto. Co-authored-by: Yu, Bing <bing1.yu@intel.com>
2024-10-29[RISC-V] RISC-V: Add implication for M extension.Tsung Chun Lin1-0/+2
That M implies Zmmul. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: M implies Zmmul. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-15.c: Add _zmmul1p0 to arch string. * gcc.target/riscv/attribute-16.c: Ditto. * gcc.target/riscv/attribute-17.c: Ditto. * gcc.target/riscv/attribute-18.c: Ditto. * gcc.target/riscv/attribute-19.c: Ditto. * gcc.target/riscv/pr110696.c: Ditto. * gcc.target/riscv/target-attr-01.c: Ditto. * gcc.target/riscv/target-attr-02.c: Ditto. * gcc.target/riscv/target-attr-03.c: Ditto. * gcc.target/riscv/target-attr-04.c: Ditto. * gcc.target/riscv/target-attr-08.c: Ditto. * gcc.target/riscv/target-attr-11.c: Ditto. * gcc.target/riscv/target-attr-14.c: Ditto. * gcc.target/riscv/target-attr-15.c: Ditto. * gcc.target/riscv/target-attr-16.c: Ditto. * gcc.target/riscv/rvv/base/pr114352-1.c: Likewise. * gcc.target/riscv/rvv/base/pr114352-3.c: Likewise. * gcc.dg/pr90838.c: Fix search string for rv64. Co-Authored-By: Jeff Law <jlaw@ventanamicro.com>
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