riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-12-05	AVR: target/107957 - Split multi-byte loads and stores.	Georg-Johann Lay	1	-0/+1
2024-11-29	AArch64: Suppress default options when march or mcpu used is not affected by it.	Tamar Christina	1	-0/+27
2024-11-27	diagnostics: replace %<%s%> with %qs [PR104896]	David Malcolm	2	-2/+2
2024-11-25	nios2: Remove all support for Nios II target.	Sandra Loosemore	1	-43/+0
2024-11-25	RISC-V: Minimal support for svvptc extension.	Dongyan Chen	2	-0/+3
2024-11-22	build: Remove INCLUDE_MEMORY [PR117737]	Andrew Pinski	3	-3/+0
2024-11-22	AVR: Tabify avr-common.cc according to coding rules.	Georg-Johann Lay	1	-26/+26
2024-11-22	AVR: Use Var(avropt_xxx) for option variables in avr.opt.	Georg-Johann Lay	1	-4/+4
2024-11-21	AVR: target/117726 - Better optimizations of ASHIFT:SI insns.	Georg-Johann Lay	1	-0/+1
2024-11-20	RISC-V: Add the mini support for SiFive extensions.	yulong	1	-0/+6
2024-11-18	AVR: target/84211 - Add a post reload register optimization pass.	Georg-Johann Lay	1	-0/+2
2024-11-13	RISC-V: Implement riscv_minimal_hwprobe_feature_bits	Yangyu Chen	2	-0/+177
2024-11-11	Initial Diamond Rapids Support	Haochen Jiang	3	-0/+20
2024-11-11	i386: Add new model number for Arrow Lake	Haochen Jiang	1	-0/+1
2024-11-01	Support Intel AMX-MOVRS	Hu, Lin1	4	-1/+22
2024-11-01	Support Intel MOVRS	Hu, Lin1	4	-0/+20
2024-11-01	Support Intel AMX-FP8	Liwei Xu	4	-1/+22
2024-11-01	Support Intel AMX-TRANSPOSE	Haochen Jiang	4	-1/+23
2024-11-01	Support Intel AMX-TF32	Haochen Jiang	4	-1/+22
2024-11-01	Support Intel AMX-AVX512	Haochen Jiang	4	-2/+36
2024-10-29	[RISC-V] RISC-V: Add implication for M extension.	Tsung Chun Lin	1	-0/+2
2024-10-25	gcc: Remove trailing whitespace	Jakub Jelinek	7	-9/+9
2024-10-24	Use unique_ptr in more places in pretty_printer/diagnostics [PR116613]	David Malcolm	3	-0/+3
2024-10-21	i386: Refactor get_intel_cpu	Haochen Jiang	1	-295/+292
2024-10-09	Revert "RISC-V: Add implication for M extension."	Jeff Law	1	-2/+0
2024-10-08	RISC-V: Add implication for M extension.	Tsung Chun Lin	1	-0/+2
2024-10-08	RISC-V: Implement TARGET_CAN_INLINE_P	Yangyu Chen	1	-165/+207
2024-10-08	RISC-V: Add an implicit dependency for Zawrs	Xiao Zeng	1	-0/+1
2024-09-27	i386: Modernize AMD processor types	Uros Bizjak	1	-35/+11
2024-09-06	AVR: Remove "Atmel" from header comment.	Georg-Johann Lay	1	-1/+1
2024-09-06	RISC-V: Fix out of index in riscv_select_multilib_by_abi	YunQiang Su	1	-1/+1
2024-09-05	RISC-V: Lookup reversely in riscv_select_multilib_by_abi	YunQiang Su	1	-1/+1
2024-08-12	Initial support for AVX10.2	Haochen Jiang	4	-2/+52
2024-08-08	RISC-V: Minimal support for Zimop extension.	Jiawei	1	-0/+8
2024-07-31	pru: Enable section anchoring by default	Dimitar Dimitrov	1	-0/+12
2024-07-30	RISC-V: Add configure check for B extention support	Edwin Lu	1	-0/+8
2024-07-30	RISC-V: Add basic support for the Zacas extension	Gianluca Guida	1	-0/+3
2024-07-30	RISC-V: Remove configure check for zabha	Patrick O'Neill	1	-9/+3
2024-07-24	aarch64: Extend aarch64_feature_flags to 128 bits	Andrew Carlotti	1	-4/+8
2024-07-24	aarch64: Decouple feature flag option storage type	Andrew Carlotti	1	-5/+6
2024-07-24	aarch64: Define aarch64_get_{asm_\|}isa_flags	Andrew Carlotti	1	-1/+1
2024-07-15	RISC-V: Allow adding enabled extension via target arch attributes	Christoph Müllner	1	-6/+11
2024-07-15	RISC-V: Rewrite target attribute handling	Christoph Müllner	1	-109/+4
2024-07-12	RISC-V: Add SiFive extensions, xsfvcp and xsfcease	Kito Cheng	1	-0/+8
2024-07-11	RISC-V: c implies zca, and conditionally zcf & zcd	Fei Gao	1	-0/+12
2024-07-10	RISC-V: Add support for B standard extension	Edwin Lu	1	-0/+7
2024-07-09	RISC-V: Deduplicate arch subset list processing	Christoph Müllner	1	-26/+6
2024-07-09	i386: Correct AVX10 CPUID emulation	Haochen Jiang	1	-2/+2
2024-07-08	[RISC-V] add implied extension repeatly until stable	Fei Gao	1	-3/+11
2024-07-03	RISC-V: Add support for Zabha extension	Gianluca Guida	1	-0/+12