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2023-08-07Daily bump.GCC Administrator4-1/+43
2023-08-06[Committed] Avoid FAIL of gcc.target/i386/pr110792.cRoger Sayle1-1/+0
2023-08-06Add builtin_expect to predict that CPU supports cpuid to cpuid.hJan Hubicka1-2/+2
2023-08-06Disable loop distribution for loops with estimated iterations 0Jan Hubicka1-2/+13
2023-08-06Fix profile update after peeled epiloguesJan Hubicka16-2/+41
2023-08-06libstdc++: [_GLIBCXX_INLINE_VERSION] Add __cxa_call_terminate symbol exportFrançois Dumont1-0/+1
2023-08-06Daily bump.GCC Administrator6-1/+48
2023-08-05PR modula2/110779 SysClock can not read the clockGaius Mulley12-113/+812
2023-08-05c: Less warnings for parameters declared as arrays [PR98536]Martin Uecker3-32/+3
2023-08-05c: _Generic should not warn in non-active branches [PR68193,PR97100,PR110703]Martin Uecker2-1/+26
2023-08-05Daily bump.GCC Administrator7-1/+1149
2023-08-04[PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condi...Xiao Zeng1-15/+102
2023-08-04analyzer: handle function attribute "alloc_size" [PR110426]David Malcolm21-63/+458
2023-08-04analyzer: fix some svalue::dump_to_pp implementationsDavid Malcolm1-7/+20
2023-08-04i386: eliminate redundant operands of VPTERNLOGYan Simonaytes5-0/+121
2023-08-04Specify signed/unsigned/dontcare in calls to extract_bit_field_1.Roger Sayle2-2/+26
2023-08-04i386: Split SUBREGs of SSE vector registers into vec_select insns.Roger Sayle2-0/+18
2023-08-04Add documentation for -Wflex-array-member-not-at-end.Qing Zhao1-0/+13
2023-08-04LRA: Check input insn pattern hard regs against early clobber hard regs for l...Vladimir N. Makarov2-1/+27
2023-08-04middle-end: clean up vect testsuite using pragma novectorTamar Christina672-3/+989
2023-08-04frontend: Add novector C pragmaTamar Christina4-39/+146
2023-08-04frontend: Add novector C++ pragmaTamar Christina9-74/+217
2023-08-04AArch64: Undo vec_widen_<sur>shiftl optabs [PR106346]Tamar Christina5-79/+110
2023-08-04gensupport: Don't segfault on empty attrs listTamar Christina1-2/+2
2023-08-04AArch64: update costing for combining vector conditionalsTamar Christina1-2/+57
2023-08-04AArch64: update costing for MLA by invariantTamar Christina1-9/+15
2023-08-04tree-optimization/110838 - vectorization of widened right shiftsRichard Biener2-5/+48
2023-08-04mid-end: Use integral time intervals in timevar.ccMatthew Malcomson2-44/+56
2023-08-04tree-optimization/110838 - less aggressively fold out-of-bound shiftsRichard Biener1-0/+4
2023-08-04Revert "RISC-V: Support RVV VFMACC rounding mode intrinsic API"Pan Li6-93/+6
2023-08-04Revert "RISC-V: Support RVV VFNMACC rounding mode intrinsic API"Pan Li4-74/+0
2023-08-04Revert "RISC-V: Support RVV VFMSAC rounding mode intrinsic API"Pan Li4-74/+0
2023-08-04Revert "RISC-V: Support RVV VFNMSAC rounding mode intrinsic API"Pan Li4-74/+0
2023-08-04AVR: Add some more devices: AVR16DD*, AVR32DD*, AVR64DD*, AVR64EA*, ATtiny42*...Georg-Johann Lay2-3/+32
2023-08-04Fix some minor typos in avr-mcus.def.Georg-Johann Lay1-17/+17
2023-08-04Fix PR 110874: infinite loop in gimple_bitwise_inverted_equal_p with freAndrew Pinski3-42/+79
2023-08-04match.pd: Canonicalize (signed x << c) >> c [PR101955]Drew Ross2-6/+77
2023-08-04RISC-V: Support RVV VFNMSAC rounding mode intrinsic APIPan Li4-0/+74
2023-08-04RISC-V: Support RVV VFMSAC rounding mode intrinsic APIPan Li4-0/+74
2023-08-04RISC-V: Support RVV VFNMACC rounding mode intrinsic APIPan Li4-0/+74
2023-08-04AArch64: Avoid the ICE on empty reduction definition in info_for_reduction [P...Hao Liu2-1/+36
2023-08-04RISC-V: Support RVV VFMACC rounding mode intrinsic APIPan Li6-6/+93
2023-08-04RISC-V: Support RVV VFWMUL rounding mode intrinsic APIPan Li5-1/+51
2023-08-04RISC-V: Support RVV VFDIV and VFRDIV rounding mode intrinsic APIPan Li6-1/+89
2023-08-04Daily bump.GCC Administrator6-1/+370
2023-08-03Print entry count in print_loop_infoJan Hubicka1-1/+2
2023-08-03Update loop iteration estimates after splittingJan Hubicka1-2/+32
2023-08-03Fix profiledbootstrapJan Hubicka1-1/+1
2023-08-03Read global value/mask in IPA.Aldy Hernandez4-40/+47
2023-08-03[PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with cond...Xiao Zeng2-6/+58
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