RISC-V: Support RVV VFWMUL rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFWMUL for the below samples.

* __riscv_vfwmul_vv_f64m2_rm
* __riscv_vfwmul_vv_f64m2_rm_m
* __riscv_vfwmul_vf_f64m2_rm
* __riscv_vfwmul_vf_f64m2_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(vfwmul_frm_obj): New declaration.
	(vfwmul_frm): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h:
	(vfwmul_frm): Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfwmul_frm): New function definition.
	* config/riscv/vector.md: (frm_mode) Add vfwmul to frm_mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-widening-mul.c: New test.

5 files changed, 51 insertions, 1 deletions

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 61a5065..afe3735 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -322,6 +322,7 @@ public:
 /* Implements below instructions for frm
    - vfwadd
    - vfwsub
+   - vfwmul
 */
 template<rtx_code CODE>
 class widen_binop_frm : public function_base
@@ -2113,6 +2114,7 @@ static CONSTEXPR const binop_frm<DIV> vfdiv_frm_obj;
 static CONSTEXPR const reverse_binop<DIV> vfrdiv_obj;
 static CONSTEXPR const reverse_binop_frm<DIV> vfrdiv_frm_obj;
 static CONSTEXPR const widen_binop<MULT> vfwmul_obj;
+static CONSTEXPR const widen_binop_frm<MULT> vfwmul_frm_obj;
 static CONSTEXPR const vfmacc vfmacc_obj;
 static CONSTEXPR const vfnmsac vfnmsac_obj;
 static CONSTEXPR const vfmadd vfmadd_obj;
@@ -2347,6 +2349,7 @@ BASE (vfdiv_frm)
 BASE (vfrdiv)
 BASE (vfrdiv_frm)
 BASE (vfwmul)
+BASE (vfwmul_frm)
 BASE (vfmacc)
 BASE (vfnmsac)
 BASE (vfmadd)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index f35fd3d..2d2b52a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -158,6 +158,7 @@ extern const function_base *const vfdiv_frm;
 extern const function_base *const vfrdiv;
 extern const function_base *const vfrdiv_frm;
 extern const function_base *const vfwmul;
+extern const function_base *const vfwmul_frm;
 extern const function_base *const vfmacc;
 extern const function_base *const vfnmsac;
 extern const function_base *const vfmadd;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index e7e6c7d..d43b33d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -328,6 +328,8 @@ DEF_RVV_FUNCTION (vfrdiv_frm, alu_frm, full_preds, f_vvf_ops)
 // 13.5. Vector Widening Floating-Point Multiply
 DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops)
 DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvf_ops)
+DEF_RVV_FUNCTION (vfwmul_frm, alu_frm, full_preds, f_wvv_ops)
+DEF_RVV_FUNCTION (vfwmul_frm, alu_frm, full_preds, f_wvf_ops)
 
 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
 DEF_RVV_FUNCTION (vfmacc, alu, full_preds, f_vvvv_ops)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 4b6c385..750b2de 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -866,7 +866,7 @@
 
 ;; Defines rounding mode of an floating-point operation.
 (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
-  (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv")
+  (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
          (cond
 	   [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
 	    (const_string "rne")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
new file mode 100644
index 0000000..893fa86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat64m2_t
+test_vfwmul_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfwmul_vv_f64m2_rm (op1, op2, 0, vl);
+}
+
+vfloat64m2_t
+test_vfwmul_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			   size_t vl) {
+  return __riscv_vfwmul_vv_f64m2_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat64m2_t
+test_vfwmul_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfwmul_vf_f64m2_rm (op1, op2, 2, vl);
+}
+
+vfloat64m2_t
+test_vfwmul_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			   size_t vl) {
+  return __riscv_vfwmul_vf_f64m2_rm_m (mask, op1, op2, 3, vl);
+}
+
+vfloat64m2_t
+test_vfwmul_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfwmul_vv_f64m2 (op1, op2, vl);
+}
+
+vfloat64m2_t
+test_vfwmul_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			size_t vl) {
+  return __riscv_vfwmul_vv_f64m2_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwmul\.[vw][vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */