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2023-12-13attribs: Fix valgrind failures on -Wno-attributes* tests [PR112953]Jakub Jelinek1-1/+1
The r14-6076 change changed the allocation of attribute tables from table = new attribute_spec[2]; to table = new attribute_spec { ... }; with ignored_attributes_table.safe_push (table); later in both cases, but didn't change the corresponding delete in free_attr_data, which means valgrind is unhappy about that: FAIL: c-c++-common/Wno-attributes-2.c -Wc++-compat (test for excess errors) Excess errors: ==974681== Mismatched free() / delete / delete [] ==974681== at 0x484965B: operator delete[](void*) (vg_replace_malloc.c:1103) ==974681== by 0x707434: free_attr_data() (attribs.cc:318) ==974681== by 0xCFF8A4: compile_file() (toplev.cc:454) ==974681== by 0x704D23: do_compile (toplev.cc:2150) ==974681== by 0x704D23: toplev::main(int, char**) (toplev.cc:2306) ==974681== by 0x7064BA: main (main.cc:39) ==974681== Address 0x51dffa0 is 0 bytes inside a block of size 40 alloc'd ==974681== at 0x4845FF5: operator new(unsigned long) (vg_replace_malloc.c:422) ==974681== by 0x70A040: handle_ignored_attributes_option(vec<char*, va_heap, vl_ptr>*) (attribs.cc:301) ==974681== by 0x7FA089: handle_pragma_diagnostic_impl<false, false> (c-pragma.cc:934) ==974681== by 0x7FA089: handle_pragma_diagnostic(cpp_reader*) (c-pragma.cc:1028) ==974681== by 0x75814F: c_parser_pragma(c_parser*, pragma_context, bool*) (c-parser.cc:14707) ==974681== by 0x784A85: c_parser_external_declaration(c_parser*) (c-parser.cc:2027) ==974681== by 0x785223: c_parser_translation_unit (c-parser.cc:1900) ==974681== by 0x785223: c_parse_file() (c-parser.cc:26713) ==974681== by 0x7F6331: c_common_parse_file() (c-opts.cc:1301) ==974681== by 0xCFF87D: compile_file() (toplev.cc:446) ==974681== by 0x704D23: toplev::main(int, char**) (toplev.cc:2306) ==974681== by 0x7064BA: main (main.cc:39) 2023-12-13 Jakub Jelinek <jakub@redhat.com> PR middle-end/112953 * attribs.cc (free_attr_data): Use delete x rather than delete[] x.
2023-12-13i386: Fix ICE on __builtin_ia32_pabsd128 without lhs [PR112962]Jakub Jelinek2-2/+19
The following patch fixes ICE on the testcase in similar way to how other folded builtins are handled in ix86_gimple_fold_builtin when they don't have a lhs; these builtins are const or pure, so normally DCE would remove them later, but with -O0 that isn't guaranteed to happen, and during expansion if they are marked TREE_SIDE_EFFECTS it might still be attempted to be expanded. This removes them right away during the folding. Initially I wanted to also change all gsi_replace last args in that function to true, but Andrew pointed to PR107209, so I've kept them as is. 2023-12-13 Jakub Jelinek <jakub@redhat.com> PR target/112962 * config/i386/i386.cc (ix86_gimple_fold_builtin): For shifts and abs without lhs replace with nop. * gcc.target/i386/pr112962.c: New test.
2023-12-13Avoid losing MEM_REF offset in MEM_EXPR adjustment for stack slot sharingRichard Biener1-3/+9
When investigating PR111591 with respect to TBAA and stack slot sharing I noticed we're eventually scrapping a [TARGET_]MEM_REF offset when rewriting the VAR_DECL base of the MEM_EXPR to use a pointer to the partition instead. The following makes sure to preserve that. * emit-rtl.cc (set_mem_attributes_minus_bitpos): Preserve the offset when rewriting an exising MEM_REF base for stack slot sharing.
2023-12-13tree-optimization/112991 - re-do PR112961 fixRichard Biener5-25/+47
The following does away with the fake edge adding as in the original PR112961 fix and instead exposes handling of entry PHIs as additional parameter of the region VN run. PR tree-optimization/112991 PR tree-optimization/112961 * tree-ssa-sccvn.h (do_rpo_vn): Add skip_entry_phis argument. * tree-ssa-sccvn.cc (do_rpo_vn): Likewise. (do_rpo_vn_1): Likewise, merge with auto-processing. (run_rpo_vn): Adjust. (pass_fre::execute): Likewise. * tree-if-conv.cc (tree_if_conversion): Revert last change. Value-number latch block but disable value-numbering of entry PHIs. * tree-ssa-uninit.cc (execute_early_warn_uninitialized): Adjust. * gcc.dg/torture/pr112991.c: New testcase.
2023-12-13tree-optimization/112990 - unsupported VEC_PERM from match patternRichard Biener1-0/+2
The following avoids creating an unsupported VEC_PERM after vector lowering from the pattern merging a bit-insert from a bit-field-ref to a VEC_PERM. For the already existing s390 testcase we get TImode vectors which later ICE during attempted expansion of a vec_perm_const. PR tree-optimization/112990 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Restrict to vector modes after lowering.
2023-12-13middle-end/111591 - explain why TBAA doesn't need adjustmentRichard Biener1-1/+7
While tidying the prototype patch I've done for the reduced testcase in PR111591 and in that process trying to produce a testcase that is miscompiled by stack slot coalescing and the TBAA info that remains un-altered I've realized we do not need to adjust TBAA info. The following documents this in the place we adjust points-to info which we do need to adjust. PR middle-end/111591 * cfgexpand.cc (update_alias_info_with_stack_vars): Document why not adjusting TBAA info on accesses is OK.
2023-12-13multiflags: fix doc warning properlyAlexandre Oliva1-2/+2
Rather than a dubious fix for a dubious warning, namely adding a period after a parenthesized @xref because the warning demands it, use @pxref that is meant for exactly this case. Thanks to Joseph Myers for introducing me to it. for gcc/ChangeLog * doc/invoke.texi (multiflags): Drop extraneous period, use @pxref instead.
2023-12-13aarch64: Implement the ACLE instruction/data prefetch functions.Victor Do Nascimento5-0/+290
Implement the ACLE data and instruction prefetch functions[1] with the following signatures: 1. Data prefetch intrinsics: ---------------------------- void __pldx (/*constant*/ unsigned int /*access_kind*/, /*constant*/ unsigned int /*cache_level*/, /*constant*/ unsigned int /*retention_policy*/, void const volatile *addr); void __pld (void const volatile *addr); 2. Instruction prefetch intrinsics: ----------------------------------- void __plix (/*constant*/ unsigned int /*cache_level*/, /*constant*/ unsigned int /*retention_policy*/, void const volatile *addr); void __pli (void const volatile *addr); `__pldx' affords the programmer more fine-grained control over the data prefetch behaviour than the analogous GCC builtin `__builtin_prefetch', and allows access to the "SLC" cache level. While `__builtin_prefetch' chooses both cache-level and retention policy automatically via the optional `locality' parameter, `__pldx' expects 2 (mandatory) arguments to explicitly define the desired cache-level and retention policies. `__plix' on the other hand, generates a code prefetch instruction and so extends functionality on aarch64 targets beyond that which is exposed by `builtin_prefetch'. `__pld' and `__pli' do prefetch of data and instructions, respectively, using default values for both cache-level and retention policies. Bootstrapped and tested on aarch64-none-linux-gnu. [1] https://arm-software.github.io/acle/main/acle.html#memory-prefetch-intrinsics gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc: (AARCH64_PLD): New enum aarch64_builtins entry. (AARCH64_PLDX): Likewise. (AARCH64_PLI): Likewise. (AARCH64_PLIX): Likewise. (aarch64_init_prefetch_builtin): New. (aarch64_general_init_builtins): Call prefetch init function. (aarch64_expand_prefetch_builtin): New. (aarch64_general_expand_builtin): Add prefetch expansion. (require_const_argument): New. * config/aarch64/aarch64.md (UNSPEC_PLDX): New. (aarch64_pldx): Likewise. * config/aarch64/arm_acle.h (__pld): Likewise. (__pli): Likewise. (__plix): Likewise. (__pldx): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/builtin_pld_pli.c: New. * gcc.target/aarch64/builtin_pld_pli_illegal.c: New.
2023-12-12range: Workaround different type precision between _Float128 and long double ↵Kewen Lin1-2/+8
[PR112788] As PR112788 shows, on rs6000 with -mabi=ieeelongdouble type _Float128 has the different type precision (128) from that (127) of type long double, but actually they has the same underlying mode, so they have the same precision as the mode indicates the same real type format ieee_quad_format. It's not sensible to have such two types which have the same mode but different type precisions, some fix attempt was posted at [1]. As the discussion there, there are some historical reasons and practical issues. Considering we passed stage 1 and it also affected the build as reported, this patch is trying to temporarily workaround it. I thought to introduce a hookpod but that seems a bit overkill, assuming scalar float type with the same mode should have the same precision looks sensible. [1] https://inbox.sourceware.org/gcc-patches/718677e7-614d-7977-312d-05a75e1fd5b4@linux.ibm.com/ PR tree-optimization/112788 gcc/ChangeLog: * value-range.h (range_compatible_p): Workaround same type mode but different type precision issue for rs6000 scalar float types _Float128 and long double.
2023-12-13i386: Fix PR110790 testcaseHaochen Jiang1-1/+1
gcc/testsuite/ChangeLog: * gcc.target/i386/pr110790-2.c: Change scan-assembler from shrq to shr\[qx\].
2023-12-13rs6000: using pli for constant splittingJiufu Guo2-0/+16
For constant building e.g. r120=0x66666666, which does not fit 'li or lis', 'pli' is used to build this constant via 'emit_move_insn'. While for a complicated constant, e.g. 0x6666666666666666ULL, when using 'rs6000_emit_set_long_const' to split the constant recursively, it fails to use 'pli' to build the half part constant: 0x66666666. 'rs6000_emit_set_long_const' could be updated to use 'pli' to build half part of the constant when necessary. For example: 0x6666666666666666ULL, "pli 3,1717986918; rldimi 3,3,32,0" can be used. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add code to use pli for 34bit constant. gcc/testsuite/ChangeLog: * gcc.target/powerpc/const-build-1.c: New test.
2023-12-13rs6000: accurate num_insns_constant_gprJiufu Guo1-138/+146
Trunk gcc supports more constants to be built via two instructions: e.g. "li/lis; xori/xoris/rldicl/rldicr/rldic". And then num_insns_constant should also be updated. Function "rs6000_emit_set_long_const" is used to build complicated constants; and "num_insns_constant_gpr" is used to compute 'how many instructions are needed" to build the constant. So, these two functions should be aligned. The idea of this patch is: to reuse "rs6000_emit_set_long_const" to compute/record the instruction number(when computing the insn_num, then do not emit instructions). gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add new parameter to record number of instructions to build the constant. (num_insns_constant_gpr): Call rs6000_emit_set_long_const to compute num_insn.
2023-12-13Daily bump.GCC Administrator10-1/+690
2023-12-12c++: class hotness attribute and member templateJason Merrill2-7/+15
The FUNCTION_DECL check ignored member function templates. gcc/cp/ChangeLog: * class.cc (propagate_class_warmth_attribute): Handle member templates. gcc/testsuite/ChangeLog: * g++.dg/ext/attr-hotness.C: Add member templates. Co-authored-by: Jason Xu <rxu@DRWHoldings.com>
2023-12-13RISC-V: Apply vla vs. vls mode heuristic vector COST modelJuzhe-Zhong17-4/+408
This patch apply vla vs. vls mode heuristic which can fixes the following FAILs: FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize scan-assembler-not vset FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize scan-assembler-times li\\s+[a-x0-9]+,0\\s+ret 2 The root cause of this FAIL is we failed to pick VLS mode for the vectorization. Before this patch: foo2: addi sp,sp,-208 addi a2,sp,64 addi a5,sp,128 lui a6,%hi(.LANCHOR0) sd ra,200(sp) addi a6,a6,%lo(.LANCHOR0) mv a0,a2 mv a1,a5 li a3,16 mv a4,sp vsetivli zero,8,e64,m8,ta,ma vle64.v v8,0(a6) vse64.v v8,0(a2) vse64.v v8,0(a5) .L4: vsetvli a5,a3,e32,m1,ta,ma slli a2,a5,2 vle32.v v2,0(a1) vle32.v v1,0(a0) sub a3,a3,a5 vadd.vv v1,v1,v2 vse32.v v1,0(a4) add a1,a1,a2 add a0,a0,a2 add a4,a4,a2 bne a3,zero,.L4 lw a4,128(sp) lw a5,64(sp) addw a5,a5,a4 lw a4,0(sp) bne a4,a5,.L5 lw a4,132(sp) lw a5,68(sp) addw a5,a5,a4 lw a4,4(sp) bne a4,a5,.L5 lw a4,136(sp) lw a5,72(sp) addw a5,a5,a4 lw a4,8(sp) bne a4,a5,.L5 lw a4,140(sp) lw a5,76(sp) addw a5,a5,a4 lw a4,12(sp) bne a4,a5,.L5 lw a4,144(sp) lw a5,80(sp) addw a5,a5,a4 lw a4,16(sp) bne a4,a5,.L5 lw a4,148(sp) lw a5,84(sp) addw a5,a5,a4 lw a4,20(sp) bne a4,a5,.L5 lw a4,152(sp) lw a5,88(sp) addw a5,a5,a4 lw a4,24(sp) bne a4,a5,.L5 lw a4,156(sp) lw a5,92(sp) addw a5,a5,a4 lw a4,28(sp) bne a4,a5,.L5 lw a4,160(sp) lw a5,96(sp) addw a5,a5,a4 lw a4,32(sp) bne a4,a5,.L5 lw a4,164(sp) lw a5,100(sp) addw a5,a5,a4 lw a4,36(sp) bne a4,a5,.L5 lw a4,168(sp) lw a5,104(sp) addw a5,a5,a4 lw a4,40(sp) bne a4,a5,.L5 lw a4,172(sp) lw a5,108(sp) addw a5,a5,a4 lw a4,44(sp) bne a4,a5,.L5 lw a4,176(sp) lw a5,112(sp) addw a5,a5,a4 lw a4,48(sp) bne a4,a5,.L5 lw a4,180(sp) lw a5,116(sp) addw a5,a5,a4 lw a4,52(sp) bne a4,a5,.L5 lw a4,184(sp) lw a5,120(sp) addw a5,a5,a4 lw a4,56(sp) bne a4,a5,.L5 lw a4,188(sp) lw a5,124(sp) addw a5,a5,a4 lw a4,60(sp) bne a4,a5,.L5 ld ra,200(sp) li a0,0 addi sp,sp,208 jr ra .L5: call abort After this patch: li a0,0 ret The heuristic leverage ARM SVE and fully tested and confirm we have same behavior as ARM SVE GCC and RVV Clang. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo): New function. (costs::record_potential_vls_unrolling): Ditto. (costs::prefer_unrolled_loop): Ditto. (costs::better_main_loop_than_p): Ditto. (costs::add_stmt_cost): Ditto. * config/riscv/riscv-vector-costs.h (enum cost_type_enum): New enum. * config/riscv/t-riscv: Add new include files. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr111313.c: Adapt test. * gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-1.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-8.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c: New test.
2023-12-13RISC-V: Refactor Dynamic LMUL codesJuzhe-Zhong31-109/+88
This patch refactor dynamic LMUL to remove this following variable: static hash_map<class loop *, autovec_info> loop_autovec_infos; which will keep growing on-the-fly. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (get_current_lmul): Remove it. (compute_estimated_lmul): New function. (costs::costs): Refactor. (costs::preferred_new_lmul_p): Ditto. (preferred_new_lmul_p): Ditto. (costs::better_main_loop_than_p): Ditto. * config/riscv/riscv-vector-costs.h (struct autovec_info): Remove it. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-4.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/pr111848.c: Adapt test.
2023-12-12testsuite: Add testcase for already fixed PR [PR112822]Peter Bergner1-0/+369
Adding a testcase for PR112822 to ensure we won't regress. 2023-12-12 Peter Bergner <bergner@linux.ibm.com> gcc/testsuite/ PR tree-optimization/112822 * g++.dg/pr112822.C: New test.
2023-12-12libstdc++: Fix std::format("{}", 'c')Jonathan Wakely3-0/+68
When I added a fast path for std::format("{}", x) in r14-5587-g41a5ea4cab2c59 I forgot to handle char separately from other integral types. That caused std::format("{}", 'c') to return "99" instead of "c". libstdc++-v3/ChangeLog: * include/std/format (__do_vformat_to): Handle char separately from other integral types. * testsuite/std/format/functions/format.cc: Check for expected output for char and bool arguments. * testsuite/std/format/string.cc: Check that 0 filling is rejected for character and string formats.
2023-12-12libstdc++: Fix std::format output of %C for negative yearsJonathan Wakely2-4/+12
During discussion of LWG 4022 I noticed that we do not correctly implement floored division for the century. We were just truncating towards zero, rather than applying the floor function. For negative values that rounds the wrong way. libstdc++-v3/ChangeLog: * include/bits/chrono_io.h (__formatter_chrono::_M_C_y_Y): Fix rounding for negative centuries. * testsuite/std/time/year/io.cc: Check %C for negative years.
2023-12-12libstdc++: Remove redundant -std flags from MakefileJonathan Wakely2-8/+8
In r14-4060-gc4baeaecbbf7d0 I moved some files from src/c++98 to src/c++11 but I didn't remove the redundant -std=gnu++11 flags for those files. The flags aren't needed now, because AM_CXXFLAGS for that directory already uses -std=gnu++11. This removes them. libstdc++-v3/ChangeLog: * src/c++11/Makefile.am: Remove redundant -std=gnu++11 flags. * src/c++11/Makefile.in: Regenerate.
2023-12-12SRA: Force gimple operand in an additional corner case (PR 112822)Martin Jambor1-3/+7
PR 112822 revealed a corner case in load_assign_lhs_subreplacements where it creates invalid gimple: an assignment where on the LHS there is a complex variable which however is not a gimple register because it has partial defs and on the right hand side there is a VIEW_CONVERT_EXPR. This patch invokes force_gimple_operand_gsi on such statements (like it already does when both sides of a generated assignment have partial definitions. gcc/ChangeLog: 2023-12-12 Martin Jambor <mjambor@suse.cz> PR tree-optimization/112822 * tree-sra.cc (load_assign_lhs_subreplacements): Invoke force_gimple_operand_gsi also when LHS has partial stores and RHS is a VIEW_CONVERT_EXPR.
2023-12-12PR modula2/112984 Compiling program with -Wpedantic shows warning in librariesGaius Mulley40-53/+93
This patch tidies up the library modules so that -Wpedantic does not generate any warnings (apart from two procedures with legitimate infinite loops). gcc/m2/ChangeLog: PR modula2/112984 * gm2-libs-coroutines/SYSTEM.mod: Remove redundant import of memcpy. * gm2-libs-iso/ClientSocket.mod: Remove redundant import of IOConsts. * gm2-libs-iso/IOChan.mod: Remove redundant import of IOConsts. * gm2-libs-iso/IOLink.mod: Remove redundant import of IOChan and SYSTEM. * gm2-libs-iso/IOResult.mod: Remove redundant import of IOChan. * gm2-libs-iso/LongIO.mod: Remove redundant import of writeString. * gm2-libs-iso/LongWholeIO.mod: Remove redundant import of IOChan. * gm2-libs-iso/M2RTS.mod: Remove redundant import of ADDRESS. * gm2-libs-iso/MemStream.mod: Remove redundant import of ADDRESS. * gm2-libs-iso/RTdata.mod: Remove redundant import of DeviceTablePtr. * gm2-libs-iso/RTfio.mod: Remove redundant import of DeviceTablePtr. * gm2-libs-iso/RTgen.mod: Remove redundant import of DeviceTablePtr. * gm2-libs-iso/RealIO.mod: Remove redundant import of writeString. * gm2-libs-iso/RndFile.mod: Remove redundant import of SYSTEM. * gm2-libs-iso/SYSTEM.mod: Remove redundant import of memcpy. * gm2-libs-iso/ShortWholeIO.mod: Remove redundant import of IOConsts. * gm2-libs-iso/TextIO.mod: Remove redundant import of IOChan. * gm2-libs-iso/TextUtil.mod: Remove redundant import of IOChan. * gm2-libs-iso/WholeIO.mod: Remove redundant import of IOChan. * gm2-libs-log/BitByteOps.mod: Remove redundant import of BYTE. * gm2-libs-log/FileSystem.mod: Remove redundant import of BYTE and ADDRESS. * gm2-libs-log/InOut.mod: Remove redundant import of String. * gm2-libs-log/RealConversions.mod: Remove redundant import of StringToLongreal. * gm2-libs/FIO.mod: Remove redundant import of SIZE. * gm2-libs/FormatStrings.mod: Remove redundant import of String and ConCatChar. * gm2-libs/IO.mod: Remove redundant import of SIZE. * gm2-libs/Indexing.mod: Remove redundant import of ADDRESS. * gm2-libs/M2Dependent.mod: Remove redundant import of SIZE. * gm2-libs/M2RTS.mod: Remove redundant import of ADDRESS. * gm2-libs/OptLib.mod: Remove redundant import of DynamicStrings. * gm2-libs/SYSTEM.mod: Remove redundant import of memcpy. * gm2-libs/StringConvert.mod: Remove redundant import of String. libgm2/ChangeLog: * libm2iso/Makefile.am (libm2iso_la_M2FLAGS): Added line breaks. * libm2iso/Makefile.in: Regenerate. * libm2log/Makefile.am (libm2log_la_M2FLAGS): Added line breaks. * libm2log/Makefile.in: Regenerate. * libm2pim/Makefile.am (libm2pim_la_M2FLAGS): Added line breaks. * libm2pim/Makefile.in: Regenerate. gcc/testsuite/ChangeLog: PR modula2/112984 * gm2/switches/pedantic/pass/hello.mod: New test. * gm2/switches/pedantic/pass/switches-pedantic-pass.exp: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-12-13LoongArch: testsuite: Remove XFAIL in vect-ftint-no-inexact.cXi Ruoyao1-2/+1
After r14-6455 this no longer fails. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-ftint-no-inexact.c (xfail): Remove.
2023-12-12testsuite: fix is_nothrow_default_constructible8.CJason Merrill1-1/+1
This testcase uses variable templates, a C++14 feature. gcc/testsuite/ChangeLog: * g++.dg/ext/is_nothrow_constructible8.C: Require C++14.
2023-12-12tree: add to clobber_kindJason Merrill10-24/+52
In discussion of PR71093 it came up that more clobber_kind options would be useful within the C++ front-end. gcc/ChangeLog: * tree-core.h (enum clobber_kind): Rename CLOBBER_EOL to CLOBBER_STORAGE_END. Add CLOBBER_STORAGE_BEGIN, CLOBBER_OBJECT_BEGIN, CLOBBER_OBJECT_END. * gimple-lower-bitint.cc * gimple-ssa-warn-access.cc * gimplify.cc * tree-inline.cc * tree-ssa-ccp.cc: Adjust for rename. * tree-pretty-print.cc: And handle new values. gcc/cp/ChangeLog: * call.cc (build_trivial_dtor_call): Use CLOBBER_OBJECT_END. * decl.cc (build_clobber_this): Take clobber_kind argument. (start_preparsed_function): Pass CLOBBER_OBJECT_BEGIN. (begin_destructor_body): Pass CLOBBER_OBJECT_END. gcc/testsuite/ChangeLog: * gcc.dg/pr87052.c: Adjust expected CLOBBER output. Co-authored-by: Nathaniel Shead <nathanieloshead@gmail.com>
2023-12-12aarch64,arm: Fix branch-protection= parsingSzabolcs Nagy7-168/+116
Refactor the parsing to have a single API and fix a few parsing issues: - Different handling of "bti+none" and "none+bti": these should be rejected because "none" can only appear alone. - Accepted empty strings such as "bti++pac-ret" or "bti+", this bug was caused by using strtok_r. - Memory got leaked (str_root was never freed). And two buffers got allocated when one is enough. The callbacks now have no failure mode, only parsing can fail and all failures are handled locally. The "-mbranch-protection=" vs "target("branch-protection=")" difference in the error message is handled by a separate argument to aarch_validate_mbranch_protection. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_override_options): Update. (aarch64_handle_attr_branch_protection): Update. * config/arm/aarch-common-protos.h (aarch_parse_branch_protection): Remove. (aarch_validate_mbranch_protection): Add new argument. * config/arm/aarch-common.cc (aarch_handle_no_branch_protection): Update. (aarch_handle_standard_branch_protection): Update. (aarch_handle_pac_ret_protection): Update. (aarch_handle_pac_ret_leaf): Update. (aarch_handle_pac_ret_b_key): Update. (aarch_handle_bti_protection): Update. (aarch_parse_branch_protection): Remove. (next_tok): New. (aarch_validate_mbranch_protection): Rewrite. * config/arm/aarch-common.h (struct aarch_branch_protect_type): Add field "alone". * config/arm/arm.cc (arm_configure_build_target): Update. gcc/testsuite/ChangeLog: * gcc.target/aarch64/branch-protection-attr.c: Update. * gcc.target/aarch64/branch-protection-option.c: Update.
2023-12-12aarch64,arm: Remove accepted_branch_protection_stringSzabolcs Nagy3-27/+1
On aarch64 this caused ICE with pragma push_options since commit ae54c1b09963779c5c3914782324ff48af32e2f1 Author: Wilco Dijkstra <wilco.dijkstra@arm.com> CommitDate: 2022-06-01 18:13:57 +0100 AArch64: Cleanup option processing code The failure is at pop_options: internal compiler error: ‘global_options’ are modified in local context On arm the variable was unused. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_override_options_after_change_1): Do not override branch_protection options. (aarch64_override_options): Remove accepted_branch_protection_string. * config/arm/aarch-common.cc (BRANCH_PROTECT_STR_MAX): Remove. (aarch_parse_branch_protection): Remove accepted_branch_protection_string. * config/arm/arm.cc: Likewise.
2023-12-12tree-optimization/112736 - avoid overread with non-grouped SLP loadRichard Biener2-19/+100
The following aovids over/under-read of storage when vectorizing a non-grouped load with SLP. Instead of forcing peeling for gaps use a smaller load for the last vector which might access excess elements. This builds upon the existing optimization avoiding peeling for gaps, generalizing it to all gap widths leaving a power-of-two remaining number of elements (but it doesn't replace or improve that particular case at this point). I wonder if the poly relational compares I set up are good enough to guarantee /* remain should now be > 0 and < nunits. */. There is existing test coverage that runs into /* DR will be unused. */ always when the gap is wider than nunits. Compared to the existing gap == nunits/2 case this only adjusts the load that will cause the overrun at the end, not every load. Apart from the poly relational compares it should reliably cover these cases but I'll leave it for stage1 to remove. PR tree-optimization/112736 * tree-vect-stmts.cc (vectorizable_load): Extend optimization to avoid peeling for gaps to handle single-element non-groups we now allow with SLP. * gcc.dg/torture/pr112736.c: New testcase.
2023-12-12ipa/92606 - properly handle no_icf attribute for variablesRichard Biener3-2/+9
The following adds no_icf handling for variables where the attribute was rejected. It also fixes the check for no_icf by checking both the source and the targets decl. PR ipa/92606 gcc/c-family/ * c-attribs.cc (handle_noicf_attribute): Also allow the attribute on global variables. gcc/ * ipa-icf.cc (sem_item_optimizer::merge_classes): Check both source and alias for the no_icf attribute. * doc/extend.texi (no_icf): Document variable attribute.
2023-12-12tree-optimization/112961 - include latch in if-conversion CSERichard Biener2-2/+24
The following makes sure to also process the (empty) latch when performing CSE on the if-converted loop body. That's important to get all uses of copies propagated out on the backedge as well. To avoid CSE on the PHI nodes itself which is prohibitive (see PR90402) this temporarily adds a fake entry edge to the loop. PR tree-optimization/112961 * tree-if-conv.cc (tree_if_conversion): Instead of excluding the latch block from VN, add a fake entry edge. * g++.dg/vect/pr112961.cc: New testcase.
2023-12-12testsuite: Fix up test directive syntax errorsJakub Jelinek3-9/+9
I've noticed +ERROR: gcc.dg/gomp/pr87887-1.c: syntax error in target selector ".-4" for " dg-warning 13 "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr87887-1.c: syntax error in target selector ".-4" for " dg-warning 13 "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr89246-1.c: syntax error in target selector ".-4" for " dg-warning 11 "unsupported argument type ‘__int128’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr89246-1.c: syntax error in target selector ".-4" for " dg-warning 11 "unsupported argument type ‘__int128’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/simd-clones-2.c: unmatched open quote in list for " dg-final 19 { scan-tree-dump "_ZGVnN2ua32vl_setArray" "optimized { target aarch64*-*-* } } " +ERROR: gcc.dg/gomp/simd-clones-2.c: unmatched open quote in list for " dg-final 19 { scan-tree-dump "_ZGVnN2ua32vl_setArray" "optimized { target aarch64*-*-* } } " regressions. The following patch fixes those. 2023-12-12 Jakub Jelinek <jakub@redhat.com> * gcc.dg/gomp/pr87887-1.c: Add missing comment argument to dg-warning. * gcc.dg/gomp/pr89246-1.c: Likewise. * gcc.dg/gomp/simd-clones-2.c: Add missing " after dump name.
2023-12-12Only allow (int)trunc(x) to (int)x simplification with ↵Xi Ruoyao2-1/+14
-ffp-int-builtin-inexact [PR107723] With -fno-fp-int-builtin-inexact, trunc is not allowed to raise FE_INEXACT and it should produce an integral result (if the input is not NaN or Inf). Thus FE_INEXACT should not be raised. But (int)x may raise FE_INEXACT when x is a non-integer, non-NaN, and non-Inf value. C23 recommends to do so in a footnote. Thus we should not simplify (int)trunc(x) to (int)x if -fno-fp-int-builtin-inexact is in-effect. gcc/ChangeLog: PR middle-end/107723 * convert.cc (convert_to_integer_1) [case BUILT_IN_TRUNC]: Break early if !flag_fp_int_builtin_inexact and flag_trapping_math. gcc/testsuite/ChangeLog: PR middle-end/107723 * gcc.dg/torture/builtin-fp-int-inexact-trunc.c: New test.
2023-12-12aarch64: Add dg-options to prfm_imm_offset_2.cRichard Sandiford1-0/+1
gcc/testsuite/ * gcc.target/aarch64/prfm_imm_offset_2.c: Add dg-options.
2023-12-12Add myself to write after approvalPaul Iannetta1-0/+1
ChangeLog: * MAINTAINERS: Add myself to write after approval Signed-off-by: Paul Iannetta <piannetta@kalrayinc.com>
2023-12-12RISC-V: Disable RVV VCOMPRESS avl propagationPan Li2-10/+61
This patch would like to disable the avl propagation for the follow reasons. According to the ISA, the first vl elements of vector register group vs2 should be extracted and packed for vcompress. And the highest element of vs2 vector may be touched by the mask, which may be eliminated by avl propagation. For example, given original vl = 4 here. We have: v0 = 0b1000 v1 = {0x1, 0x2, 0x3, 0x4} v2 = {0x5, 0x6, 0x7, 0x8} Then: vcompress v1, v2, v0 (avl = 4), v1 = {0x8, 0x2, 0x3, 0x4}. <== Correct. vcompress v1, v2, v0 (avl = 2), v1 will be unchanged. <== Wrong. Finally, we cannot propagate avl of vcompress because it may has senmatics change to the result. This patch also fix the failure of gcc.c-torture/execute/990128-1.c for the following configurations. riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Disable the avl propogation for the vcompress. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-12-12libquadmath: Restore linking against -lm on most targets [PR112963]Jakub Jelinek3-2/+32
The r14-4825 change added AC_CHECK_LIBM to libquadmath configure.ac and replaced unconditional linking with -lm with linking with $(LIBM) determined by that. Unfortunately that broke bare metal targets because AC_CHECK_LIBM attempts to link against -lm and this was after (unconditional) GCC_NO_EXECUTABLES. Then r14-4863 partially reverted that change (no longer AC_CHECK_LIBM), but didn't revert the Makefile.am change of -lm to $(LIBM), which had the effect that libquadmath is not linked against -lm on any arch. That is a serious problem though e.g. on Linux, because libquadmath calls a few libm entrypoints and e.g. on powerpc64le the underlinking can cause crashes in IFUNC resolvers of libm. Instead of adding further reversion of the r14-4825 commit and use -lm unconditionally again, this patch adds an AC_CHECK_LIBM like substitutions with the *-ncr-sysv4.3* target handling removed (I think we don't support such targets, especially not in libquadmath) and with the default case replaced by simple using -lm. That is something in between using -lm unconditionally and what AC_CHECK_LIBM does if it would work on bare metal - we know from GCC 13 and earlier that we can link -lm on all targets libquadmath is built for, and just white list a couple of targets which we know don't have separate -lm and don't want to link against that (like Darwin, Cygwin, ...). 2023-12-12 Jakub Jelinek <jakub@redhat.com> PR libquadmath/112963 * configure.ac (LIBM): Readd AC_CHECK_LIBM-like check without doing AC_CHECK_LIB in it. * configure: Regenerated. * Makefile.in: Regenerated.
2023-12-12LoongArch: Fix warnings building libgccXi Ruoyao1-10/+10
We are excluding loongarch-opts.h from target libraries, but now struct loongarch_target and gcc_options are not declared in the target libraries, causing: In file included from ../.././gcc/options.h:8, from ../.././gcc/tm.h:49, from ../../../gcc/libgcc/fixed-bit.c:48: ../../../gcc/libgcc/../gcc/config/loongarch/loongarch-opts.h:57:41: warning: 'struct gcc_options' declared inside parameter list will not be visible outside of this definition or declaration 57 | struct gcc_options *opts, | ^~~~~~~~~~~ So exclude the declarations referring to the C++ structs as well. gcc/ChangeLog: * config/loongarch/loongarch-opts.h (la_target): Move into #if for loongarch-def.h. (loongarch_init_target): Likewise. (loongarch_config_target): Likewise. (loongarch_update_gcc_opt_status): Likewise.
2023-12-12LoongArch: Allow -mcmodel=extreme and model attribute with ↵Xi Ruoyao6-11/+44
-mexplicit-relocs=auto There seems no real reason to require -mexplicit-relocs=always for -mcmodel=extreme or model attribute. As the linker does not know how to relax a 3-operand la.local or la.global pseudo instruction, just emit explicit relocs for SYMBOL_PCREL64, and under TARGET_CMODEL_EXTREME also SYMBOL_GOT_DISP. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p): Return true for SYMBOL_PCREL64. Return true for SYMBOL_GOT_DISP if TARGET_CMODEL_EXTREME. (loongarch_split_symbol): Check for la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE instead of TARGET_EXPLICIT_RELOCS. (loongarch_print_operand_reloc): Likewise. (loongarch_option_override_internal): Likewise. (loongarch_handle_model_attribute): Likewise. * doc/invoke.texi (-mcmodel=extreme): Update the compatibility between it and -mexplicit-relocs=. gcc/testsuite/ChangeLog: * gcc.target/loongarch/attr-model-3.c: New test. * gcc.target/loongarch/attr-model-4.c: New test. * gcc.target/loongarch/func-call-extreme-3.c: New test. * gcc.target/loongarch/func-call-extreme-4.c: New test.
2023-12-12tree-optimization/112939 - VN PHI visiting and -ftrivial-auto-var-initRichard Biener2-1/+26
The following builds upon the last fix, making sure we only value-number to visited (un-)defs, otherwise prefer .VN_TOP. PR tree-optimization/112939 * tree-ssa-sccvn.cc (visit_phi): When all args are undefined make sure we end up with a value that was visited, otherwise fall back to .VN_TOP. * gcc.dg/pr112939.c: New testcase.
2023-12-12Don't assume it's AVX_U128_CLEAN after call_insn whose ↵liuhongt3-3/+78
abi.mode_clobber(V4DImode) deosn't contains all SSE_REGS. If the function desn't clobber any sse registers or only clobber 128-bit part, then vzeroupper isn't issued before the function exit. the status not CLEAN but ANY after the function. Also for sibling_call, it's safe to issue an vzeroupper. Also there could be missing vzeroupper since there's no mode_exit for sibling_call_p. gcc/ChangeLog: PR target/112891 * config/i386/i386.cc (ix86_avx_u128_mode_after): Return AVX_U128_ANY if callee_abi doesn't clobber all_sse_regs to align with ix86_avx_u128_mode_needed. (ix86_avx_u128_mode_needed): Return AVX_U128_ClEAN for sibling_call. gcc/testsuite/ChangeLog: * gcc.target/i386/pr112891.c: New test. * gcc.target/i386/pr112891-2.c: New test.
2023-12-12untyped calls: enable target switching [PR112334]Alexandre Oliva2-2/+21
The computation of apply_args_size and apply_result_size is saved in a static variable, so that the corresponding _mode arrays are initialized only once. That is not compatible with switchable targets, and ARM's arm_set_current_function, by saving and restoring target globals, exercises this problem with a testcase such as that in the PR, in which more than one function in the translation unit calls __builtin_apply or __builtin_return, respectively. This patch moves the _size statics into the target_builtins array, with a bit of ugliness over _plus_one so that zero initialization of the struct does the right thing. for gcc/ChangeLog PR target/112334 * builtins.h (target_builtins): Add fields for apply_args_size and apply_result_size. * builtins.cc (apply_args_size, apply_result_size): Cache results in fields rather than in static variables. (get_apply_args_size, set_apply_args_size): New. (get_apply_result_size, set_apply_result_size): New.
2023-12-12i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943]Hongyu Wang2-4/+71
The ashl/lshr/ashr expanders calls ix86_expand_binary_operator, while they will be called for some post-reload split, and TARGET_APX_NDD is required for these calls to avoid force-load to memory at postreload stage. gcc/ChangeLog: PR target/112943 * config/i386/i386.md (ashl<mode>3): Add TARGET_APX_NDD to ix86_expand_binary_operator call. (<insn><mode>3): Likewise for rshift. (<insn>di3): Likewise for DImode rotate. (<insn><mode>3): Likewise for SWI124 rotate. gcc/testsuite/ChangeLog: PR target/112943 * gcc.target/i386/pr112943.c: New test.
2023-12-11analyzer: add more test coverage for tainted modulusDavid Malcolm2-0/+76
Add more test coverage for r14-6349-g0bef72539e585d. gcc/testsuite/ChangeLog: * gcc.dg/plugin/plugin.exp: Add taint-modulus.c to analyzer_kernel_plugin.c tests. * gcc.dg/plugin/taint-modulus.c: New test. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-12-12MAINTAINERS: Update my email addressFeng Wang1-1/+1
ChangeLog: * MAINTAINERS: Update my email address
2023-12-12RISC-V: Add avail interface into function_group_infoFeng Wang5-475/+503
Patch v3: Fix typo and remove the modification of rvv.exp. Patch v2: Using variadic macro and add the dependency into t-riscv. In order to add other extension about vector,this patch add unsigned int (*avail) (void) into function_group_info to determine whether to register the intrinsic based on ISA info. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Add AVAIL argument. (read_vl): Using AVAIL argument default value. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64): Ditto. (vleff): Ditto. (vadd): Ditto. (vsub): Ditto. (vrsub): Ditto. (vneg): Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x): Ditto. (vzext): Ditto. (vsext): Ditto. (vadc): Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto. (vfwcvt_rtz_xu) Ditto.: (vfwcvt_f): Ditto. (vfwcvt_x_frm): Ditto. (vfwcvt_xu_frm) Ditto.: (vfncvt_x): Ditto. (vfncvt_xu): Ditto. (vfncvt_rtz_x): Ditto. (vfncvt_rtz_xu): Ditto. (vfncvt_f): Ditto. (vfncvt_rod_f): Ditto. (vfncvt_x_frm): Ditto. (vfncvt_xu_frm): Ditto. (vfncvt_f_frm): Ditto. (vredsum): Ditto. (vredmaxu): Ditto. (vredmax): Ditto. (vredminu): Ditto. (vredmin): Ditto. (vredand): Ditto. (vredor): Ditto. (vredxor): Ditto. (vwredsum): Ditto. (vwredsumu): Ditto. (vfredusum): Ditto. (vfredosum): Ditto. (vfredmax): Ditto. (vfredmin): Ditto. (vfredusum_frm): Ditto. (vfredosum_frm): Ditto. (vfwredosum): Ditto. (vfwredusum): Ditto. (vfwredosum_frm): Ditto. (vfwredusum_frm): Ditto. (vmand): Ditto. (vmnand): Ditto. (vmandn): Ditto. (vmxor): Ditto. (vmor): Ditto. (vmnor): Ditto. (vmorn): Ditto. (vmxnor): Ditto. (vmmv): Ditto. (vmclr): Ditto. (vmset): Ditto. (vmnot): Ditto. (vcpop): Ditto. (vfirst): Ditto. (vmsbf): Ditto. (vmsif): Ditto. (vmsof): Ditto. (viota): Ditto. (vid): Ditto. (vmv_x): Ditto. (vmv_s): Ditto. (vfmv_f): Ditto. (vfmv_s): Ditto. (vslideup): Ditto. (vslidedown): Ditto. (vslide1up): Ditto. (vslide1down): Ditto. (vfslide1up): Ditto. (vfslide1down): Ditto. (vrgather): Ditto. (vrgatherei16): Ditto. (vcompress): Ditto. (vundefined): Ditto. (vreinterpret): Ditto. (vlmul_ext): Ditto. (vlmul_trunc): Ditto. (vset): Ditto. (vget): Ditto. (vcreate): Ditto. (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): Using variadic macro. * config/riscv/riscv-vector-builtins.h (struct function_group_info): Add avail function interface into struct. * config/riscv/t-riscv: Add dependency * config/riscv/riscv-vector-builtins-avail.h: New file.The definition of AVAIL marco.
2023-12-12RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC]Juzhe-Zhong3-40/+52
This patch moves RVV POLY VALUE estimation from riscv.cc to riscv-v.cc for future better maintain like other target hook implementation. Committed as it is obviously a code refinement. gcc/ChangeLog: * config/riscv/riscv-protos.h (estimated_poly_value): New function. * config/riscv/riscv-v.cc (estimated_poly_value): Ditto. * config/riscv/riscv.cc (riscv_estimated_poly_value): Move RVV POLY VALUE estimation to riscv-v.cc
2023-12-12LoongArch: Fix eh_return epilogue for normal returns.Yang Yujie4-13/+84
On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved and restored in the function prologue and epilogue if the given function calls __builtin_eh_return. This causes the return value to be overwritten on normal return paths and breaks a rare case of libgcc's _Unwind_RaiseException. gcc/ChangeLog: * config/loongarch/loongarch.cc: Do not restore the saved eh_return data registers ($r4-$r7) for a normal return of a function that calls __builtin_eh_return elsewhere. * config/loongarch/loongarch-protos.h: Same. * config/loongarch/loongarch.md: Same. gcc/testsuite/ChangeLog: * gcc.target/loongarch/eh_return-normal-return.c: New test.
2023-12-12MAINTAINERS: Add myself to write after approval and DCOFeng Wang1-0/+1
ChangeLog: * MAINTAINERS: Add myself to write after approval
2023-12-12Daily bump.GCC Administrator13-1/+596
2023-12-11testsuite: Disable -fstack-protector* for some strub testsJakub Jelinek4-4/+4
In our distro builds, we test with RUNTESTFLAGS='--target_board=unix\{,-fstack-protector-strong\}' because SSP is something we use widely in the distribution. 4 new strub test FAIL with that option though, as can be seen with a simple make check-gcc check-g++ RUNTESTFLAGS='--target_board=unix\{,-fstack-protector-strong\} dg.exp=strub-O*' - in particular, the expand dump \[(\]call\[^\n\]*strub_leave.*\n\[(\]code_label regexps see code_labels in there introduced for stack protector. The following patch fixes it by using -fno-stack-protector for these explicitly. 2023-12-11 Jakub Jelinek <jakub@redhat.com> * c-c++-common/strub-O2fni.c: Add -fno-stack-protector to dg-options. * c-c++-common/strub-O3fni.c: Likewise. * c-c++-common/strub-Os.c: Likewise. * c-c++-common/strub-Og.c: Likewise.
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