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2023-10-08rs6000: build constant via li/lis;rldicl/rldicrJiufu Guo2-2/+105
2023-10-08rs6000: build constant via lis;rotldiJiufu Guo2-7/+53
2023-10-08rs6000: build constant via li;rotldiJiufu Guo2-6/+98
2023-10-08[i386] Fix apx test fails on 32bit targetHongyu Wang5-5/+5
2023-10-08RISC-V: add static-pie supportYanzhang Wang1-3/+4
2023-10-08TEST: Fix XPASS of TSVC testsuites for RVVJuzhe-Zhong23-23/+23
2023-10-08RISC-V: Enable more tests of "vect" for RVVJuzhe-Zhong1-37/+101
2023-10-08Daily bump.GCC Administrator3-1/+502
2023-10-07aarch64: Enable Cortex-X4 CPUSaurabh Jha3-4/+6
2023-10-07Revert "RISC-V: Add more run test for FP rounding autovec"Lehua Ding10-371/+2
2023-10-07[APX EGPR] Handle vex insns that only support GPR16 (5/5)Kong Lingling4-142/+242
2023-10-07[APX_EGPR] Handle legacy insns that only support GPR16 (4/5)Kong Lingling3-170/+289
2023-10-07[APX EGPR] Handle legacy insns that only support GPR16 (3/5)Kong Lingling5-33/+132
2023-10-07[APX EGPR] Handle legacy insns that only support GPR16 (2/5)Kong Lingling2-24/+155
2023-10-07[APX EGPR] Handle legacy insn that only support GPR16 (1/5)Kong Lingling4-6/+57
2023-10-07[APX EGPR] Handle GPR16 only vector move insnsHongyu Wang2-16/+60
2023-10-07[APX EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint.Kong Lingling3-0/+122
2023-10-07[APX EGPR] Add backend hook for base_reg_class/index_reg_class.Kong Lingling4-1/+111
2023-10-07[APX EGPR] Add register and memory constraints that disallow EGPRKong Lingling2-1/+62
2023-10-07[APX EGPR] Add 16 new integer general purpose registersKong Lingling7-24/+252
2023-10-07[APX_EGPR] Initial support for APX_FKong Lingling12-5/+102
2023-10-07[APX EGPR] middle-end: Add index_reg_class with insn argument.Hongyu Wang5-10/+37
2023-10-07[APX EGPR] middle-end: Add insn argument to base_reg_classKong Lingling6-23/+79
2023-10-07RISC-V: Add more run test for FP rounding autovecPan Li10-2/+371
2023-10-07rs6000: use mtvsrws to move sf from si p9Jiufu Guo2-9/+37
2023-10-07rs6000: optimize moving to sf from highpart diJiufu Guo3-5/+49
2023-10-07RISC-V: Bugfix for legitimize address PR/111634Pan Li1-1/+1
2023-10-07RISC-V: Fix scan-assembler-times of RVV test casexuli2-10/+10
2023-10-07Daily bump.GCC Administrator5-1/+153
2023-10-06i386: Implement doubleword shift left by 1 bit using add+adc.Roger Sayle4-1/+33
2023-10-06Makefile.tpl: disable -Werror for feedback stage [PR111663]Sergei Trofimovich2-0/+8
2023-10-06i386: Split lea into shorter left shift by 2 or 3 bits with -Oz.Roger Sayle2-0/+14
2023-10-06RISC-V: const: hide mvconst splitter from IRAVineet Gupta1-3/+6
2023-10-06Docs: Minimally document standard C/C++ attribute syntax.Sandra Loosemore1-22/+52
2023-10-06amdgcn: switch mov insns to compact syntaxAndrew Stubbs2-130/+108
2023-10-06amdgcn: silence warningAndrew Stubbs1-1/+1
2023-10-06libgomp.texi: Document some of the device-memory routinesTobias Burnus1-15/+288
2023-10-06MATCH: Fix infinite loop between `vec_cond(vec_cond(a,b,0), c, d)` and `a & b`Andrew Pinski2-0/+12
2023-10-06ipa: Remove ipa_bitsJakub Jelinek4-415/+206
2023-10-05RISC-V: Use stdint-gcc.h in rvv testsuitePatrick O'Neill28-28/+28
2023-10-06RISC-V: Update comments for FP rounding related autovecPan Li1-1/+5
2023-10-06Daily bump.GCC Administrator7-1/+267
2023-10-05RISC-V: Test memcpy inlined on riscv_vPatrick O'Neill2-0/+8
2023-10-05Delete MALLOC_ABI_ALIGNMENT define from pa32-linux.hJohn David Anglin1-5/+0
2023-10-05libstdc++: [_GLIBCXX_INLINE_VERSION] Add missing symbolsFrançois Dumont1-0/+9
2023-10-05Create a fast VRP passAndrew MacLeod3-0/+126
2023-10-05Add a dom based ranger for fast VRP.Andrew MacLeod2-0/+328
2023-10-05Add outgoing range vector calcualtion APIAndrew MacLeod2-0/+228
2023-10-05ipa-utils: avoid uninitialized probabilities on ICF [PR111559]Sergei Trofimovich2-7/+24
2023-10-05secpol: consistent indentationJan Engelhardt1-16/+16
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