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2023-05-02RISC-V: Table A.6 conformance testsPatrick O'Neill28-0/+360
These tests cover basic cases to ensure the atomic mappings follow the strengthened Table A.6 mappings that are compatible with Table A.7. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-a-6-fence-1.c: New test. * gcc.target/riscv/amo-table-a-6-fence-2.c: New test. * gcc.target/riscv/amo-table-a-6-fence-3.c: New test. * gcc.target/riscv/amo-table-a-6-fence-4.c: New test. * gcc.target/riscv/amo-table-a-6-fence-5.c: New test. * gcc.target/riscv/amo-table-a-6-load-1.c: New test. * gcc.target/riscv/amo-table-a-6-load-2.c: New test. * gcc.target/riscv/amo-table-a-6-load-3.c: New test. * gcc.target/riscv/amo-table-a-6-store-1.c: New test. * gcc.target/riscv/amo-table-a-6-store-2.c: New test. * gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Weaken atomic loadsPatrick O'Neill1-2/+26
This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/sync.md (atomic_load<mode>): Implement atomic load mapping. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Weaken mem_thread_fencePatrick O'Neill1-3/+13
This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Weaken LR/SC pairsPatrick O'Neill3-47/+114
Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs as needed. Atomic compare and exchange ops provide success and failure memory models. C++17 and later place no restrictions on the relative strength of each model, so ensure we cover both by using a model that enforces the ordering of both given models. This change brings LR/SC ops in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_union_memmodels): Expose riscv_union_memmodels function to sync.md. * config/riscv/riscv.cc (riscv_union_memmodels): Add function to get the union of two memmodels in sync.md. (riscv_print_operand): Add %I and %J flags that output the optimal LR/SC flag bits for a given memory model. * config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl bits on SC op and replace with optimized %I, %J flags. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Eliminate AMO op fencesPatrick O'Neill2-17/+11
Atomic operations with the appropriate bits set already enfore release semantics. Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/riscv.cc (riscv_memmodel_needs_amo_release): Change function name. (riscv_print_operand): Remove unneeded %F case. * config/riscv/sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Strengthen atomic storesPatrick O'Neill2-3/+27
This change makes atomic stores strictly stronger than table A.6 of the ISA manual. This mapping makes the overall patchset compatible with table A.7 as well. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> PR target/89835 gcc/ChangeLog: * config/riscv/sync.md (atomic_store<mode>): Use simple store instruction in combination with fence(s). gcc/testsuite/ChangeLog: * gcc.target/riscv/pr89835.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Add AMO release bitsPatrick O'Neill1-1/+6
This patch sets the relevant .rl bits on amo operations. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Enforce atomic compare_exchange SEQ_CSTPatrick O'Neill1-2/+9
This patch enforces SEQ_CST for atomic compare_exchange ops. Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/sync.md (atomic_cas_value_strong<mode>): Change FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Enforce subword atomic LR/SC SEQ_CSTPatrick O'Neill1-4/+4
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/sync.md: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pairs. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Enforce Libatomic LR/SC SEQ_CSTPatrick O'Neill1-2/+2
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> libgcc/ChangeLog: * config/riscv/atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pairs. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: Eliminate SYNC memory modelsPatrick O'Neill1-8/+3
Remove references to MEMMODEL_SYNC_* models by converting via memmodel_base(). 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and sanitize memmodel input with memmodel_base. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02libstdc++: Regenerate baseline_symbols.txt files for LinuxJakub Jelinek8-0/+16
The following patch regenerates the ABI files (I've only changed the Linux files which were updated recently (last month)). 2023-05-02 Jakub Jelinek <jakub@redhat.com> * config/abi/post/aarch64-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/i486-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/m68k-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/riscv64-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/s390x-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt: Update. * config/abi/post/x86_64-linux-gnu/baseline_symbols.txt: Update.
2023-05-02RISC-V: Name newly added flags in changelogPatrick O'Neill1-2/+4
This patch fixes the changelog to explicitly name the added command line flags introduced in this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html 2023-05-01 Patrick O'Neill <patrick@rivosinc.com> Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-05-02RISC-V: ICE for vlmul_ext_v intrinsic APIYanzhang Wang2-1/+16
PR target/109617 gcc/ChangeLog: * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test. Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com> Co-authored-by: Pan Li <pan2.li@intel.com> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
2023-05-02RISC-V: fix build issue with gcc 4.9.xRomain Naour1-2/+2
GCC should still build with GCC 4.8.3 or newer [1] using C++03 by default. But a recent change in RISC-V port introduced a C++11 feature "std::log2" [2]. Use log2 from the C header, without the namespace [3]. [1] https://gcc.gnu.org/install/prerequisites.html [2] https://gcc.gnu.org/git/?p=gcc.git;a=patch;h=7caa1ae5e451e780fbc4746a54e3f19d4f4304dc [3] https://stackoverflow.com/questions/26733413/error-log2-is-not-a-member-of-std Fixes: https://gitlab.com/buildroot.org/toolchains-builder/-/jobs/4202276589 gcc/ChangeLog: * config/riscv/genrvv-type-indexer.cc: Use log2 from the C header, without the namespace. Signed-off-by: Romain Naour <romain.naour@gmail.com>
2023-05-02c++: Add testcase for already fixed PR [PR109506]Patrick Palka1-0/+22
The PR109666 fix r14-386-g07c52d1eec967 incidentally also fixes this PR. PR c++/109506 gcc/testsuite/ChangeLog: * g++.dg/cpp0x/nsdmi-template26.C: New test.
2023-05-02docs: port documentation of VRP paramsMartin Liska1-6/+9
gcc/ChangeLog: * doc/invoke.texi: Update documentation based on param.opt file.
2023-05-02tree-optimization/109672 - properly check emulated plus during vectRichard Biener1-12/+9
The following refactors the check for emulated vector support for the cases of plus, minus and negate. In the PR we end up with a SImode plus, supported by the target but emulated and in this context fail to verify we are dealing with exactly word_mode. PR tree-optimization/109672 * tree-vect-stmts.cc (vectorizable_operation): For plus, minus and negate always check the vector mode is word mode.
2023-05-02[i386] Fix testcases for emulated scatterRichard Biener4-5/+8
The following adjusts testcases where the pr88531 fail with -m32 because we do not consider MMX size vectorization there and the pr89618 runs into load/store cost differences with -m32. * gcc.target/i386/pr88531-2a.c: Skip scanning for ia32. * gcc.target/i386/pr88531-2b.c: Likewise. * gcc.target/i386/pr88531-2c.c: Likewise. * gcc.target/i386/pr89618-2.c: Likewise. Disable AVX512.
2023-05-02ibstdc++: Shut up -Wattribute-alias warning [PR109694]Jakub Jelinek1-0/+2
I've followed what other files do, using attribute alias with not really matching function type (after all, it isn't really possible when it is a constructor), but seems I've missed it warns: ../../../../../libstdc++-v3/src/c++98/ios_init.cc:203:8: warning: ‘void std::ios_base_library_init()’ alias between functions of incompatible types ‘void()’ and ‘void +(std::ios_base::Init::)()’ [-Wattribute-alias=] 203 | void ios_base_library_init (void) | ^~~~~~~~~~~~~~~~~~~~~ ../../../../../libstdc++-v3/src/c++98/ios_init.cc:78:3: note: aliased declaration here 78 | ios_base::Init::Init() | ^~~~~~~~ The PR talks about clang++ warning there (which I think isn't really supported, libstdc++ sources ought to be built by GCC), but it warns when built with GCC too. The following patch fixes it by doing what other libstdc++ sources do in those cases. 2023-05-02 Jakub Jelinek <jakub@redhat.com> PR libstdc++/109694 * src/c++98/ios_init.cc: Add #pragma GCC diagnostic ignored for -Wattribute-alias.
2023-05-02Daily bump.GCC Administrator6-1/+432
2023-05-01ubsan: ubsan_maybe_instrument_array_ref tweakMarek Polacek1-6/+2
In <https://gcc.gnu.org/pipermail/gcc-patches/2023-March/613687.html> we discussed that the copy_node in ubsan_maybe_instrument_array_ref is redundant, but also that it'd be best to postpone the optimization to GCC 14. So I'm making that change now. gcc/c-family/ChangeLog: * c-ubsan.cc (ubsan_maybe_instrument_array_ref): Don't copy_node.
2023-05-01c++: array DMI and member fn [PR109666]Jason Merrill5-41/+58
Here it turns out I also needed to adjust cfun when stepping out of the member function to instantiate the DMI. But instead of adding that tweak, let's unify with instantiate_body and just push_to_top_level instead of trying to do the minimum subset of it. There was no measurable change in compile time on stdc++.h. This should also resolve 109506 without yet another tweak. PR c++/109666 gcc/cp/ChangeLog: * name-lookup.cc (maybe_push_to_top_level) (maybe_pop_from_top_level): Split out... * pt.cc (instantiate_body): ...from here. * init.cc (maybe_instantiate_nsdmi_init): Use them. * name-lookup.h: Declare them.. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/nsdmi-array2.C: New test.
2023-05-01PHIOPT: Update comment about what the pass now doesAndrew Pinski1-31/+36
I noticed I didn't update the comment about how the pass works after I initially added match_simplify_replacement. Anyways this updates the comment to be the current state of the pass. OK? gcc/ChangeLog: * tree-ssa-phiopt.cc: Update comment about how the transformation are implemented.
2023-05-01Convert xstormy16 to LRAJeff Law1-3/+0
This patch converts the xstormy16 patch to LRA. It introduces a code quality regression in the shiftsi testcase, but it also fixes numerous aborts/errors. IMHO it's a good tradeoff. gcc/ * config/stormy16/stormy16.cc (TARGET_LRA_P): Remove defintion.
2023-05-01Enable LRA on several portsJeff Law6-17/+0
Spurred by Segher's RFC, I went ahead and tested several ports with LRA enabled. Not surprisingly, many failed, but a few built their full set of libraries successful and of those a few even ran their testsuites with no regressions. In fact, enabling LRA fixes a small number of failures on the iq2000 port. This patch converts the ports which built their libraries and have test results that are as good as or better than without LRA. There may be minor code quality regressions or there may be minor code quality improvements -- I'm leaving that for the port maintainers to own going forward. gcc/ * config/cris/cris.cc (TARGET_LRA_P): Remove. * config/epiphany/epiphany.cc (TARGET_LRA_P): Remove. * config/iq2000/iq2000.cc (TARGET_LRA_P): Remove. * config/m32r/m32r.cc (TARGET_LRA_P): Remove. * config/microblaze/microblaze.cc (TARGET_LRA_P): Remove. * config/mmix/mmix.cc (TARGET_LRA_P): Remove.
2023-05-01apply debug-remap to file names in .su filesRasmus Villemoes3-2/+8
The .su files generated with -fstack-usage are arguably debug info. In order to make builds more reproducible, apply the same remapping logic to the recorded file names as for when producing the debug info embedded in the object files. To this end, teach print_decl_identifier() a new PRINT_DECL_REMAP_DEBUG flag and use that from output_stack_usage_1(). gcc/ChangeLog: * print-tree.h (PRINT_DECL_REMAP_DEBUG): New flag. * print-tree.cc (print_decl_identifier): Implement it. * toplev.cc (output_stack_usage_1): Use it.
2023-05-01libgcc pru: Define TARGET_HAS_NO_HW_DIVIDEDimitar Dimitrov1-0/+3
This patch aligns the configuration to the actual PRU capabilities. It also reduces the size of the affected libgcc functions. For a real-world project using integer arithmetics the savings are significant: Before: text data bss dec hex filename 3688 865 544 5097 13e9 hc-sr04-range-sensor.elf With TARGET_HAS_NO_HW_DIVIDE defined: text data bss dec hex filename 2824 865 544 4233 1089 hc-sr04-range-sensor.elf Execution speed also appears to have improved. The moddi3 function is now executed in half the CPU cycles. libgcc/ChangeLog: * config/pru/t-pru (HOST_LIBGCC2_CFLAGS): Add -DTARGET_HAS_NO_HW_DIVIDE. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2023-05-01Remove unused friends in int_range<>.Aldy Hernandez1-5/+0
gcc/ChangeLog: * value-range.h (class int_range): Remove gt_ggc_mx and gt_pch_nx friends.
2023-05-01Inline irange::set_nonzero.Aldy Hernandez1-2/+18
irange::set_nonzero is used everywhere and benefits immensely from inlining. gcc/ChangeLog: * value-range.h (irange::set_nonzero): Inline.
2023-05-01Cleanup irange::set.Aldy Hernandez5-135/+59
Now that anti-ranges are no more and iranges contain wide_ints instead of trees, various cleanups are possible. This is one of a handful of patches improving the performance of irange::set() which is not on a hot path, but quite sensitive because it is so pervasive. gcc/ChangeLog: * gimple-range-op.cc (cfn_ffs::fold_range): Use the correct precision. * gimple-ssa-warn-alloca.cc (alloca_call_type): Use <2> for invalid_range, as it is an inverse range. * tree-vrp.cc (find_case_label_range): Avoid trees. * value-range.cc (irange::irange_set): Delete. (irange::irange_set_1bit_anti_range): Delete. (irange::irange_set_anti_range): Delete. (irange::set): Cleanup. * value-range.h (class irange): Remove irange_set, irange_set_anti_range, irange_set_1bit_anti_range. (irange::set_undefined): Remove set to m_type.
2023-05-01Convert internal representation of irange to wide_ints.Aldy Hernandez6-213/+153
gcc/ChangeLog: * range-op.cc (update_known_bitmask): Adjust for irange containing wide_ints internally. * tree-ssanames.cc (set_nonzero_bits): Same. * tree-ssanames.h (set_nonzero_bits): Same. * value-range-storage.cc (irange_storage::set_irange): Same. (irange_storage::get_irange): Same. * value-range.cc (irange::operator=): Same. (irange::irange_set): Same. (irange::irange_set_1bit_anti_range): Same. (irange::irange_set_anti_range): Same. (irange::set): Same. (irange::verify_range): Same. (irange::contains_p): Same. (irange::irange_single_pair_union): Same. (irange::union_): Same. (irange::irange_contains_p): Same. (irange::intersect): Same. (irange::invert): Same. (irange::set_range_from_nonzero_bits): Same. (irange::set_nonzero_bits): Same. (mask_to_wi): Same. (irange::intersect_nonzero_bits): Same. (irange::union_nonzero_bits): Same. (gt_ggc_mx): Same. (gt_pch_nx): Same. (tree_range): Same. (range_tests_strict_enum): Same. (range_tests_misc): Same. (range_tests_nonzero_bits): Same. * value-range.h (irange::type): Same. (irange::varying_compatible_p): Same. (irange::irange): Same. (int_range::int_range): Same. (irange::set_undefined): Same. (irange::set_varying): Same. (irange::lower_bound): Same. (irange::upper_bound): Same.
2023-05-01Rewrite bounds_of_var_in_loop() to use ranges.Aldy Hernandez3-249/+117
Little by little, bounds_of_var_in_loop() has grown into an unmaintainable mess. This patch rewrites the code to use the relevant APIs as well as refactor it to make it more readable. gcc/ChangeLog: * gimple-range-fold.cc (tree_lower_bound): Delete. (tree_upper_bound): Delete. (vrp_val_max): Delete. (vrp_val_min): Delete. (fold_using_range::range_of_ssa_name_with_loop_info): Call range_of_var_in_loop. * vr-values.cc (valid_value_p): Delete. (fix_overflow): Delete. (get_scev_info): New. (bounds_of_var_in_loop): Refactor into... (induction_variable_may_overflow_p): ...this, (range_from_loop_direction): ...and this, (range_of_var_in_loop): ...and this. * vr-values.h (bounds_of_var_in_loop): Delete. (range_of_var_in_loop): New.
2023-05-01Replace vrp_val* with wide_ints.Aldy Hernandez6-115/+78
This patch removes all uses of vrp_val_{min,max} in favor for a irange_val_* which are wide_int based. This will leave only one use of vrp_val_* which returns trees in range_of_ssa_name_with_loop_info() because it needs to work with non-integers (floats, etc). In a follow-up patch, this function will also be cleaned up such that vrp_val_* can be deleted. The functions min_limit and max_limit in range-op.cc are now useless as they're basically irange_val*. I didn't rename them yet to avoid churn. I'll do it in a later patch. gcc/ChangeLog: * gimple-range-fold.cc (adjust_pointer_diff_expr): Rewrite with irange_val*. (vrp_val_max): New. (vrp_val_min): New. * gimple-range-op.cc (cfn_strlen::fold_range): Use irange_val_*. * range-op.cc (max_limit): Same. (min_limit): Same. (plus_minus_ranges): Same. (operator_rshift::op1_range): Same. (operator_cast::inside_domain_p): Same. * value-range.cc (vrp_val_is_max): Delete. (vrp_val_is_min): Delete. (range_tests_misc): Use irange_val_*. * value-range.h (vrp_val_is_min): Delete. (vrp_val_is_max): Delete. (vrp_val_max): Delete. (irange_val_min): New. (vrp_val_min): Delete. (irange_val_max): New. * vr-values.cc (check_for_binary_op_overflow): Use irange_val_*.
2023-05-01Conversion to irange wide_int API.Aldy Hernandez26-440/+608
This converts the irange API to use wide_ints exclusively, along with its users. This patch will slow down VRP, as there will be more useless wide_int to tree conversions. However, this slowdown is only temporary, as a follow-up patch will convert the internal representation of iranges to wide_ints for a net overall gain in performance. gcc/ChangeLog: * fold-const.cc (expr_not_equal_to): Convert to irange wide_int API. * gimple-fold.cc (size_must_be_zero_p): Same. * gimple-loop-versioning.cc (loop_versioning::prune_loop_conditions): Same. * gimple-range-edge.cc (gcond_edge_range): Same. (gimple_outgoing_range::calc_switch_ranges): Same. * gimple-range-fold.cc (adjust_imagpart_expr): Same. (adjust_realpart_expr): Same. (fold_using_range::range_of_address): Same. (fold_using_range::relation_fold_and_or): Same. * gimple-range-gori.cc (gori_compute::gori_compute): Same. (range_is_either_true_or_false): Same. * gimple-range-op.cc (cfn_toupper_tolower::get_letter_range): Same. (cfn_clz::fold_range): Same. (cfn_ctz::fold_range): Same. * gimple-range-tests.cc (class test_expr_eval): Same. * gimple-ssa-warn-alloca.cc (alloca_call_type): Same. * ipa-cp.cc (ipa_value_range_from_jfunc): Same. (propagate_vr_across_jump_function): Same. (decide_whether_version_node): Same. * ipa-prop.cc (ipa_get_value_range): Same. * ipa-prop.h (ipa_range_set_and_normalize): Same. * range-op.cc (get_shift_range): Same. (value_range_from_overflowed_bounds): Same. (value_range_with_overflow): Same. (create_possibly_reversed_range): Same. (equal_op1_op2_relation): Same. (not_equal_op1_op2_relation): Same. (lt_op1_op2_relation): Same. (le_op1_op2_relation): Same. (gt_op1_op2_relation): Same. (ge_op1_op2_relation): Same. (operator_mult::op1_range): Same. (operator_exact_divide::op1_range): Same. (operator_lshift::op1_range): Same. (operator_rshift::op1_range): Same. (operator_cast::op1_range): Same. (operator_logical_and::fold_range): Same. (set_nonzero_range_from_mask): Same. (operator_bitwise_or::op1_range): Same. (operator_bitwise_xor::op1_range): Same. (operator_addr_expr::fold_range): Same. (pointer_plus_operator::wi_fold): Same. (pointer_or_operator::op1_range): Same. (INT): Same. (UINT): Same. (INT16): Same. (UINT16): Same. (SCHAR): Same. (UCHAR): Same. (range_op_cast_tests): Same. (range_op_lshift_tests): Same. (range_op_rshift_tests): Same. (range_op_bitwise_and_tests): Same. (range_relational_tests): Same. * range.cc (range_zero): Same. (range_nonzero): Same. * range.h (range_true): Same. (range_false): Same. (range_true_and_false): Same. * tree-data-ref.cc (split_constant_offset_1): Same. * tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Same. * tree-ssa-loop-unswitch.cc (struct unswitch_predicate): Same. (find_unswitching_predicates_for_bb): Same. * tree-ssa-phiopt.cc (value_replacement): Same. * tree-ssa-threadbackward.cc (back_threader::find_taken_edge_cond): Same. * tree-ssanames.cc (ssa_name_has_boolean_range): Same. * tree-vrp.cc (find_case_label_range): Same. * value-query.cc (range_query::get_tree_range): Same. * value-range.cc (irange::set_nonnegative): Same. (frange::contains_p): Same. (frange::singleton_p): Same. (frange::internal_singleton_p): Same. (irange::irange_set): Same. (irange::irange_set_1bit_anti_range): Same. (irange::irange_set_anti_range): Same. (irange::set): Same. (irange::operator==): Same. (irange::singleton_p): Same. (irange::contains_p): Same. (irange::set_range_from_nonzero_bits): Same. (DEFINE_INT_RANGE_INSTANCE): Same. (INT): Same. (UINT): Same. (SCHAR): Same. (UINT128): Same. (UCHAR): Same. (range): New. (tree_range): New. (range_int): New. (range_uint): New. (range_uint128): New. (range_uchar): New. (range_char): New. (build_range3): Convert to irange wide_int API. (range_tests_irange3): Same. (range_tests_int_range_max): Same. (range_tests_strict_enum): Same. (range_tests_misc): Same. (range_tests_nonzero_bits): Same. (range_tests_nan): Same. (range_tests_signed_zeros): Same. * value-range.h (Value_Range::Value_Range): Same. (irange::set): Same. (irange::nonzero_p): Same. (irange::contains_p): Same. (range_includes_zero_p): Same. (irange::set_nonzero): Same. (irange::set_zero): Same. (contains_zero_p): Same. (frange::contains_p): Same. * vr-values.cc (simplify_using_ranges::op_with_boolean_value_range_p): Same. (bounds_of_var_in_loop): Same. (simplify_using_ranges::legacy_fold_cond_overflow): Same.
2023-05-01Merge irange::union/intersect into irange_union/intersect.Aldy Hernandez2-18/+7
gcc/ChangeLog: * value-range.cc (irange::irange_union): Rename to... (irange::union_): ...this. (irange::irange_intersect): Rename to... (irange::intersect): ...this. * value-range.h (irange::union_): Delete. (irange::intersect): Delete.
2023-05-01Convert get_legacy_range in bounds_of_var_in_loop to irange API.Aldy Hernandez1-2/+5
gcc/ChangeLog: * vr-values.cc (bounds_of_var_in_loop): Convert to irange API.
2023-05-01Various cleanups in vr-values.cc towards ranger API.Aldy Hernandez2-452/+87
gcc/ChangeLog: * vr-values.cc (check_for_binary_op_overflow): Tidy up by using ranger API. (compare_ranges): Delete. (compare_range_with_value): Delete. (bounds_of_var_in_loop): Tidy up by using ranger API. (simplify_using_ranges::fold_cond_with_ops): Cleanup and rename from vrp_evaluate_conditional_warnv_with_ops_using_ranges. (simplify_using_ranges::legacy_fold_cond_overflow): Remove strict_overflow_p and only_ranges. (simplify_using_ranges::legacy_fold_cond): Adjust call to legacy_fold_cond_overflow. (simplify_using_ranges::simplify_abs_using_ranges): Adjust for rename. (range_fits_type_p): Rename value_range to irange. * vr-values.h (range_fits_type_p): Adjust prototype.
2023-05-01Remove irange::tree_{lower,upper}_bound.Aldy Hernandez2-53/+22
gcc/ChangeLog: * value-range.cc (irange::irange_set_anti_range): Remove uses of tree_lower_bound and tree_upper_bound. (irange::verify_range): Same. (irange::operator==): Same. (irange::singleton_p): Same. * value-range.h (irange::tree_lower_bound): Delete. (irange::tree_upper_bound): Delete. (irange::lower_bound): Delete. (irange::upper_bound): Delete. (irange::zero_p): Remove uses of tree_lower_bound and tree_upper_bound.
2023-05-01Remove irange::{min,max,kind}.Aldy Hernandez5-118/+19
gcc/ChangeLog: * tree-ssa-loop-niter.cc (refine_value_range_using_guard): Remove kind() call. (determine_value_range): Same. (record_nonwrapping_iv): Same. (infer_loop_bounds_from_signedness): Same. (scev_var_range_cant_overflow): Same. * tree-vrp.cc (operand_less_p): Delete. * tree-vrp.h (operand_less_p): Delete. * value-range.cc (get_legacy_range): Remove uses of deprecated API. (irange::value_inside_range): Delete. * value-range.h (vrange::kind): Delete. (irange::num_pairs): Remove check of m_kind. (irange::min): Delete. (irange::max): Delete.
2023-05-01vrange_storage overhaulAldy Hernandez13-362/+518
[tl;dr: This is a rewrite of value-range-storage.* such that global ranges and the internal ranger cache can use the same efficient storage mechanism. It is optimized such that when wide_ints are dropped into irange, the copying back and forth from storage will be very fast, while being able to hold any number of sub-ranges dynamically allocated at run-time. This replaces the global storage mechanism which was limited to 6-subranges.] Previously we had a vrange allocator for use in the ranger cache. It worked with trees and could be used in place (fast), but it was not memory efficient. With the upcoming switch to wide_ints for irange, we can't afford to allocate ranges that can be used in place, because an irange will be significantly larger, as it will hold full wide_ints. We need a trailing_wide_int mechanism similar to what we use for global ranges, but fast enough to use in the ranger's cache. The global ranges had another allocation mechanism that was trailing_wide_int based. It was memory efficient but slow given the constant conversions from trees to wide_ints. This patch gets us the best of both worlds by providing a storage mechanism with a custom trailing wide int interface, while at the same time being fast enough to use in the ranger cache. We use a custom trailing wide_int mechanism but more flexible than trailing_wide_int, since the latter has compile-time fixed-sized wide_ints. The original TWI structure has the current length of each wide_int in a static portion preceeding the variable length: template <int N> struct GTY((user)) trailing_wide_ints { ... ... /* The current length of each number. that will, in turn, turn off TBAA on gimple, trees and RTL. */ struct {unsigned char len;} m_len[N]; /* The variable-length part of the structure, which always contains at least one HWI. Element I starts at index I * M_MAX_LEN. */ HOST_WIDE_INT m_val[1]; }; We need both m_len[] and m_val[] to be variable-length at run-time. In the previous incarnation of the storage mechanism the limitation of m_len[] being static meant that we were limited to whatever [N] could use up the unused bits in the TWI control world. In practice this meant we were limited to 6 sub-ranges. This worked fine for global ranges, but is a no go for our internal cache, where we must represent things exactly (ranges for switches, etc). The new implementation removes this restriction by making both m_len[] and m_val[] variable length. Also, rolling our own allows future optimization be using some of the leftover bits in the control world. Also, in preparation for the wide_int conversion, vrange_storage is now optimized to blast the bits directly into the ultimate irange instead of going through the irange API. So ultimately copying back and forth between the ranger cache and the storage mechanism is just a matter of copying a few bits for the control word, and copying an array of HOST_WIDE_INTs. These changes were heavily profiled, and yielded a good chunk of the overall speedup for the wide_int conversion. Finally, vrange_storage is now a first class structure with GTY markers and all, thus alleviating the void * hack in struct tree_ssa_name and friends. This removes a few warts in the API and looks cleaner overall. gcc/ChangeLog: * gimple-fold.cc (maybe_fold_comparisons_from_match_pd): Adjust for vrange_storage. * gimple-range-cache.cc (sbr_vector::sbr_vector): Same. (sbr_vector::grow): Same. (sbr_vector::set_bb_range): Same. (sbr_vector::get_bb_range): Same. (sbr_sparse_bitmap::sbr_sparse_bitmap): Same. (sbr_sparse_bitmap::set_bb_range): Same. (sbr_sparse_bitmap::get_bb_range): Same. (block_range_cache::block_range_cache): Same. (ssa_global_cache::ssa_global_cache): Same. (ssa_global_cache::get_global_range): Same. (ssa_global_cache::set_global_range): Same. * gimple-range-cache.h: Same. * gimple-range-edge.cc (gimple_outgoing_range::gimple_outgoing_range): Same. (gimple_outgoing_range::switch_edge_range): Same. (gimple_outgoing_range::calc_switch_ranges): Same. * gimple-range-edge.h: Same. * gimple-range-infer.cc (infer_range_manager::infer_range_manager): Same. (infer_range_manager::get_nonzero): Same. (infer_range_manager::maybe_adjust_range): Same. (infer_range_manager::add_range): Same. * gimple-range-infer.h: Rename obstack_vrange_allocator to vrange_allocator. * tree-core.h (struct irange_storage_slot): Remove. (struct tree_ssa_name): Remove irange_info and frange_info. Make range_info a pointer to vrange_storage. * tree-ssanames.cc (range_info_fits_p): Adjust for vrange_storage. (range_info_alloc): Same. (range_info_free): Same. (range_info_get_range): Same. (range_info_set_range): Same. (get_nonzero_bits): Same. * value-query.cc (get_ssa_name_range_info): Same. * value-range-storage.cc (class vrange_internal_alloc): New. (class vrange_obstack_alloc): New. (class vrange_ggc_alloc): New. (vrange_allocator::vrange_allocator): New. (vrange_allocator::~vrange_allocator): New. (vrange_storage::alloc_slot): New. (vrange_allocator::alloc): New. (vrange_allocator::free): New. (vrange_allocator::clone): New. (vrange_allocator::clone_varying): New. (vrange_allocator::clone_undefined): New. (vrange_storage::alloc): New. (vrange_storage::set_vrange): Remove slot argument. (vrange_storage::get_vrange): Same. (vrange_storage::fits_p): Same. (vrange_storage::equal_p): New. (irange_storage::write_lengths_address): New. (irange_storage::lengths_address): New. (irange_storage_slot::alloc_slot): Remove. (irange_storage::alloc): New. (irange_storage_slot::irange_storage_slot): Remove. (irange_storage::irange_storage): New. (write_wide_int): New. (irange_storage_slot::set_irange): Remove. (irange_storage::set_irange): New. (read_wide_int): New. (irange_storage_slot::get_irange): Remove. (irange_storage::get_irange): New. (irange_storage_slot::size): Remove. (irange_storage::equal_p): New. (irange_storage_slot::num_wide_ints_needed): Remove. (irange_storage::size): New. (irange_storage_slot::fits_p): Remove. (irange_storage::fits_p): New. (irange_storage_slot::dump): Remove. (irange_storage::dump): New. (frange_storage_slot::alloc_slot): Remove. (frange_storage::alloc): New. (frange_storage_slot::set_frange): Remove. (frange_storage::set_frange): New. (frange_storage_slot::get_frange): Remove. (frange_storage::get_frange): New. (frange_storage_slot::fits_p): Remove. (frange_storage::equal_p): New. (frange_storage::fits_p): New. (ggc_vrange_allocator): New. (ggc_alloc_vrange_storage): New. * value-range-storage.h (class vrange_storage): Rewrite. (class irange_storage): Rewrite. (class frange_storage): Rewrite. (class obstack_vrange_allocator): Remove. (class ggc_vrange_allocator): Remove. (vrange_allocator::alloc_vrange): Remove. (vrange_allocator::alloc_irange): Remove. (vrange_allocator::alloc_frange): Remove. (ggc_alloc_vrange_storage): New. * value-range.h (class irange): Rename vrange_allocator to irange_storage. (class frange): Same.
2023-05-01Daily bump.GCC Administrator7-1/+118
2023-04-30Revert "[PATCH] libcpp: suppress builtin macro redefined warnings for __LINE__"Jeff Law3-70/+5
This reverts commit e7ce7c4905fd254760b1cd187752a03bc0c148ba.
2023-04-30[Committed] Update xstormy16's neghi2 pattern to not clobber the carry flag.Roger Sayle2-5/+4
When I converted xstormy's neghi2 pattern from a define_expand to a define_insn, I forgot that define_expand implicitly produces a sequence of instructions, but a define_insn is an implicit parallel, thereby messing up the clobber (reg:BI CARRY_REG), which can then cause an ICE in the auto-generated added_clobbers_hard_reg_p. Whilst stripping the superfluous PARALLEL resolves this issue, an even better fix is to use xstormy16's INC instruction, that (like NOT) doesn't affect the carry flag, resulting in a neghi2 implementation that can more easily be CSE'd and scheduled. Many thanks (again) to Jeff Law for testing/reporting this issue. 2024-04-30 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/stormy16/stormy16.md (neghi2): Rewrite pattern using inc to avoid clobbering the carry flag. gcc/testsuite/ChangeLog * gcc.target/xstormy16/neghi2.c: Update expected implementation.
2023-04-30Improve error message for excess elements in array initializer from {"a"}Andrew Pinski6-11/+11
So char arrays are not the only type that be initialized from {"a"}. We can have wchar_t (L"") and char16_t (u"") types too. So let's print out the type of the array instead of just saying char. Note in the testsuite I used regex . to match '[' and ']' as I could not figure out how many '\' I needed. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/c/ChangeLog: * c-typeck.cc (process_init_element): Print out array type for excessive elements. gcc/testsuite/ChangeLog: * gcc.dg/init-bad-1.c: Update error message. * gcc.dg/init-bad-2.c: Likewise. * gcc.dg/init-bad-3.c: Likewise. * gcc.dg/init-excess-3.c: Likewise. * gcc.dg/pr61096-1.c: Likewise.
2023-04-30Fix C/107926: Wrong error message when initializing char arrayAndrew Pinski2-5/+25
The problem here is the code which handles {"a"} is supposed to handle the case where the is something after the string but it only handles the case where there is another string so we go down the other path and error out saying "excess elements in struct initializer" even though this was a character array. To fix this, we need to move the ckeck if the initializer is a string after the check for array and initializer. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. Thanks, Adnrew Pinski gcc/c/ChangeLog: PR c/107926 * c-typeck.cc (process_init_element): Move the check for string cst until after the error message. gcc/testsuite/ChangeLog: PR c/107926 * gcc.dg/init-excess-3.c: New test.
2023-04-30MATCH: add some of what phiopt's builtin_zero_pattern didAndrew Pinski1-2/+39
This adds the patterns for POPCOUNT BSWAP FFS PARITY CLZ and CTZ. For "a != 0 ? FUNC(a) : CST". CLRSB, CLRSBL, and CLRSBLL will be moved next. Note this is not enough to remove cond_removal_in_builtin_zero_pattern as we need to handle the case where there is an NOP_CONVERT inside the conditional to move out of the condition inside match_simplify_replacement. OK? Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * match.pd: Add patterns for "a != 0 ? FUNC(a) : CST" for FUNC of POPCOUNT BSWAP FFS PARITY CLZ and CTZ.
2023-04-30PHIOPT: Allow moving of some builtin callsAndrew Pinski1-4/+31
While moving working on moving cond_removal_in_builtin_zero_pattern to match, I noticed that functions were not allowed to move as we reject all non-assignments. This changes to allowing a few calls which are known not to throw/trap. Right now it is restricted to ones which cond_removal_in_builtin_zero_pattern handles but adding more is just adding it to the switch statement. gcc/ChangeLog: * tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p): Allow some builtin/internal function calls which are known not to trap/throw. (phiopt_worker::match_simplify_replacement): Use name instead of getting the lhs again.
2023-04-30hwasan: adjust wording in expected output in testsMartin Liska4-7/+7
gcc/testsuite/ChangeLog: * c-c++-common/hwasan/asan-pr70541.c: Adjust wording of expected output. * c-c++-common/hwasan/heap-overflow.c: Likewise. * c-c++-common/hwasan/sanity-check-pure-c.c: Likewise. * c-c++-common/hwasan/use-after-free.c: Likewise.
2023-04-30libsanitizer: link hwasan against lsan libraryMartin Liska2-3/+5
Similarly to libasan.so, libhwasan.so also utilizes some of the symbols from lsan library. PR sanitizer/109674 libsanitizer/ChangeLog: * hwasan/Makefile.am: Depend on liblsan. * hwasan/Makefile.in: Re-generate.
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