aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-05-10Avoid g++.dg/torture/pr106922.C FAIL with the pre-C++11 ABIRichard Biener1-0/+9
The following forces the g++.dg/torture/pr106922.C testcase to use the C++11 libstdc++ ABI and checks whether that worked. gcc/testsuite/ * g++.dg/torture/pr106922.C: Force _GLIBCXX_USE_CXX11_ABI to 1.
2023-05-10Fix a couple constraints on the H8 in preparation for LRA conversionJeff Law1-2/+2
So this is the 2nd patch on the way to LRA for the H8. LRA is more sensitive to getting define_constraint vs define_memory_constraint vs define_special_memory_constraint correct. than reload. The H8 port has the "Q" constraint, which is used to indicate memory addresses that can be used under certain circumstances in various ALU operations. So it should be a memory constraint. Ideally it'd would be a simple memory constraint, but it's used in contexts where MEMs are valid only for certain parts in the H8 family. So it really needs to be a special_memory_constraint. The "Zz" constraint accepts memory, but the forms are limited and can not be reloaded into a register. It seems to be working, but I wouldn't be totally surprised if this got stressed in the right way if it broke. Anyway, this patch fixes "Q" and "Zz" to be special memory constraints. Regression tested with gdbsim and pushed to the trunk. gcc * config/h8300/constraints.md (Q): Make this a special memory constraint. (Zz): Similarly.
2023-05-10ipa-prop: Fix ipa_get_callee_param_type for calls with argument type mismatchesJakub Jelinek1-1/+1
The PR contains a testcase where the Fortran FE creates FUNCTION_TYPE which doesn't really match the passed in arguments (FUNCTION_TYPE has 5 arguments, call has 6). Now, I think that is a Fortran FE bug that should be fixed there, but I think with function pointers one can create something similar (of course invalid) in C/C++ too,so IMHO IPA should be also more careful. The ipa_get_callee_param_type function can return NULL if something goes wrong and it does e.g. if asked for 7th argument type on a function with just 5 arguments and similar. But, if a function isn't varargs, when asked for 6th argument type on a function with just 5 arguments it actually returns void_type_node because the argument list is in that case terminated with void_list_node. The following patch makes sure we don't treat void_list_node as something holding another argument. 2023-05-10 Jakub Jelinek <jakub@redhat.com> PR fortran/109788 * ipa-prop.cc (ipa_get_callee_param_type): Don't return TREE_VALUE (t) if t is void_list_node.
2023-05-10aarch64: Simplify sqmovun expanderKyrylo Tkachov2-40/+13
This patch is a no-op as it removes the explicit vec-concat-zero patterns in favour of vczle/vczbe. This allows us to delete the explicit expander too. Tests are added to ensure the optimisation required still triggers. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>_insn_le): Delete. (aarch64_sqmovun<mode>_insn_be): Delete. (aarch64_sqmovun<mode><vczle><vczbe>): New define_insn. (aarch64_sqmovun<mode>): Delete expander. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/pr99195_4.c: Add tests for sqmovun.
2023-05-10[PATCH] aarch64: PR target/99195 annotate simple permutation patterns for ↵Kyrylo Tkachov2-8/+16
vec-concat-zero Another straightforward patch annotating patterns for the zip1, zip2, uzp1, uzp2, rev* instructions, plus tests. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_<PERMUTE:perm_insn><mode>): Rename to... (aarch64_<PERMUTE:perm_insn><mode><vczle><vczbe>): ... This. (aarch64_rev<REVERSE:rev_op><mode>): Rename to... (aarch64_rev<REVERSE:rev_op><mode><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add tests for zip and rev intrinsics.
2023-05-10aarch64: PR target/99195 annotate simple saturating add/sub patterns for ↵Kyrylo Tkachov3-11/+41
vec-concat-zero Moving onto the saturating instructions, this one goes through the simple add/sub ones. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_<su_optab>q<addsub><mode>): Rename to... (aarch64_<su_optab>q<addsub><mode><vczle><vczbe>): ... This. (aarch64_<sur>qadd<mode>): Rename to... (aarch64_<sur>qadd<mode><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add testing for qadd, qsub. * gcc.target/aarch64/simd/pr99195_6.c: New test.
2023-05-10aarch64: Simplify QSHRN expanders and patternsKyrylo Tkachov2-34/+50
This patch deletes the explicit BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN patterns for the QSHRN instructions in favour of annotating a single one with <vczle><vczbe>. This allows simplification of the expander too. Tests are added to ensure that we still optimise away the concat-with-zero use case. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): Delete. (aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): Delete. (aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): New define_insn. (aarch64_<sur>q<r>shr<u>n_n<mode>): Simplify expander. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/pr99195_5.c: New test.
2023-05-10aarch64: PR target/99195 annotate simple narrowing patterns for vec-concat-zeroKyrylo Tkachov2-84/+37
This patch cleans up some almost-duplicate patterns for the XTN, SQXTN, UQXTN instructions. Using the <vczle><vczbe> attributes we can remove the BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN cases, as well as the intrinsic expanders that select between the two. Tests are also added. Thankfully the diffstat comes out negative \O/. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le): Delete. (aarch64_xtn<mode>_insn_be): Likewise. (trunc<mode><Vnarrowq>2): Rename to... (trunc<mode><Vnarrowq>2<vczle><vczbe>): ... This. (aarch64_xtn<mode>): Move under the above. Just emit the truncate RTL. (aarch64_<su>qmovn<mode>): Likewise. (aarch64_<su>qmovn<mode><vczle><vczbe>): New define_insn. (aarch64_<su>qmovn<mode>_insn_le): Delete. (aarch64_<su>qmovn<mode>_insn_be): Likewise. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_4.c: Add tests for vmovn, vqmovn.
2023-05-10c++: Reject attributes without arguments used as pack expansion [PR109756]Jakub Jelinek2-2/+40
The following testcase shows we silently accept (and ignore) attributes without arguments used as pack expansions. This is because we call make_pack_expansion and that starts with if (!arg || arg == error_mark_node) return arg; Now, an attribute without arguments like [[noreturn...]] is IMHO always invalid, in this case for 2 reasons; one is that as it has no arguments, no pack can be present and second is that the standard says that attributes need to specially permit uses of parameter pack and doesn't explicitly permit it for any of the standard attributes (except for alignas? which has different syntax). If an attribute has some arguments but doesn't contain packs in those arguments, make_pack_expansion will already diagnose it. The patch also changes cp_parser_std_attribute, such that for attributes unknown to the compiler (or perhaps registered just for -Wno-attributes=) we differentiate between the attribute having no arguments (in that case we want to diagnose them when followed by ellipsis even if they are unknown, as they can't contain a pack in that case) and the case where they do have arguments but we've just skipped over those arguments because we don't know how to parse them (except that they are a balanced token sequence) - in that case we really don't know if they contain packs or not. 2023-05-10 Jakub Jelinek <jakub@redhat.com> PR c++/109756 * parser.cc (cp_parser_std_attribute): For unknown attributes with arguments set TREE_VALUE (attribute) to error_mark_node after skipping the balanced tokens. (cp_parser_std_attribute_list): If ... is used after attribute without arguments, diagnose it and return error_mark_node. If TREE_VALUE (attribute) is error_mark_node, don't call make_pack_expansion nor return early error_mark_node. * g++.dg/cpp0x/gen-attrs-78.C: New test.
2023-05-10RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying ↵Li Xu3-0/+56
REG_P(operand[1]) in -O0. This issue happens is because the operand1 of scalar move can be REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to not insert the vsetvl instruction correctly, and the compiler crashes. Consider this following case: int16_t foo1 (void *base, size_t vl) { int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl)); return maxVal; } Before this patch: bug.c:15:1: internal compiler error: Segmentation fault 15 | } | ^ 0x145d723 crash_signal ../.././riscv-gcc/gcc/toplev.cc:314 0x22929dd const_csr_operand(rtx_def*, machine_mode) ../.././riscv-gcc/gcc/config/riscv/predicates.md:44 0x2292a21 csr_operand(rtx_def*, machine_mode) ../.././riscv-gcc/gcc/config/riscv/predicates.md:46 0x23dfbb0 recog_356 ../.././riscv-gcc/gcc/config/riscv/iterators.md:72 0x23efecd recog(rtx_def*, rtx_insn*, int*) ../.././riscv-gcc/gcc/config/riscv/iterators.md:89 0xdddc15 recog_memoized(rtx_insn*) ../.././riscv-gcc/gcc/recog.h:273 After this patch: vsetivli zero,0,e16,m1,ta,ma vmv.x.s a5,v1 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s intruction replace null avl with (const_int 0). gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/scalar_move-10.c: New test. * gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
2023-05-10RISC-V: Fix incorrect implementation of ↵Juzhe-Zhong15-39/+32
TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT This incorrect codes blocks the scalable RVV auto-vectorization. Take a look at this target hook implementation of aarch64. They only have the similiar handling on TARGET_SIMD. They let movmisalign<mode> to handle scalable vector of SVE. For RVV, we should follow the same implementation of ARM SVE. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix incorrect codes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/v-2.c: Adapt testcase. * gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto.
2023-05-10RISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773]Juzhe-Zhong3-0/+71
This patch is fix dead loop in vsetvl intrinsic avl checking. vsetvli->get_def () has vsetvli->get_def () has vsetvli..... Then it will keep looping in the vsetvli avl checking which is a dead loop. PR target/109773 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (avl_source_has_vsetvl_p): New function. (source_equal_p): Fix dead loop in vsetvl avl checking. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: New test. * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: New test.
2023-05-10New testcaseAndrew Pinski1-0/+28
While I was writting a match.pd patch, I can across GCC was being miscompiled but no testcase was failing. So this adds that testcase. Committed after testing on x86_64 with make check-gcc RUNTESTFLAGS="execute.exp=20230509-1.c" gcc/testsuite/ChangeLog: * gcc.c-torture/execute/20230509-1.c: New test.
2023-05-10CRIS: Fix ccmode typo in cris_postdbr_cmpelimHans-Peter Nilsson1-1/+1
Typo spotted while doing CCmode improvements, as a missed optimization. It's almost visible from the patch context; there's not much done in terms of "mode-adjustment" when replacing (reg:CC CRIS_CC0_REGNUM) with a copy! This bug affects functions in the newlib printf-formatting functions (nothing else in libgcc or newlib libc), with the performance impact on coremark scores being less than 1e-6 (3/5078992 cycles, 6/48543 bytes). * config/cris/cris.cc (cris_postdbr_cmpelim): Correct mode of modeadjusted_dccr.
2023-05-10Daily bump.GCC Administrator9-1/+1527
2023-05-09Update cpplib ru.poJoseph Myers1-43/+29
* ru.po: Update.
2023-05-09Update gcc hr.poJoseph Myers1-3/+3
* hr.po: Update.
2023-05-09libstdc++: Fix <chrono> pretty printers and add testsJonathan Wakely2-18/+113
This fixes a couple of errors in the printers for chrono types, and adds tests to ensure they keep working. libstdc++-v3/ChangeLog: * python/libstdcxx/v6/printers.py (StdChronoDurationPrinter): Print floating-point durations correctly. (StdChronoTimePointPrinter): Support printing only the value, not the type name. Uncomment handling for known clocks. (StdChronoZonedTimePrinter): Remove type names from output. (StdChronoCalendarPrinter): Fix hh_mm_ss member access. (StdChronoTimeZonePrinter): Add equals sign to output. * testsuite/libstdc++-prettyprinters/chrono.cc: New test.
2023-05-09c++: error-recovery ICE with unstable satisfaction [PR109752]Patrick Palka2-3/+36
After diagnosing and recovering from unstable satisfaction, it's possible to evaluate an atom for the first time noisily rather than quietly. The satisfaction cache tries to handle this situation gracefully, but apparently not gracefully enough: we inserted an empty slot into the cache, and left it empty, which later makes hash_table::check_complete_insertion unhappy. This patch fixes this by removing the empty slot in this case. PR c++/109752 gcc/cp/ChangeLog: * constraint.cc (satisfaction_cache::satisfaction_cache): In the unexpected case of evaluating an atom for the first time noisily, remove the cache slot that we inserted. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-pr109752.C: New test.
2023-05-09c++: noexcept-spec from nested class confusion [PR109761]Patrick Palka2-7/+22
When late processing a noexcept-spec from a nested class after completion of the outer class (since it's a complete-class context), we pass the wrong class context to noexcept_override_late_checks -- the outer class type instead of the nested class type -- which leads to bogus errors in the below test. This patch fixes this by making noexcept_override_late_checks obtain the class context directly via DECL_CONTEXT instead of via an additional parameter. PR c++/109761 gcc/cp/ChangeLog: * parser.cc (cp_parser_class_specifier): Don't pass a class context to noexcept_override_late_checks. (noexcept_override_late_checks): Remove 'type' parameter and use DECL_CONTEXT of 'fndecl' instead. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/noexcept78.C: New test.
2023-05-09arm: [MVE intrinsics] rework vmaxaq vminaqChristophe Lyon5-240/+8
Implement vmaxaq and vminaq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmaxaq, vminaq): New. * config/arm/arm-mve-builtins-base.def (vmaxaq, vminaq): New. * config/arm/arm-mve-builtins-base.h (vmaxaq, vminaq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vmaxaq and vminaq. * config/arm/arm_mve.h (vminaq): Remove. (vmaxaq): Remove. (vminaq_m): Remove. (vmaxaq_m): Remove. (vminaq_s8): Remove. (vmaxaq_s8): Remove. (vminaq_s16): Remove. (vmaxaq_s16): Remove. (vminaq_s32): Remove. (vmaxaq_s32): Remove. (vminaq_m_s8): Remove. (vmaxaq_m_s8): Remove. (vminaq_m_s16): Remove. (vmaxaq_m_s16): Remove. (vminaq_m_s32): Remove. (vmaxaq_m_s32): Remove. (__arm_vminaq_s8): Remove. (__arm_vmaxaq_s8): Remove. (__arm_vminaq_s16): Remove. (__arm_vmaxaq_s16): Remove. (__arm_vminaq_s32): Remove. (__arm_vmaxaq_s32): Remove. (__arm_vminaq_m_s8): Remove. (__arm_vmaxaq_m_s8): Remove. (__arm_vminaq_m_s16): Remove. (__arm_vmaxaq_m_s16): Remove. (__arm_vminaq_m_s32): Remove. (__arm_vmaxaq_m_s32): Remove. (__arm_vminaq): Remove. (__arm_vmaxaq): Remove. (__arm_vminaq_m): Remove. (__arm_vmaxaq_m): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmaxaq vminaqChristophe Lyon2-39/+28
Factorize vmaxaq vminaq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMAXAVMINAQ, MVE_VMAXAVMINAQ_M): New. (mve_insn): Add vmaxa, vmina. (supf): Add VMAXAQ_S, VMAXAQ_M_S, VMINAQ_S, VMINAQ_M_S. * config/arm/mve.md (mve_vmaxaq_s<mode>, mve_vminaq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmaxaq_m_s<mode>, mve_vminaq_m_s<mode>): Merge into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-09arm: [MVE intrinsics] add binary_maxamina shapeChristophe Lyon2-0/+41
This patch adds the binary_maxamina shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_maxamina): New. * config/arm/arm-mve-builtins-shapes.h (binary_maxamina): New.
2023-05-09arm: [MVE intrinsics] rework vmaxnmaq vminnmaqChristophe Lyon5-148/+8
Implement vmaxnmaq and vminnmaq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmaxnmaq, vminnmaq): New. * config/arm/arm-mve-builtins-base.def (vmaxnmaq, vminnmaq): New. * config/arm/arm-mve-builtins-base.h (vmaxnmaq, vminnmaq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vmaxnmaq and vminnmaq. * config/arm/arm_mve.h (vminnmaq): Remove. (vmaxnmaq): Remove. (vmaxnmaq_m): Remove. (vminnmaq_m): Remove. (vminnmaq_f16): Remove. (vmaxnmaq_f16): Remove. (vminnmaq_f32): Remove. (vmaxnmaq_f32): Remove. (vmaxnmaq_m_f16): Remove. (vminnmaq_m_f16): Remove. (vmaxnmaq_m_f32): Remove. (vminnmaq_m_f32): Remove. (__arm_vminnmaq_f16): Remove. (__arm_vmaxnmaq_f16): Remove. (__arm_vminnmaq_f32): Remove. (__arm_vmaxnmaq_f32): Remove. (__arm_vmaxnmaq_m_f16): Remove. (__arm_vminnmaq_m_f16): Remove. (__arm_vmaxnmaq_m_f32): Remove. (__arm_vminnmaq_m_f32): Remove. (__arm_vminnmaq): Remove. (__arm_vmaxnmaq): Remove. (__arm_vmaxnmaq_m): Remove. (__arm_vminnmaq_m): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmaxnmaq vminnmaqChristophe Lyon2-39/+24
Factorize vmaxnmaq and vminnmaq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMAXNMA_VMINNMAQ) (MVE_VMAXNMA_VMINNMAQ_M): New. (mve_insn): Add vmaxnma, vminnma. * config/arm/mve.md (mve_vmaxnmaq_f<mode>, mve_vminnmaq_f<mode>): Merge into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vmaxnmaq_m_f<mode>, mve_vminnmaq_m_f<mode>): Merge into ... (@mve_<mve_insn>q_m_f<mode>): ... this.
2023-05-09arm: [MVE intrinsics] rework vmaxnmavq vmaxnmvq vminnmavq vminnmvqChristophe Lyon4-314/+18
Implement vmaxnmavq vmaxnmvq vminnmavq vminnmvq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_F): New. (vmaxnmavq, vmaxnmvq, vminnmavq, vminnmvq): New. * config/arm/arm-mve-builtins-base.def (vmaxnmavq, vmaxnmvq) (vminnmavq, vminnmvq): New. * config/arm/arm-mve-builtins-base.h (vmaxnmavq, vmaxnmvq) (vminnmavq, vminnmvq): New. * config/arm/arm_mve.h (vminnmvq): Remove. (vminnmavq): Remove. (vmaxnmvq): Remove. (vmaxnmavq): Remove. (vmaxnmavq_p): Remove. (vmaxnmvq_p): Remove. (vminnmavq_p): Remove. (vminnmvq_p): Remove. (vminnmvq_f16): Remove. (vminnmavq_f16): Remove. (vmaxnmvq_f16): Remove. (vmaxnmavq_f16): Remove. (vminnmvq_f32): Remove. (vminnmavq_f32): Remove. (vmaxnmvq_f32): Remove. (vmaxnmavq_f32): Remove. (vmaxnmavq_p_f16): Remove. (vmaxnmvq_p_f16): Remove. (vminnmavq_p_f16): Remove. (vminnmvq_p_f16): Remove. (vmaxnmavq_p_f32): Remove. (vmaxnmvq_p_f32): Remove. (vminnmavq_p_f32): Remove. (vminnmvq_p_f32): Remove. (__arm_vminnmvq_f16): Remove. (__arm_vminnmavq_f16): Remove. (__arm_vmaxnmvq_f16): Remove. (__arm_vmaxnmavq_f16): Remove. (__arm_vminnmvq_f32): Remove. (__arm_vminnmavq_f32): Remove. (__arm_vmaxnmvq_f32): Remove. (__arm_vmaxnmavq_f32): Remove. (__arm_vmaxnmavq_p_f16): Remove. (__arm_vmaxnmvq_p_f16): Remove. (__arm_vminnmavq_p_f16): Remove. (__arm_vminnmvq_p_f16): Remove. (__arm_vmaxnmavq_p_f32): Remove. (__arm_vmaxnmvq_p_f32): Remove. (__arm_vminnmavq_p_f32): Remove. (__arm_vminnmvq_p_f32): Remove. (__arm_vminnmvq): Remove. (__arm_vminnmavq): Remove. (__arm_vmaxnmvq): Remove. (__arm_vmaxnmavq): Remove. (__arm_vmaxnmavq_p): Remove. (__arm_vmaxnmvq_p): Remove. (__arm_vminnmavq_p): Remove. (__arm_vminnmvq_p): Remove. (__arm_vmaxnmavq_m): Remove. (__arm_vmaxnmvq_m): Remove.
2023-05-09arm: [MVE intrinsics] add support for mve_q_p_fChristophe Lyon1-1/+1
We can call code_for_mve_q_p_f only once this function exists, which is the case after we factorized vmaxnmavq, vmaxnmvq, vminnmavq and vminnmvq in a previous patch. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-functions.h (unspec_mve_function_exact_insn_pred_p): Use code_for_mve_q_p_f.
2023-05-09arm: [MVE intrinsics] factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvqChristophe Lyon2-99/+37
Factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMAXNMxV_MINNMxVQ) (MVE_VMAXNMxV_MINNMxVQ_P): New. (mve_insn): Add vmaxnmav, vmaxnmv, vminnmav, vminnmv. * config/arm/mve.md (mve_vmaxnmavq_f<mode>, mve_vmaxnmvq_f<mode>) (mve_vminnmavq_f<mode>, mve_vminnmvq_f<mode>): Merge into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vmaxnmavq_p_f<mode>, mve_vmaxnmvq_p_f<mode>) (mve_vminnmavq_p_f<mode>, mve_vminnmvq_p_f<mode>): Merge into ... (@mve_<mve_insn>q_p_f<mode>): ... this.
2023-05-09arm: [MVE intrinsics] rework vmaxnmq vminnmqChristophe Lyon4-224/+6
Implement vmaxnmq and vminnmq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmaxnmq, vminnmq): New. * config/arm/arm-mve-builtins-base.def (vmaxnmq, vminnmq): New. * config/arm/arm-mve-builtins-base.h (vmaxnmq, vminnmq): New. * config/arm/arm_mve.h (vminnmq): Remove. (vmaxnmq): Remove. (vmaxnmq_m): Remove. (vminnmq_m): Remove. (vminnmq_x): Remove. (vmaxnmq_x): Remove. (vminnmq_f16): Remove. (vmaxnmq_f16): Remove. (vminnmq_f32): Remove. (vmaxnmq_f32): Remove. (vmaxnmq_m_f32): Remove. (vmaxnmq_m_f16): Remove. (vminnmq_m_f32): Remove. (vminnmq_m_f16): Remove. (vminnmq_x_f16): Remove. (vminnmq_x_f32): Remove. (vmaxnmq_x_f16): Remove. (vmaxnmq_x_f32): Remove. (__arm_vminnmq_f16): Remove. (__arm_vmaxnmq_f16): Remove. (__arm_vminnmq_f32): Remove. (__arm_vmaxnmq_f32): Remove. (__arm_vmaxnmq_m_f32): Remove. (__arm_vmaxnmq_m_f16): Remove. (__arm_vminnmq_m_f32): Remove. (__arm_vminnmq_m_f16): Remove. (__arm_vminnmq_x_f16): Remove. (__arm_vminnmq_x_f32): Remove. (__arm_vmaxnmq_x_f16): Remove. (__arm_vmaxnmq_x_f32): Remove. (__arm_vminnmq): Remove. (__arm_vmaxnmq): Remove. (__arm_vmaxnmq_m): Remove. (__arm_vminnmq_m): Remove. (__arm_vminnmq_x): Remove. (__arm_vmaxnmq_x): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmaxnmq vminnmqChristophe Lyon2-54/+19
Factorize vmaxnmq and vminnmq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MAX_MIN_F): New. (MVE_FP_M_BINARY): Add VMAXNMQ_M_F, VMINNMQ_M_F. (mve_insn): Add vmaxnm, vminnm. (max_min_f_str): New. * config/arm/mve.md (mve_vmaxnmq_f<mode>, mve_vminnmq_f<mode>): Merge into ... (@mve_<max_min_f_str>q_f<mode>): ... this. (mve_vmaxnmq_m_f<mode>, mve_vminnmq_m_f<mode>): Merge into ... (@mve_<mve_insn>q_m_f<mode>): ... this.
2023-05-09arm: add smax/smin expanders for v*hfChristophe Lyon1-6/+6
This patch adds the missing expanders for smax/smin for v*hf modes, by using the VDQWH iterator instead of VALLW. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/vec-common.md (smin<mode>3): Use VDQWH iterator. (smax<mode>3): Likewise.
2023-05-09arm: [MVE intrinsics] rework vmaxvq vminvq vmaxavq vminavqChristophe Lyon4-616/+25
Implement vmaxvq, vminvq, vmaxavq, vminavq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_S_U) (FUNCTION_PRED_P_S): New. (vmaxavq, vminavq, vmaxvq, vminvq): New. * config/arm/arm-mve-builtins-base.def (vmaxavq, vminavq, vmaxvq) (vminvq): New. * config/arm/arm-mve-builtins-base.h (vmaxavq, vminavq, vmaxvq) (vminvq): New. * config/arm/arm_mve.h (vminvq): Remove. (vmaxvq): Remove. (vminvq_p): Remove. (vmaxvq_p): Remove. (vminvq_u8): Remove. (vmaxvq_u8): Remove. (vminvq_s8): Remove. (vmaxvq_s8): Remove. (vminvq_u16): Remove. (vmaxvq_u16): Remove. (vminvq_s16): Remove. (vmaxvq_s16): Remove. (vminvq_u32): Remove. (vmaxvq_u32): Remove. (vminvq_s32): Remove. (vmaxvq_s32): Remove. (vminvq_p_u8): Remove. (vmaxvq_p_u8): Remove. (vminvq_p_s8): Remove. (vmaxvq_p_s8): Remove. (vminvq_p_u16): Remove. (vmaxvq_p_u16): Remove. (vminvq_p_s16): Remove. (vmaxvq_p_s16): Remove. (vminvq_p_u32): Remove. (vmaxvq_p_u32): Remove. (vminvq_p_s32): Remove. (vmaxvq_p_s32): Remove. (__arm_vminvq_u8): Remove. (__arm_vmaxvq_u8): Remove. (__arm_vminvq_s8): Remove. (__arm_vmaxvq_s8): Remove. (__arm_vminvq_u16): Remove. (__arm_vmaxvq_u16): Remove. (__arm_vminvq_s16): Remove. (__arm_vmaxvq_s16): Remove. (__arm_vminvq_u32): Remove. (__arm_vmaxvq_u32): Remove. (__arm_vminvq_s32): Remove. (__arm_vmaxvq_s32): Remove. (__arm_vminvq_p_u8): Remove. (__arm_vmaxvq_p_u8): Remove. (__arm_vminvq_p_s8): Remove. (__arm_vmaxvq_p_s8): Remove. (__arm_vminvq_p_u16): Remove. (__arm_vmaxvq_p_u16): Remove. (__arm_vminvq_p_s16): Remove. (__arm_vmaxvq_p_s16): Remove. (__arm_vminvq_p_u32): Remove. (__arm_vmaxvq_p_u32): Remove. (__arm_vminvq_p_s32): Remove. (__arm_vmaxvq_p_s32): Remove. (__arm_vminvq): Remove. (__arm_vmaxvq): Remove. (__arm_vminvq_p): Remove. (__arm_vmaxvq_p): Remove. (vminavq): Remove. (vmaxavq): Remove. (vminavq_p): Remove. (vmaxavq_p): Remove. (vminavq_s8): Remove. (vmaxavq_s8): Remove. (vminavq_s16): Remove. (vmaxavq_s16): Remove. (vminavq_s32): Remove. (vmaxavq_s32): Remove. (vminavq_p_s8): Remove. (vmaxavq_p_s8): Remove. (vminavq_p_s16): Remove. (vmaxavq_p_s16): Remove. (vminavq_p_s32): Remove. (vmaxavq_p_s32): Remove. (__arm_vminavq_s8): Remove. (__arm_vmaxavq_s8): Remove. (__arm_vminavq_s16): Remove. (__arm_vmaxavq_s16): Remove. (__arm_vminavq_s32): Remove. (__arm_vmaxavq_s32): Remove. (__arm_vminavq_p_s8): Remove. (__arm_vmaxavq_p_s8): Remove. (__arm_vminavq_p_s16): Remove. (__arm_vmaxavq_p_s16): Remove. (__arm_vminavq_p_s32): Remove. (__arm_vmaxavq_p_s32): Remove. (__arm_vminavq): Remove. (__arm_vmaxavq): Remove. (__arm_vminavq_p): Remove. (__arm_vmaxavq_p): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmaxvq vminvq vmaxavq vminavqChristophe Lyon2-101/+40
Factorize vmaxvq vminvq vmaxavq vminavq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VMAXVQ_VMINVQ, MVE_VMAXVQ_VMINVQ_P): New. (mve_insn): Add vmaxav, vmaxv, vminav, vminv. (supf): Add VMAXAVQ_S, VMAXAVQ_P_S, VMINAVQ_S, VMINAVQ_P_S. * config/arm/mve.md (mve_vmaxavq_s<mode>, mve_vmaxvq_<supf><mode>) (mve_vminavq_s<mode>, mve_vminvq_<supf><mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmaxavq_p_s<mode>, mve_vmaxvq_p_<supf><mode>) (mve_vminavq_p_s<mode>, mve_vminvq_p_<supf><mode>): Merge into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-09arm: [MVE intrinsics add unspec_mve_function_exact_insn_pred_pChristophe Lyon1-0/+64
Introduce a function that will be used to build intrinsics that use p predication. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-functions.h (class unspec_mve_function_exact_insn_pred_p): New.
2023-05-09arm: [MVE intrinsics] add binary_maxavminav shapeChristophe Lyon2-0/+31
This patch adds the binary_maxavminav shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_maxavminav): New. * config/arm/arm-mve-builtins-shapes.h (binary_maxavminav): New.
2023-05-09arm: [MVE intrinsics] add binary_maxvminv shapeChristophe Lyon2-0/+31
This patch adds the binary_maxvminv shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_maxvminv): New. * config/arm/arm-mve-builtins-shapes.h (binary_maxvminv): New.
2023-05-09aarch64: Improve register allocation for lane instructionsRichard Sandiford251-368/+413
REG_ALLOC_ORDER is much less important than it used to be, but it is still used as a tie-breaker when multiple registers in a class are equally good. Previously aarch64 used the default approach of allocating in order of increasing register number. But as the comment in the patch says, it's better to allocate FP and predicate registers in the opposite order, so that we don't eat into smaller register classes unnecessarily. This fixes some existing FIXMEs and improves the register allocation for some Arm ACLE code. Doing this also showed that *vcond_mask_<mode><vpred> (predicated MOV/SEL) unnecessarily required p0-p7 rather than p0-p15 for the unpredicated movprfx alternatives. Only the predicated movprfx alternative requires p0-p7 (due to the movprfx itself, rather than due to the main instruction). gcc/ * config/aarch64/aarch64-protos.h (aarch64_adjust_reg_alloc_order): Declare. * config/aarch64/aarch64.h (REG_ALLOC_ORDER): Define. (ADJUST_REG_ALLOC_ORDER): Likewise. * config/aarch64/aarch64.cc (aarch64_adjust_reg_alloc_order): New function. * config/aarch64/aarch64-sve.md (*vcond_mask_<mode><vpred>): Use Upa rather than Upl for unpredicated movprfx alternatives. gcc/testsuite/ * gcc.target/aarch64/sve/acle/asm/abd_f16.c: Remove XFAILs. * gcc.target/aarch64/sve/acle/asm/abd_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/asr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/asr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/divr_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f16_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f32_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_f64_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulx_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulx_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulx_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmad_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmad_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmad_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmla_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmla_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmla_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmls_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmls_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmls_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmsb_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmsb_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/nmsb_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f16_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f32_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_f64_notrap.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalb_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c: Likewise.
2023-05-09aarch64: Fix cut-&-pasto in aarch64-sve2-acle-asm.expRichard Sandiford1-1/+1
aarch64-sve2-acle-asm.exp tried to prevent --with-cpu/tune from affecting the results, but it used sve_flags rather than sve2_flags. This was a silent failure when running the full testsuite, but was a fatal error when running the harness individually. gcc/testsuite/ * gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Use sve2_flags instead of sve_flags.
2023-05-09PR modula2/109779 isolib SkipLine skips the first character of the ↵Gaius Mulley3-67/+141
successive line This is a patch for the m2iso library to prevent SkipLine from consuming the next character on the next line. gcc/m2/ChangeLog: PR modula2/109779 * gm2-libs-iso/RTgen.mod (doLook): Remove old. Remove re-assignment of result. * gm2-libs-iso/TextIO.mod (CanRead): Rename into ... (CharAvailable): ... this. (DumpState): New procedure. (SetResult): Rename as SetNul. (WasGoodChar): Rename into ... (EofOrEoln): ... this. (SkipLine): Skip over the newline. (ReadString): Flip THEN ELSE statements after testing for EofOrEoln. (ReadRestLine): Flip THEN ELSE statements after testing for EofOrEoln. gcc/testsuite/ChangeLog: PR modula2/109779 * gm2/isolib/run/pass/skiplinetest.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-05-09c++: Reject pack expansion of assume attribute [PR109756]Jakub Jelinek2-0/+32
http://eel.is/c++draft/dcl.attr#grammar-4 says "In an attribute-list, an ellipsis may appear only if that attribute's specification permits it." and doesn't explicitly permit it on any standard attribute. The https://wg21.link/p1774r8 paper which introduced assume attribute says "We could therefore hypothetically permit the assume attribute to directly support pack expansion: template <int... args> void f() { [[assume(args >= 0)...]]; } However, we do not propose this. It would require substantial additional work for a very rare use case. Note that this can instead be expressed with a fold expression, which is equivalent to the above and works out of the box without any extra effort: template <int... args> void f() { [[assume(((args >= 0) && ...))]]; } ", but as the testcase shows, GCC 13+ ICEs on assume attribute followed by ... if it contains packs. The following patch rejects those instead of ICE and for C++17 or later suggests using fold expressions instead (it doesn't make sense to suggest it for C++14 and earlier when we'd error on the fold expressions). 2023-05-09 Jakub Jelinek <jakub@redhat.com> PR c++/109756 * cp-gimplify.cc (process_stmt_assume_attribute): Diagnose pack expansion of assume attribute. * g++.dg/cpp23/attr-assume11.C: New test.
2023-05-09Eliminate more comparisons on the H8 portJeff Law1-1/+13
This patch fixes a minor code quality issue I found while testing LRA on the H8. Specifically we have a peephole which converts a comparison of a memory location against zero into a load + comparison which is actually more efficient. This triggers when there are registers available at the right point during peephole2. If the load is not a mode dependent address we can actually do better by realizing the load itself sets the proper flags and eliminate the comparison. I may have expected this to happen when I wrote the original peephole2, but cmpelim runs before peephole2, so clearly if we want to eliminate the comparison we have to do it manually. gcc/ * config/h8300/testcompare.md: Add peephole2 which uses a memory load to set flags, thus eliminating a compare against zero.
2023-05-09libgomp testsuite: Use 'lang_test_file_found' instead of 'lang_test_file'Thomas Schwinge8-24/+8
The value of 'lang_test_file' isn't actually used anywhere. libgomp/ * testsuite/libgomp.c++/c++.exp: Don't set 'lang_test_file'. * testsuite/libgomp.fortran/fortran.exp: Likewise. * testsuite/libgomp.oacc-c++/c++.exp: Likewise. * testsuite/libgomp.oacc-fortran/fortran.exp: Likewise. * testsuite/libgomp.c/c.exp: Unset 'lang_test_file_found' instead of 'lang_test_file'. * testsuite/libgomp.oacc-c/c.exp: Likewise. * testsuite/libgomp.graphite/graphite.exp: Likewise. * testsuite/lib/libgomp.exp (libgomp_target_compile): Look for 'lang_test_file_found' instead of 'lang_test_file'.
2023-05-09libgomp testsuite: Only use 'blddir' if setThomas Schwinge3-4/+7
(It is unclear to me why the current working directory needs to be in 'LD_LIBRARY_PATH'; leaving that alone for now.) libgomp/ * testsuite/lib/libgomp.exp (libgomp_init): Only use 'blddir' if set. * testsuite/libgomp.c++/c++.exp: Likewise. * testsuite/libgomp.oacc-c++/c++.exp: Likewise.
2023-05-09libgomp C++ testsuite: Don't compute 'blddir' twiceThomas Schwinge2-6/+0
It has already been set in 'libgomp/testsuite/lib/libgomp.exp:libgomp_init'. libgomp/ * testsuite/libgomp.c++/c++.exp (blddir): Don't set. * testsuite/libgomp.oacc-c++/c++.exp (blddir): Likewise.
2023-05-09arm: [MVE intrinsics] rework vshllbq vshlltqChristophe Lyon4-424/+6
Implement vshllbq and vshlltq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vshllbq, vshlltq): New. * config/arm/arm-mve-builtins-base.def (vshllbq, vshlltq): New. * config/arm/arm-mve-builtins-base.h (vshllbq, vshlltq): New. * config/arm/arm_mve.h (vshlltq): Remove. (vshllbq): Remove. (vshllbq_m): Remove. (vshlltq_m): Remove. (vshllbq_x): Remove. (vshlltq_x): Remove. (vshlltq_n_u8): Remove. (vshllbq_n_u8): Remove. (vshlltq_n_s8): Remove. (vshllbq_n_s8): Remove. (vshlltq_n_u16): Remove. (vshllbq_n_u16): Remove. (vshlltq_n_s16): Remove. (vshllbq_n_s16): Remove. (vshllbq_m_n_s8): Remove. (vshllbq_m_n_s16): Remove. (vshllbq_m_n_u8): Remove. (vshllbq_m_n_u16): Remove. (vshlltq_m_n_s8): Remove. (vshlltq_m_n_s16): Remove. (vshlltq_m_n_u8): Remove. (vshlltq_m_n_u16): Remove. (vshllbq_x_n_s8): Remove. (vshllbq_x_n_s16): Remove. (vshllbq_x_n_u8): Remove. (vshllbq_x_n_u16): Remove. (vshlltq_x_n_s8): Remove. (vshlltq_x_n_s16): Remove. (vshlltq_x_n_u8): Remove. (vshlltq_x_n_u16): Remove. (__arm_vshlltq_n_u8): Remove. (__arm_vshllbq_n_u8): Remove. (__arm_vshlltq_n_s8): Remove. (__arm_vshllbq_n_s8): Remove. (__arm_vshlltq_n_u16): Remove. (__arm_vshllbq_n_u16): Remove. (__arm_vshlltq_n_s16): Remove. (__arm_vshllbq_n_s16): Remove. (__arm_vshllbq_m_n_s8): Remove. (__arm_vshllbq_m_n_s16): Remove. (__arm_vshllbq_m_n_u8): Remove. (__arm_vshllbq_m_n_u16): Remove. (__arm_vshlltq_m_n_s8): Remove. (__arm_vshlltq_m_n_s16): Remove. (__arm_vshlltq_m_n_u8): Remove. (__arm_vshlltq_m_n_u16): Remove. (__arm_vshllbq_x_n_s8): Remove. (__arm_vshllbq_x_n_s16): Remove. (__arm_vshllbq_x_n_u8): Remove. (__arm_vshllbq_x_n_u16): Remove. (__arm_vshlltq_x_n_s8): Remove. (__arm_vshlltq_x_n_s16): Remove. (__arm_vshlltq_x_n_u8): Remove. (__arm_vshlltq_x_n_u16): Remove. (__arm_vshlltq): Remove. (__arm_vshllbq): Remove. (__arm_vshllbq_m): Remove. (__arm_vshlltq_m): Remove. (__arm_vshllbq_x): Remove. (__arm_vshlltq_x): Remove.
2023-05-09arm: [MVE intrinsics] factorize vshllbq vshlltqChristophe Lyon2-44/+16
Factorize vshllbq vshlltq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vshllb, vshllt. (VSHLLBQ_N, VSHLLTQ_N): Remove. (VSHLLxQ_N): New. (VSHLLBQ_M_N, VSHLLTQ_M_N): Remove. (VSHLLxQ_M_N): New. * config/arm/mve.md (mve_vshllbq_n_<supf><mode>) (mve_vshlltq_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vshllbq_m_n_<supf><mode>, mve_vshlltq_m_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-09arm: [MVE intrinsics] add binary_widen_n shapeChristophe Lyon2-0/+54
This patch adds the binary_widen_n shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_widen_n): New. * config/arm/arm-mve-builtins-shapes.h (binary_widen_n): New.
2023-05-09arm: [MVE intrinsics] rework vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq ↵Christophe Lyon5-789/+25
vqmovuntq Implement vmovnbq, vmovntq, vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmovnbq, vmovntq, vqmovnbq) (vqmovntq, vqmovunbq, vqmovuntq): New. * config/arm/arm-mve-builtins-base.def (vmovnbq, vmovntq) (vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq): New. * config/arm/arm-mve-builtins-base.h (vmovnbq, vmovntq, vqmovnbq) (vqmovntq, vqmovunbq, vqmovuntq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vmovnbq, vmovntq, vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq. * config/arm/arm_mve.h (vqmovntq): Remove. (vqmovnbq): Remove. (vqmovnbq_m): Remove. (vqmovntq_m): Remove. (vqmovntq_u16): Remove. (vqmovnbq_u16): Remove. (vqmovntq_s16): Remove. (vqmovnbq_s16): Remove. (vqmovntq_u32): Remove. (vqmovnbq_u32): Remove. (vqmovntq_s32): Remove. (vqmovnbq_s32): Remove. (vqmovnbq_m_s16): Remove. (vqmovntq_m_s16): Remove. (vqmovnbq_m_u16): Remove. (vqmovntq_m_u16): Remove. (vqmovnbq_m_s32): Remove. (vqmovntq_m_s32): Remove. (vqmovnbq_m_u32): Remove. (vqmovntq_m_u32): Remove. (__arm_vqmovntq_u16): Remove. (__arm_vqmovnbq_u16): Remove. (__arm_vqmovntq_s16): Remove. (__arm_vqmovnbq_s16): Remove. (__arm_vqmovntq_u32): Remove. (__arm_vqmovnbq_u32): Remove. (__arm_vqmovntq_s32): Remove. (__arm_vqmovnbq_s32): Remove. (__arm_vqmovnbq_m_s16): Remove. (__arm_vqmovntq_m_s16): Remove. (__arm_vqmovnbq_m_u16): Remove. (__arm_vqmovntq_m_u16): Remove. (__arm_vqmovnbq_m_s32): Remove. (__arm_vqmovntq_m_s32): Remove. (__arm_vqmovnbq_m_u32): Remove. (__arm_vqmovntq_m_u32): Remove. (__arm_vqmovntq): Remove. (__arm_vqmovnbq): Remove. (__arm_vqmovnbq_m): Remove. (__arm_vqmovntq_m): Remove. (vmovntq): Remove. (vmovnbq): Remove. (vmovnbq_m): Remove. (vmovntq_m): Remove. (vmovntq_u16): Remove. (vmovnbq_u16): Remove. (vmovntq_s16): Remove. (vmovnbq_s16): Remove. (vmovntq_u32): Remove. (vmovnbq_u32): Remove. (vmovntq_s32): Remove. (vmovnbq_s32): Remove. (vmovnbq_m_s16): Remove. (vmovntq_m_s16): Remove. (vmovnbq_m_u16): Remove. (vmovntq_m_u16): Remove. (vmovnbq_m_s32): Remove. (vmovntq_m_s32): Remove. (vmovnbq_m_u32): Remove. (vmovntq_m_u32): Remove. (__arm_vmovntq_u16): Remove. (__arm_vmovnbq_u16): Remove. (__arm_vmovntq_s16): Remove. (__arm_vmovnbq_s16): Remove. (__arm_vmovntq_u32): Remove. (__arm_vmovnbq_u32): Remove. (__arm_vmovntq_s32): Remove. (__arm_vmovnbq_s32): Remove. (__arm_vmovnbq_m_s16): Remove. (__arm_vmovntq_m_s16): Remove. (__arm_vmovnbq_m_u16): Remove. (__arm_vmovntq_m_u16): Remove. (__arm_vmovnbq_m_s32): Remove. (__arm_vmovntq_m_s32): Remove. (__arm_vmovnbq_m_u32): Remove. (__arm_vmovntq_m_u32): Remove. (__arm_vmovntq): Remove. (__arm_vmovnbq): Remove. (__arm_vmovnbq_m): Remove. (__arm_vmovntq_m): Remove. (vqmovuntq): Remove. (vqmovunbq): Remove. (vqmovunbq_m): Remove. (vqmovuntq_m): Remove. (vqmovuntq_s16): Remove. (vqmovunbq_s16): Remove. (vqmovuntq_s32): Remove. (vqmovunbq_s32): Remove. (vqmovunbq_m_s16): Remove. (vqmovuntq_m_s16): Remove. (vqmovunbq_m_s32): Remove. (vqmovuntq_m_s32): Remove. (__arm_vqmovuntq_s16): Remove. (__arm_vqmovunbq_s16): Remove. (__arm_vqmovuntq_s32): Remove. (__arm_vqmovunbq_s32): Remove. (__arm_vqmovunbq_m_s16): Remove. (__arm_vqmovuntq_m_s16): Remove. (__arm_vqmovunbq_m_s32): Remove. (__arm_vqmovuntq_m_s32): Remove. (__arm_vqmovuntq): Remove. (__arm_vqmovunbq): Remove. (__arm_vqmovunbq_m): Remove. (__arm_vqmovuntq_m): Remove.
2023-05-09arm: [MVE intrinsics] factorize vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq ↵Christophe Lyon2-162/+64
vqmovuntq Factorize vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq vqmovuntq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_MOVN, MVE_MOVN_M): New. (mve_insn): Add vmovnb, vmovnt, vqmovnb, vqmovnt, vqmovunb, vqmovunt. (isu): Likewise. (supf): Add VQMOVUNBQ_M_S, VQMOVUNBQ_S, VQMOVUNTQ_M_S, VQMOVUNTQ_S. * config/arm/mve.md (mve_vmovnbq_<supf><mode>) (mve_vmovntq_<supf><mode>, mve_vqmovnbq_<supf><mode>) (mve_vqmovntq_<supf><mode>, mve_vqmovunbq_s<mode>) (mve_vqmovuntq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmovnbq_m_<supf><mode>, mve_vmovntq_m_<supf><mode>) (mve_vqmovnbq_m_<supf><mode>, mve_vqmovntq_m_<supf><mode>) (mve_vqmovunbq_m_s<mode>, mve_vqmovuntq_m_s<mode>): Merge into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-09arm: [MVE intrinsics] add binary_move_narrow and binary_move_narrow_unsigned ↵Christophe Lyon2-0/+75
shapes This patch adds the binary_move_narrow and binary_move_narrow_unsigned shapes descriptions. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_move_narrow): New. (binary_move_narrow_unsigned): New. * config/arm/arm-mve-builtins-shapes.h (binary_move_narrow): New. (binary_move_narrow_unsigned): New.
generated by cgit v1.1 at 2025-09-19 01:08:16 +0000