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2023-05-11c++: converted lambda as template argument [PR83258, ...]Patrick Palka5-4/+32
r8-1253-g3d2e25a240c711 removed the template argument linkage requirement in convert_nontype_argument for C++17 (which r9-3836-g4be5c72cf3ea3e later factored out into invalid_tparm_referent_p), but we need to also remove the one in convert_nontype_argument_function for benefit of the first and third testcase which we currently reject even in C++17/20 mode. And in invalid_tparm_referent_p we're inadvertendly returning false for the address of a lambda's static op() since it's DECL_ARTIFICIAL, which currently causes us to reject the second (C++20) testcase. But this DECL_ARTIFICIAL check seems to be relevant only for VAR_DECL, and in fact this code path was originally reachable only for VAR_DECL until recently (r13-6970-gb5e38b1c166357). So this patch restricts the check to VAR_DECL. Co-authored-by: Jonathan Wakely <jwakely@redhat.com> PR c++/83258 PR c++/80488 PR c++/97700 gcc/cp/ChangeLog: * pt.cc (convert_nontype_argument_function): Remove linkage requirement for C++17 and later. (invalid_tparm_referent_p) <case ADDR_EXPR>: Restrict DECL_ARTIFICIAL rejection test to VAR_DECL. gcc/testsuite/ChangeLog: * g++.dg/ext/visibility/anon8.C: Don't expect a "no linkage" error for the template argument &B2:fn in C++17 mode. * g++.dg/cpp0x/lambda/lambda-conv15.C: New test. * g++.dg/cpp2a/nontype-class56.C: New test. * g++.dg/template/function2.C: New test.
2023-05-11[vxworks] [testsuite] [aarch64] use builtin in pred-not-gen-4.cAlexandre Oliva1-3/+1
On vxworks, isunordered is defined as a macro that ultimately calls a _Fpcomp function, that GCC doesn't recognize as a builtin, so it can't optimize accordingly. Use __builtin_isunordered instead to get the desired code for the test. for gcc/testsuite/ChangeLog * gcc.target/aarch64/sve/pred-not-gen-4.c: Drop math.h include, call builtin.
2023-05-11MAINTAINERS: Fix alphabetic sorting.Robin Dapp1-1/+1
ChangeLog: * MAINTAINERS: Sort.
2023-05-11RISC-V: Update RVV integer compare simplification commentsPan Li1-1/+8
The VMSET simplification RVV integer comparision has merged already. This patch would like to update the comments for the cases that the define_split will act on. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * config/riscv/vector.md: Add comments for simplifying to vmset. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-11RISC-V: Add autovectorization tests for binary integer operations.Robin Dapp59-0/+1375
This patchs adds scan as well as execution tests for vectorized binary integer operations. The tests are not comprehensive as the vector type promotions (vec_unpack, extend etc.) are not implemented yet. Also, vmulh, vmulhu, and vmulhsu and others are still missing. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/shift-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/shift-template.h: New test. * gcc.target/riscv/rvv/autovec/shift-run.c: New test. * gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/shift-scalar-template.h: New test. * gcc.target/riscv/rvv/autovec/shift-scalar-run.c: New test. * gcc.target/riscv/rvv/autovec/vadd-run-template.h: New test. * gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vadd-template.h: New test. * gcc.target/riscv/rvv/autovec/vand-run.c: New test. * gcc.target/riscv/rvv/autovec/vand-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vand-template.h: New test. * gcc.target/riscv/rvv/autovec/vdiv-run.c: New test. * gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vdiv-template.h: New test. * gcc.target/riscv/rvv/autovec/vmax-run.c: New test. * gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmax-template.h: New test. * gcc.target/riscv/rvv/autovec/vmin-run.c: New test. * gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmin-template.h: New test. * gcc.target/riscv/rvv/autovec/vmul-run.c: New test. * gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vmul-template.h: New test. * gcc.target/riscv/rvv/autovec/vor-run.c: New test. * gcc.target/riscv/rvv/autovec/vor-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vor-template.h: New test. * gcc.target/riscv/rvv/autovec/vrem-run.c: New test. * gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vrem-template.h: New test. * gcc.target/riscv/rvv/autovec/vsub-run.c: New test. * gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vsub-template.h: New test. * gcc.target/riscv/rvv/autovec/vxor-run.c: New test. * gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/vxor-template.h: New test. Co-authored-by: Michael Collison <collison@rivosinc.com>
2023-05-11RISC-V: Split off shift patterns for autovectorization.Robin Dapp2-1/+50
This patch splits off the shift patterns of the binop patterns. This is necessary as the scalar shifts require a Pmode operand as shift count. To this end, a new iterator any_int_binop_no_shift is introduced. At a later point when the binops are split up further in commutative and non-commutative patterns (which both do not include the shift patterns) we might not need this anymore. gcc/ChangeLog: * config/riscv/autovec.md (<optab><mode>3): Add scalar shift pattern. (v<optab><mode>3): Add vector shift pattern. * config/riscv/vector-iterators.md: New iterator.
2023-05-11RISC-V: Clarify vlmax and length handling.Robin Dapp5-61/+83
This patch tries to improve the wrappers that emit either vlmax or non-vlmax operations. Now, emit_len_op can be used to emit a regular operation. Depending on whether a length != NULL is passed either no VLMAX flags are set or we emit a vsetvli and set VLMAX flags. The patch also adds some comments that describes some of the rationale of the current handling of vlmax/nonvlmax operations. gcc/ChangeLog: * config/riscv/autovec.md: Use renamed functions. * config/riscv/riscv-protos.h (emit_vlmax_op): Rename. (emit_vlmax_reg_op): To this. (emit_nonvlmax_op): Rename. (emit_len_op): To this. (emit_nonvlmax_binop): Rename. (emit_len_binop): To this. * config/riscv/riscv-v.cc (emit_pred_op): Add default parameter. (emit_pred_binop): Remove vlmax_p. (emit_vlmax_op): Rename. (emit_vlmax_reg_op): To this. (emit_nonvlmax_op): Rename. (emit_len_op): To this. (emit_nonvlmax_binop): Rename. (emit_len_binop): To this. (sew64_scalar_helper): Use renamed functions. (expand_tuple_move): Use renamed functions. * config/riscv/riscv.cc (vector_zero_call_used_regs): Use renamed functions. * config/riscv/vector.md: Use renamed functions.
2023-05-11RISC-V: Add vectorized binops and insn_expander helpers.Robin Dapp3-64/+123
This patch adds basic binary integer operations support. It is based on Michael Collison's work and makes use of the existing helpers in riscv-c.cc. It introduces emit_nonvlmax_binop which, in turn, uses emit_pred_binop. Setting the destination as well as the mask and the length are factored out into separate functions. gcc/ChangeLog: * config/riscv/autovec.md (<optab><mode>3): Add integer binops. * config/riscv/riscv-protos.h (emit_nonvlmax_binop): Declare. * config/riscv/riscv-v.cc (emit_pred_op): New function. (set_expander_dest_and_mask): New function. (emit_pred_binop): New function. (emit_nonvlmax_binop): New function. Co-authored-by: Michael Collison <collison@rivosinc.com>
2023-05-11libstdc++: Fix std::abs(__float128) for -NaN and -0.0 [PR109758]Jonathan Wakely2-2/+63
The current implementation of this non-standard overload of std::abs incorrectly returns a negative value for negative NaNs and negative zero, because x < 0 is false in both cases. Use fabsl(long double) or fabsf128(_Float128) if those do the right thing. Otherwise, use __builtin_signbit(x) instead of x < 0 to detect negative inputs. This assumes that __builtin_signbit handles __float128 correctly, but that seems to be true for all of GCC, clang and icc. libstdc++-v3/ChangeLog: PR libstdc++/109758 * include/bits/std_abs.h (abs(__float128)): Handle negative NaN and negative zero correctly. * testsuite/26_numerics/headers/cmath/109758.cc: New test.
2023-05-11VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IVPan Li10-26/+29
This patch is going to be commited after bootstrap && regression on X86 PASSED. Thanks Richards. gcc/ChangeLog: * cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR. * gimple-loop-interchange.cc (tree_loop_interchange::map_inductions_to_loop): Ditto. * tree-ssa-loop-ivcanon.cc (create_canonical_iv): Ditto. * tree-ssa-loop-ivopts.cc (create_new_iv): Ditto. * tree-ssa-loop-manip.cc (create_iv): Ditto. (tree_transform_and_unroll_loop): Ditto. (canonicalize_loop_ivs): Ditto. * tree-ssa-loop-manip.h (create_iv): Ditto. * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Ditto. * tree-vect-loop-manip.cc (vect_set_loop_controls_directly): Ditto. (vect_set_loop_condition_normal): Ditto. * tree-vect-loop.cc (vect_create_epilog_for_reduction): Ditto. * tree-vect-stmts.cc (vectorizable_store): Ditto. (vectorizable_load): Ditto. Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
2023-05-11fortran: use grep instead of fgrepXi Ruoyao1-1/+1
fgrep has been deprecated in favor of grep -F for a long time, and the curren grep release (3.10) prints a warning of fgrep is used. Stop using fgrep so we won't see the warning. We can't hard code grep -F here or it may break build on hosts w/o GNU grep. autoconf documentation contains a warning about this issue and suggest to use AC_PROG_FGREP and $FGREP, but these are too overkill in the specific case: there is no way "debian" could be interpreted as an non-trivial regex, so we can use a plain grep here. gcc/fortran/ChangeLog: * Make-lang.in: Use grep instead of fgrep.
2023-05-11arm: [MVE intrinsics] rework vmovlbq vmovltqChristophe Lyon4-454/+6
Implement vmovlbq, vmovltq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmovlbq, vmovltq): New. * config/arm/arm-mve-builtins-base.def (vmovlbq, vmovltq): New. * config/arm/arm-mve-builtins-base.h (vmovlbq, vmovltq): New. * config/arm/arm_mve.h (vmovlbq): Remove. (vmovltq): Remove. (vmovlbq_m): Remove. (vmovltq_m): Remove. (vmovlbq_x): Remove. (vmovltq_x): Remove. (vmovlbq_s8): Remove. (vmovlbq_s16): Remove. (vmovltq_s8): Remove. (vmovltq_s16): Remove. (vmovltq_u8): Remove. (vmovltq_u16): Remove. (vmovlbq_u8): Remove. (vmovlbq_u16): Remove. (vmovlbq_m_s8): Remove. (vmovltq_m_s8): Remove. (vmovlbq_m_u8): Remove. (vmovltq_m_u8): Remove. (vmovlbq_m_s16): Remove. (vmovltq_m_s16): Remove. (vmovlbq_m_u16): Remove. (vmovltq_m_u16): Remove. (vmovlbq_x_s8): Remove. (vmovlbq_x_s16): Remove. (vmovlbq_x_u8): Remove. (vmovlbq_x_u16): Remove. (vmovltq_x_s8): Remove. (vmovltq_x_s16): Remove. (vmovltq_x_u8): Remove. (vmovltq_x_u16): Remove. (__arm_vmovlbq_s8): Remove. (__arm_vmovlbq_s16): Remove. (__arm_vmovltq_s8): Remove. (__arm_vmovltq_s16): Remove. (__arm_vmovltq_u8): Remove. (__arm_vmovltq_u16): Remove. (__arm_vmovlbq_u8): Remove. (__arm_vmovlbq_u16): Remove. (__arm_vmovlbq_m_s8): Remove. (__arm_vmovltq_m_s8): Remove. (__arm_vmovlbq_m_u8): Remove. (__arm_vmovltq_m_u8): Remove. (__arm_vmovlbq_m_s16): Remove. (__arm_vmovltq_m_s16): Remove. (__arm_vmovlbq_m_u16): Remove. (__arm_vmovltq_m_u16): Remove. (__arm_vmovlbq_x_s8): Remove. (__arm_vmovlbq_x_s16): Remove. (__arm_vmovlbq_x_u8): Remove. (__arm_vmovlbq_x_u16): Remove. (__arm_vmovltq_x_s8): Remove. (__arm_vmovltq_x_s16): Remove. (__arm_vmovltq_x_u8): Remove. (__arm_vmovltq_x_u16): Remove. (__arm_vmovlbq): Remove. (__arm_vmovltq): Remove. (__arm_vmovlbq_m): Remove. (__arm_vmovltq_m): Remove. (__arm_vmovlbq_x): Remove. (__arm_vmovltq_x): Remove.
2023-05-11arm: [MVE intrinsics] add unary_widen shapeChristophe Lyon2-0/+47
This patch adds the unary_widen shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_widen): New. * config/arm/arm-mve-builtins-shapes.h (unary_widen): New.
2023-05-11arm: [MVE intrinsics] factorize vmovlbq vmovltqChristophe Lyon2-39/+15
Factorize vmovlbq, vmovltq builtins so that they use the same parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vmovlb, vmovlt. (VMOVLBQ, VMOVLTQ): Merge into ... (VMOVLxQ): ... this. (VMOVLTQ_M, VMOVLBQ_M): Merge into ... (VMOVLxQ_M): ... this. * config/arm/mve.md (mve_vmovltq_<supf><mode>) (mve_vmovlbq_<supf><mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vmovlbq_m_<supf><mode>, mve_vmovltq_m_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] rework vaddlvqChristophe Lyon5-93/+51
Implement vaddlvq using the new MVE builtins framework. Since we kept v4si hardcoded in the builtin name, we need to special-case it in unspec_mve_function_exact_insn_pred_p. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vaddlvq): New. * config/arm/arm-mve-builtins-base.def (vaddlvq): New. * config/arm/arm-mve-builtins-base.h (vaddlvq): New. * config/arm/arm-mve-builtins-functions.h (unspec_mve_function_exact_insn_pred_p): Handle vaddlvq. * config/arm/arm_mve.h (vaddlvq): Remove. (vaddlvq_p): Remove. (vaddlvq_s32): Remove. (vaddlvq_u32): Remove. (vaddlvq_p_s32): Remove. (vaddlvq_p_u32): Remove. (__arm_vaddlvq_s32): Remove. (__arm_vaddlvq_u32): Remove. (__arm_vaddlvq_p_s32): Remove. (__arm_vaddlvq_p_u32): Remove. (__arm_vaddlvq): Remove. (__arm_vaddlvq_p): Remove.
2023-05-11arm: [MVE intrinsics] factorize vaddlvqChristophe Lyon2-4/+6
Factorize vaddlvq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vaddlv. * config/arm/mve.md (mve_vaddlvq_<supf>v4si): Rename into ... (@mve_<mve_insn>q_<supf>v4si): ... this. (mve_vaddlvq_p_<supf>v4si): Rename into ... (@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-11arm: [MVE intrinsics] add unary_acc shapeChristophe Lyon2-0/+29
This patch adds the unary_acc shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_acc): New. * config/arm/arm-mve-builtins-shapes.h (unary_acc): New.
2023-05-11arm: [MVE intrinsics] rework vaddvaqChristophe Lyon4-202/+3
Implement vaddvaq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vaddvaq): New. * config/arm/arm-mve-builtins-base.def (vaddvaq): New. * config/arm/arm-mve-builtins-base.h (vaddvaq): New. * config/arm/arm_mve.h (vaddvaq): Remove. (vaddvaq_p): Remove. (vaddvaq_u8): Remove. (vaddvaq_s8): Remove. (vaddvaq_u16): Remove. (vaddvaq_s16): Remove. (vaddvaq_u32): Remove. (vaddvaq_s32): Remove. (vaddvaq_p_u8): Remove. (vaddvaq_p_s8): Remove. (vaddvaq_p_u16): Remove. (vaddvaq_p_s16): Remove. (vaddvaq_p_u32): Remove. (vaddvaq_p_s32): Remove. (__arm_vaddvaq_u8): Remove. (__arm_vaddvaq_s8): Remove. (__arm_vaddvaq_u16): Remove. (__arm_vaddvaq_s16): Remove. (__arm_vaddvaq_u32): Remove. (__arm_vaddvaq_s32): Remove. (__arm_vaddvaq_p_u8): Remove. (__arm_vaddvaq_p_s8): Remove. (__arm_vaddvaq_p_u16): Remove. (__arm_vaddvaq_p_s16): Remove. (__arm_vaddvaq_p_u32): Remove. (__arm_vaddvaq_p_s32): Remove. (__arm_vaddvaq): Remove. (__arm_vaddvaq_p): Remove.
2023-05-11arm: [MVE intrinsics] add unary_int32_acc shapeChristophe Lyon2-0/+35
This patch adds the unary_int32_acc shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_int32_acc): New. * config/arm/arm-mve-builtins-shapes.h (unary_int32_acc): New.
2023-05-11arm: [MVE intrinsics] factorize vaddvaqChristophe Lyon2-4/+6
Factorize vaddvaq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vaddva. * config/arm/mve.md (mve_vaddvaq_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vaddvaq_p_<supf><mode>): Rename into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11arm: [MVE intrinsics] rework vaddvqChristophe Lyon4-200/+3
Implement vaddvq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vaddvq): New. * config/arm/arm-mve-builtins-base.def (vaddvq): New. * config/arm/arm-mve-builtins-base.h (vaddvq): New. * config/arm/arm_mve.h (vaddvq): Remove. (vaddvq_p): Remove. (vaddvq_s8): Remove. (vaddvq_s16): Remove. (vaddvq_s32): Remove. (vaddvq_u8): Remove. (vaddvq_u16): Remove. (vaddvq_u32): Remove. (vaddvq_p_u8): Remove. (vaddvq_p_s8): Remove. (vaddvq_p_u16): Remove. (vaddvq_p_s16): Remove. (vaddvq_p_u32): Remove. (vaddvq_p_s32): Remove. (__arm_vaddvq_s8): Remove. (__arm_vaddvq_s16): Remove. (__arm_vaddvq_s32): Remove. (__arm_vaddvq_u8): Remove. (__arm_vaddvq_u16): Remove. (__arm_vaddvq_u32): Remove. (__arm_vaddvq_p_u8): Remove. (__arm_vaddvq_p_s8): Remove. (__arm_vaddvq_p_u16): Remove. (__arm_vaddvq_p_s16): Remove. (__arm_vaddvq_p_u32): Remove. (__arm_vaddvq_p_s32): Remove. (__arm_vaddvq): Remove. (__arm_vaddvq_p): Remove.
2023-05-11arm: [MVE intrinsics] add unary_int32 shapeChristophe Lyon2-0/+28
This patch adds the unary_int32 shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_int32): New. * config/arm/arm-mve-builtins-shapes.h (unary_int32): New.
2023-05-11arm: [MVE intrinsics] factorize vaddvqChristophe Lyon3-5/+7
Factorize vaddvq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vaddv. * config/arm/mve.md (@mve_vaddvq_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vaddvq_p_<supf><mode>): Rename into ... (@mve_<mve_insn>q_p_<supf><mode>): ... this. * config/arm/vec-common.md: Use gen_mve_q instead of gen_mve_vaddvq.
2023-05-11arm: [MVE intrinsics] rework vdupqChristophe Lyon4-333/+13
Implement vdupq using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N): New. (vdupq): New. * config/arm/arm-mve-builtins-base.def (vdupq): New. * config/arm/arm-mve-builtins-base.h: (vdupq): New. * config/arm/arm_mve.h (vdupq_n): Remove. (vdupq_m): Remove. (vdupq_n_f16): Remove. (vdupq_n_f32): Remove. (vdupq_n_s8): Remove. (vdupq_n_s16): Remove. (vdupq_n_s32): Remove. (vdupq_n_u8): Remove. (vdupq_n_u16): Remove. (vdupq_n_u32): Remove. (vdupq_m_n_u8): Remove. (vdupq_m_n_s8): Remove. (vdupq_m_n_u16): Remove. (vdupq_m_n_s16): Remove. (vdupq_m_n_u32): Remove. (vdupq_m_n_s32): Remove. (vdupq_m_n_f16): Remove. (vdupq_m_n_f32): Remove. (vdupq_x_n_s8): Remove. (vdupq_x_n_s16): Remove. (vdupq_x_n_s32): Remove. (vdupq_x_n_u8): Remove. (vdupq_x_n_u16): Remove. (vdupq_x_n_u32): Remove. (vdupq_x_n_f16): Remove. (vdupq_x_n_f32): Remove. (__arm_vdupq_n_s8): Remove. (__arm_vdupq_n_s16): Remove. (__arm_vdupq_n_s32): Remove. (__arm_vdupq_n_u8): Remove. (__arm_vdupq_n_u16): Remove. (__arm_vdupq_n_u32): Remove. (__arm_vdupq_m_n_u8): Remove. (__arm_vdupq_m_n_s8): Remove. (__arm_vdupq_m_n_u16): Remove. (__arm_vdupq_m_n_s16): Remove. (__arm_vdupq_m_n_u32): Remove. (__arm_vdupq_m_n_s32): Remove. (__arm_vdupq_x_n_s8): Remove. (__arm_vdupq_x_n_s16): Remove. (__arm_vdupq_x_n_s32): Remove. (__arm_vdupq_x_n_u8): Remove. (__arm_vdupq_x_n_u16): Remove. (__arm_vdupq_x_n_u32): Remove. (__arm_vdupq_n_f16): Remove. (__arm_vdupq_n_f32): Remove. (__arm_vdupq_m_n_f16): Remove. (__arm_vdupq_m_n_f32): Remove. (__arm_vdupq_x_n_f16): Remove. (__arm_vdupq_x_n_f32): Remove. (__arm_vdupq_n): Remove. (__arm_vdupq_m): Remove.
2023-05-11arm: [MVE intrinsics] add unary_n shapeChristophe Lyon2-0/+54
This patch adds the unary_n shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (unary_n): New. * config/arm/arm-mve-builtins-shapes.h (unary_n): New.
2023-05-11arm: [MVE intrinsics] factorize vdupqChristophe Lyon2-10/+20
Factorize vdup builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_FP_M_N_VDUPQ_ONLY) (MVE_FP_N_VDUPQ_ONLY): New. (mve_insn): Add vdupq. * config/arm/mve.md (mve_vdupq_n_f<mode>): Rename into ... (@mve_<mve_insn>q_n_f<mode>): ... this. (mve_vdupq_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vdupq_m_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this. (mve_vdupq_m_n_f<mode>): Rename into ... (@mve_<mve_insn>q_m_n_f<mode>): ... this.
2023-05-11arm: [MVE intrinsics] rework vrev16q vrev32q vrev64qChristophe Lyon4-820/+11
Implement vrev16q, vrev32q, vrev64q using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vrev16q, vrev32q, vrev64q): New. * config/arm/arm-mve-builtins-base.def (vrev16q, vrev32q) (vrev64q): New. * config/arm/arm-mve-builtins-base.h (vrev16q, vrev32q) (vrev64q): New. * config/arm/arm_mve.h (vrev16q): Remove. (vrev32q): Remove. (vrev64q): Remove. (vrev64q_m): Remove. (vrev16q_m): Remove. (vrev32q_m): Remove. (vrev16q_x): Remove. (vrev32q_x): Remove. (vrev64q_x): Remove. (vrev64q_f16): Remove. (vrev64q_f32): Remove. (vrev32q_f16): Remove. (vrev16q_s8): Remove. (vrev32q_s8): Remove. (vrev32q_s16): Remove. (vrev64q_s8): Remove. (vrev64q_s16): Remove. (vrev64q_s32): Remove. (vrev64q_u8): Remove. (vrev64q_u16): Remove. (vrev64q_u32): Remove. (vrev32q_u8): Remove. (vrev32q_u16): Remove. (vrev16q_u8): Remove. (vrev64q_m_u8): Remove. (vrev64q_m_s8): Remove. (vrev64q_m_u16): Remove. (vrev64q_m_s16): Remove. (vrev64q_m_u32): Remove. (vrev64q_m_s32): Remove. (vrev16q_m_s8): Remove. (vrev32q_m_f16): Remove. (vrev16q_m_u8): Remove. (vrev32q_m_s8): Remove. (vrev64q_m_f16): Remove. (vrev32q_m_u8): Remove. (vrev32q_m_s16): Remove. (vrev64q_m_f32): Remove. (vrev32q_m_u16): Remove. (vrev16q_x_s8): Remove. (vrev16q_x_u8): Remove. (vrev32q_x_s8): Remove. (vrev32q_x_s16): Remove. (vrev32q_x_u8): Remove. (vrev32q_x_u16): Remove. (vrev64q_x_s8): Remove. (vrev64q_x_s16): Remove. (vrev64q_x_s32): Remove. (vrev64q_x_u8): Remove. (vrev64q_x_u16): Remove. (vrev64q_x_u32): Remove. (vrev32q_x_f16): Remove. (vrev64q_x_f16): Remove. (vrev64q_x_f32): Remove. (__arm_vrev16q_s8): Remove. (__arm_vrev32q_s8): Remove. (__arm_vrev32q_s16): Remove. (__arm_vrev64q_s8): Remove. (__arm_vrev64q_s16): Remove. (__arm_vrev64q_s32): Remove. (__arm_vrev64q_u8): Remove. (__arm_vrev64q_u16): Remove. (__arm_vrev64q_u32): Remove. (__arm_vrev32q_u8): Remove. (__arm_vrev32q_u16): Remove. (__arm_vrev16q_u8): Remove. (__arm_vrev64q_m_u8): Remove. (__arm_vrev64q_m_s8): Remove. (__arm_vrev64q_m_u16): Remove. (__arm_vrev64q_m_s16): Remove. (__arm_vrev64q_m_u32): Remove. (__arm_vrev64q_m_s32): Remove. (__arm_vrev16q_m_s8): Remove. (__arm_vrev16q_m_u8): Remove. (__arm_vrev32q_m_s8): Remove. (__arm_vrev32q_m_u8): Remove. (__arm_vrev32q_m_s16): Remove. (__arm_vrev32q_m_u16): Remove. (__arm_vrev16q_x_s8): Remove. (__arm_vrev16q_x_u8): Remove. (__arm_vrev32q_x_s8): Remove. (__arm_vrev32q_x_s16): Remove. (__arm_vrev32q_x_u8): Remove. (__arm_vrev32q_x_u16): Remove. (__arm_vrev64q_x_s8): Remove. (__arm_vrev64q_x_s16): Remove. (__arm_vrev64q_x_s32): Remove. (__arm_vrev64q_x_u8): Remove. (__arm_vrev64q_x_u16): Remove. (__arm_vrev64q_x_u32): Remove. (__arm_vrev64q_f16): Remove. (__arm_vrev64q_f32): Remove. (__arm_vrev32q_f16): Remove. (__arm_vrev32q_m_f16): Remove. (__arm_vrev64q_m_f16): Remove. (__arm_vrev64q_m_f32): Remove. (__arm_vrev32q_x_f16): Remove. (__arm_vrev64q_x_f16): Remove. (__arm_vrev64q_x_f32): Remove. (__arm_vrev16q): Remove. (__arm_vrev32q): Remove. (__arm_vrev64q): Remove. (__arm_vrev64q_m): Remove. (__arm_vrev16q_m): Remove. (__arm_vrev32q_m): Remove. (__arm_vrev16q_x): Remove. (__arm_vrev32q_x): Remove. (__arm_vrev64q_x): Remove.
2023-05-11arm: [MVE intrinsics] factorize vrev16q vrev32q vrev64qChristophe Lyon2-36/+61
Factorize vrev16q vrev32q vrev64q so that they use generic builtin names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_V8HF, MVE_V16QI) (MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY) (MVE_FP_M_VREV32Q_ONLY): New iterators. (mve_insn): Add vrev16q, vrev32q, vrev64q. * config/arm/mve.md (mve_vrev64q_f<mode>): Rename into ... (@mve_<mve_insn>q_f<mode>): ... this (mve_vrev32q_fv8hf): Rename into @mve_<mve_insn>q_f<mode>. (mve_vrev64q_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vrev32q_<supf><mode>): Rename into @mve_<mve_insn>q_<supf><mode>. (mve_vrev16q_<supf>v16qi): Rename into @mve_<mve_insn>q_<supf><mode>. (mve_vrev64q_m_<supf><mode>): Rename into @mve_<mve_insn>q_m_<supf><mode>. (mve_vrev32q_m_fv8hf): Rename into @mve_<mve_insn>q_m_f<mode>. (mve_vrev32q_m_<supf><mode>): Rename into @mve_<mve_insn>q_m_<supf><mode>. (mve_vrev64q_m_f<mode>): Rename into @mve_<mve_insn>q_m_f<mode>. (mve_vrev16q_m_<supf>v16qi): Rename into @mve_<mve_insn>q_m_<supf><mode>.
2023-05-11arm: [MVE intrinsics] rework vcmpChristophe Lyon6-2930/+149
Implement vcmp using the new MVE builtins framework. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vcmpeqq, vcmpneq, vcmpgeq) (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New. * config/arm/arm-mve-builtins-base.def (vcmpeqq, vcmpneq, vcmpgeq) (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New. * config/arm/arm-mve-builtins-base.h (vcmpeqq, vcmpneq, vcmpgeq) (vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New. * config/arm/arm-mve-builtins-functions.h (class unspec_based_mve_function_exact_insn_vcmp): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vcmp. * config/arm/arm_mve.h (vcmpneq): Remove. (vcmphiq): Remove. (vcmpeqq): Remove. (vcmpcsq): Remove. (vcmpltq): Remove. (vcmpleq): Remove. (vcmpgtq): Remove. (vcmpgeq): Remove. (vcmpneq_m): Remove. (vcmphiq_m): Remove. (vcmpeqq_m): Remove. (vcmpcsq_m): Remove. (vcmpcsq_m_n): Remove. (vcmpltq_m): Remove. (vcmpleq_m): Remove. (vcmpgtq_m): Remove. (vcmpgeq_m): Remove. (vcmpneq_s8): Remove. (vcmpneq_s16): Remove. (vcmpneq_s32): Remove. (vcmpneq_u8): Remove. (vcmpneq_u16): Remove. (vcmpneq_u32): Remove. (vcmpneq_n_u8): Remove. (vcmphiq_u8): Remove. (vcmphiq_n_u8): Remove. (vcmpeqq_u8): Remove. (vcmpeqq_n_u8): Remove. (vcmpcsq_u8): Remove. (vcmpcsq_n_u8): Remove. (vcmpneq_n_s8): Remove. (vcmpltq_s8): Remove. (vcmpltq_n_s8): Remove. (vcmpleq_s8): Remove. (vcmpleq_n_s8): Remove. (vcmpgtq_s8): Remove. (vcmpgtq_n_s8): Remove. (vcmpgeq_s8): Remove. (vcmpgeq_n_s8): Remove. (vcmpeqq_s8): Remove. (vcmpeqq_n_s8): Remove. (vcmpneq_n_u16): Remove. (vcmphiq_u16): Remove. (vcmphiq_n_u16): Remove. (vcmpeqq_u16): Remove. (vcmpeqq_n_u16): Remove. (vcmpcsq_u16): Remove. (vcmpcsq_n_u16): Remove. (vcmpneq_n_s16): Remove. (vcmpltq_s16): Remove. (vcmpltq_n_s16): Remove. (vcmpleq_s16): Remove. (vcmpleq_n_s16): Remove. (vcmpgtq_s16): Remove. (vcmpgtq_n_s16): Remove. (vcmpgeq_s16): Remove. (vcmpgeq_n_s16): Remove. (vcmpeqq_s16): Remove. (vcmpeqq_n_s16): Remove. (vcmpneq_n_u32): Remove. (vcmphiq_u32): Remove. (vcmphiq_n_u32): Remove. (vcmpeqq_u32): Remove. (vcmpeqq_n_u32): Remove. (vcmpcsq_u32): Remove. (vcmpcsq_n_u32): Remove. (vcmpneq_n_s32): Remove. (vcmpltq_s32): Remove. (vcmpltq_n_s32): Remove. (vcmpleq_s32): Remove. (vcmpleq_n_s32): Remove. (vcmpgtq_s32): Remove. (vcmpgtq_n_s32): Remove. (vcmpgeq_s32): Remove. (vcmpgeq_n_s32): Remove. (vcmpeqq_s32): Remove. (vcmpeqq_n_s32): Remove. (vcmpneq_n_f16): Remove. (vcmpneq_f16): Remove. (vcmpltq_n_f16): Remove. (vcmpltq_f16): Remove. (vcmpleq_n_f16): Remove. (vcmpleq_f16): Remove. (vcmpgtq_n_f16): Remove. (vcmpgtq_f16): Remove. (vcmpgeq_n_f16): Remove. (vcmpgeq_f16): Remove. (vcmpeqq_n_f16): Remove. (vcmpeqq_f16): Remove. (vcmpneq_n_f32): Remove. (vcmpneq_f32): Remove. (vcmpltq_n_f32): Remove. (vcmpltq_f32): Remove. (vcmpleq_n_f32): Remove. (vcmpleq_f32): Remove. (vcmpgtq_n_f32): Remove. (vcmpgtq_f32): Remove. (vcmpgeq_n_f32): Remove. (vcmpgeq_f32): Remove. (vcmpeqq_n_f32): Remove. (vcmpeqq_f32): Remove. (vcmpeqq_m_f16): Remove. (vcmpeqq_m_f32): Remove. (vcmpneq_m_u8): Remove. (vcmpneq_m_n_u8): Remove. (vcmphiq_m_u8): Remove. (vcmphiq_m_n_u8): Remove. (vcmpeqq_m_u8): Remove. (vcmpeqq_m_n_u8): Remove. (vcmpcsq_m_u8): Remove. (vcmpcsq_m_n_u8): Remove. (vcmpneq_m_s8): Remove. (vcmpneq_m_n_s8): Remove. (vcmpltq_m_s8): Remove. (vcmpltq_m_n_s8): Remove. (vcmpleq_m_s8): Remove. (vcmpleq_m_n_s8): Remove. (vcmpgtq_m_s8): Remove. (vcmpgtq_m_n_s8): Remove. (vcmpgeq_m_s8): Remove. (vcmpgeq_m_n_s8): Remove. (vcmpeqq_m_s8): Remove. (vcmpeqq_m_n_s8): Remove. (vcmpneq_m_u16): Remove. (vcmpneq_m_n_u16): Remove. (vcmphiq_m_u16): Remove. (vcmphiq_m_n_u16): Remove. (vcmpeqq_m_u16): Remove. (vcmpeqq_m_n_u16): Remove. (vcmpcsq_m_u16): Remove. (vcmpcsq_m_n_u16): Remove. (vcmpneq_m_s16): Remove. (vcmpneq_m_n_s16): Remove. (vcmpltq_m_s16): Remove. (vcmpltq_m_n_s16): Remove. (vcmpleq_m_s16): Remove. (vcmpleq_m_n_s16): Remove. (vcmpgtq_m_s16): Remove. (vcmpgtq_m_n_s16): Remove. (vcmpgeq_m_s16): Remove. (vcmpgeq_m_n_s16): Remove. (vcmpeqq_m_s16): Remove. (vcmpeqq_m_n_s16): Remove. (vcmpneq_m_u32): Remove. (vcmpneq_m_n_u32): Remove. (vcmphiq_m_u32): Remove. (vcmphiq_m_n_u32): Remove. (vcmpeqq_m_u32): Remove. (vcmpeqq_m_n_u32): Remove. (vcmpcsq_m_u32): Remove. (vcmpcsq_m_n_u32): Remove. (vcmpneq_m_s32): Remove. (vcmpneq_m_n_s32): Remove. (vcmpltq_m_s32): Remove. (vcmpltq_m_n_s32): Remove. (vcmpleq_m_s32): Remove. (vcmpleq_m_n_s32): Remove. (vcmpgtq_m_s32): Remove. (vcmpgtq_m_n_s32): Remove. (vcmpgeq_m_s32): Remove. (vcmpgeq_m_n_s32): Remove. (vcmpeqq_m_s32): Remove. (vcmpeqq_m_n_s32): Remove. (vcmpeqq_m_n_f16): Remove. (vcmpgeq_m_f16): Remove. (vcmpgeq_m_n_f16): Remove. (vcmpgtq_m_f16): Remove. (vcmpgtq_m_n_f16): Remove. (vcmpleq_m_f16): Remove. (vcmpleq_m_n_f16): Remove. (vcmpltq_m_f16): Remove. (vcmpltq_m_n_f16): Remove. (vcmpneq_m_f16): Remove. (vcmpneq_m_n_f16): Remove. (vcmpeqq_m_n_f32): Remove. (vcmpgeq_m_f32): Remove. (vcmpgeq_m_n_f32): Remove. (vcmpgtq_m_f32): Remove. (vcmpgtq_m_n_f32): Remove. (vcmpleq_m_f32): Remove. (vcmpleq_m_n_f32): Remove. (vcmpltq_m_f32): Remove. (vcmpltq_m_n_f32): Remove. (vcmpneq_m_f32): Remove. (vcmpneq_m_n_f32): Remove. (__arm_vcmpneq_s8): Remove. (__arm_vcmpneq_s16): Remove. (__arm_vcmpneq_s32): Remove. (__arm_vcmpneq_u8): Remove. (__arm_vcmpneq_u16): Remove. (__arm_vcmpneq_u32): Remove. (__arm_vcmpneq_n_u8): Remove. (__arm_vcmphiq_u8): Remove. (__arm_vcmphiq_n_u8): Remove. (__arm_vcmpeqq_u8): Remove. (__arm_vcmpeqq_n_u8): Remove. (__arm_vcmpcsq_u8): Remove. (__arm_vcmpcsq_n_u8): Remove. (__arm_vcmpneq_n_s8): Remove. (__arm_vcmpltq_s8): Remove. (__arm_vcmpltq_n_s8): Remove. (__arm_vcmpleq_s8): Remove. (__arm_vcmpleq_n_s8): Remove. (__arm_vcmpgtq_s8): Remove. (__arm_vcmpgtq_n_s8): Remove. (__arm_vcmpgeq_s8): Remove. (__arm_vcmpgeq_n_s8): Remove. (__arm_vcmpeqq_s8): Remove. (__arm_vcmpeqq_n_s8): Remove. (__arm_vcmpneq_n_u16): Remove. (__arm_vcmphiq_u16): Remove. (__arm_vcmphiq_n_u16): Remove. (__arm_vcmpeqq_u16): Remove. (__arm_vcmpeqq_n_u16): Remove. (__arm_vcmpcsq_u16): Remove. (__arm_vcmpcsq_n_u16): Remove. (__arm_vcmpneq_n_s16): Remove. (__arm_vcmpltq_s16): Remove. (__arm_vcmpltq_n_s16): Remove. (__arm_vcmpleq_s16): Remove. (__arm_vcmpleq_n_s16): Remove. (__arm_vcmpgtq_s16): Remove. (__arm_vcmpgtq_n_s16): Remove. (__arm_vcmpgeq_s16): Remove. (__arm_vcmpgeq_n_s16): Remove. (__arm_vcmpeqq_s16): Remove. (__arm_vcmpeqq_n_s16): Remove. (__arm_vcmpneq_n_u32): Remove. (__arm_vcmphiq_u32): Remove. (__arm_vcmphiq_n_u32): Remove. (__arm_vcmpeqq_u32): Remove. (__arm_vcmpeqq_n_u32): Remove. (__arm_vcmpcsq_u32): Remove. (__arm_vcmpcsq_n_u32): Remove. (__arm_vcmpneq_n_s32): Remove. (__arm_vcmpltq_s32): Remove. (__arm_vcmpltq_n_s32): Remove. (__arm_vcmpleq_s32): Remove. (__arm_vcmpleq_n_s32): Remove. (__arm_vcmpgtq_s32): Remove. (__arm_vcmpgtq_n_s32): Remove. (__arm_vcmpgeq_s32): Remove. (__arm_vcmpgeq_n_s32): Remove. (__arm_vcmpeqq_s32): Remove. (__arm_vcmpeqq_n_s32): Remove. (__arm_vcmpneq_m_u8): Remove. (__arm_vcmpneq_m_n_u8): Remove. (__arm_vcmphiq_m_u8): Remove. (__arm_vcmphiq_m_n_u8): Remove. (__arm_vcmpeqq_m_u8): Remove. (__arm_vcmpeqq_m_n_u8): Remove. (__arm_vcmpcsq_m_u8): Remove. (__arm_vcmpcsq_m_n_u8): Remove. (__arm_vcmpneq_m_s8): Remove. (__arm_vcmpneq_m_n_s8): Remove. (__arm_vcmpltq_m_s8): Remove. (__arm_vcmpltq_m_n_s8): Remove. (__arm_vcmpleq_m_s8): Remove. (__arm_vcmpleq_m_n_s8): Remove. (__arm_vcmpgtq_m_s8): Remove. (__arm_vcmpgtq_m_n_s8): Remove. (__arm_vcmpgeq_m_s8): Remove. (__arm_vcmpgeq_m_n_s8): Remove. (__arm_vcmpeqq_m_s8): Remove. (__arm_vcmpeqq_m_n_s8): Remove. (__arm_vcmpneq_m_u16): Remove. (__arm_vcmpneq_m_n_u16): Remove. (__arm_vcmphiq_m_u16): Remove. (__arm_vcmphiq_m_n_u16): Remove. (__arm_vcmpeqq_m_u16): Remove. (__arm_vcmpeqq_m_n_u16): Remove. (__arm_vcmpcsq_m_u16): Remove. (__arm_vcmpcsq_m_n_u16): Remove. (__arm_vcmpneq_m_s16): Remove. (__arm_vcmpneq_m_n_s16): Remove. (__arm_vcmpltq_m_s16): Remove. (__arm_vcmpltq_m_n_s16): Remove. (__arm_vcmpleq_m_s16): Remove. (__arm_vcmpleq_m_n_s16): Remove. (__arm_vcmpgtq_m_s16): Remove. (__arm_vcmpgtq_m_n_s16): Remove. (__arm_vcmpgeq_m_s16): Remove. (__arm_vcmpgeq_m_n_s16): Remove. (__arm_vcmpeqq_m_s16): Remove. (__arm_vcmpeqq_m_n_s16): Remove. (__arm_vcmpneq_m_u32): Remove. (__arm_vcmpneq_m_n_u32): Remove. (__arm_vcmphiq_m_u32): Remove. (__arm_vcmphiq_m_n_u32): Remove. (__arm_vcmpeqq_m_u32): Remove. (__arm_vcmpeqq_m_n_u32): Remove. (__arm_vcmpcsq_m_u32): Remove. (__arm_vcmpcsq_m_n_u32): Remove. (__arm_vcmpneq_m_s32): Remove. (__arm_vcmpneq_m_n_s32): Remove. (__arm_vcmpltq_m_s32): Remove. (__arm_vcmpltq_m_n_s32): Remove. (__arm_vcmpleq_m_s32): Remove. (__arm_vcmpleq_m_n_s32): Remove. (__arm_vcmpgtq_m_s32): Remove. (__arm_vcmpgtq_m_n_s32): Remove. (__arm_vcmpgeq_m_s32): Remove. (__arm_vcmpgeq_m_n_s32): Remove. (__arm_vcmpeqq_m_s32): Remove. (__arm_vcmpeqq_m_n_s32): Remove. (__arm_vcmpneq_n_f16): Remove. (__arm_vcmpneq_f16): Remove. (__arm_vcmpltq_n_f16): Remove. (__arm_vcmpltq_f16): Remove. (__arm_vcmpleq_n_f16): Remove. (__arm_vcmpleq_f16): Remove. (__arm_vcmpgtq_n_f16): Remove. (__arm_vcmpgtq_f16): Remove. (__arm_vcmpgeq_n_f16): Remove. (__arm_vcmpgeq_f16): Remove. (__arm_vcmpeqq_n_f16): Remove. (__arm_vcmpeqq_f16): Remove. (__arm_vcmpneq_n_f32): Remove. (__arm_vcmpneq_f32): Remove. (__arm_vcmpltq_n_f32): Remove. (__arm_vcmpltq_f32): Remove. (__arm_vcmpleq_n_f32): Remove. (__arm_vcmpleq_f32): Remove. (__arm_vcmpgtq_n_f32): Remove. (__arm_vcmpgtq_f32): Remove. (__arm_vcmpgeq_n_f32): Remove. (__arm_vcmpgeq_f32): Remove. (__arm_vcmpeqq_n_f32): Remove. (__arm_vcmpeqq_f32): Remove. (__arm_vcmpeqq_m_f16): Remove. (__arm_vcmpeqq_m_f32): Remove. (__arm_vcmpeqq_m_n_f16): Remove. (__arm_vcmpgeq_m_f16): Remove. (__arm_vcmpgeq_m_n_f16): Remove. (__arm_vcmpgtq_m_f16): Remove. (__arm_vcmpgtq_m_n_f16): Remove. (__arm_vcmpleq_m_f16): Remove. (__arm_vcmpleq_m_n_f16): Remove. (__arm_vcmpltq_m_f16): Remove. (__arm_vcmpltq_m_n_f16): Remove. (__arm_vcmpneq_m_f16): Remove. (__arm_vcmpneq_m_n_f16): Remove. (__arm_vcmpeqq_m_n_f32): Remove. (__arm_vcmpgeq_m_f32): Remove. (__arm_vcmpgeq_m_n_f32): Remove. (__arm_vcmpgtq_m_f32): Remove. (__arm_vcmpgtq_m_n_f32): Remove. (__arm_vcmpleq_m_f32): Remove. (__arm_vcmpleq_m_n_f32): Remove. (__arm_vcmpltq_m_f32): Remove. (__arm_vcmpltq_m_n_f32): Remove. (__arm_vcmpneq_m_f32): Remove. (__arm_vcmpneq_m_n_f32): Remove. (__arm_vcmpneq): Remove. (__arm_vcmphiq): Remove. (__arm_vcmpeqq): Remove. (__arm_vcmpcsq): Remove. (__arm_vcmpltq): Remove. (__arm_vcmpleq): Remove. (__arm_vcmpgtq): Remove. (__arm_vcmpgeq): Remove. (__arm_vcmpneq_m): Remove. (__arm_vcmphiq_m): Remove. (__arm_vcmpeqq_m): Remove. (__arm_vcmpcsq_m): Remove. (__arm_vcmpltq_m): Remove. (__arm_vcmpleq_m): Remove. (__arm_vcmpgtq_m): Remove. (__arm_vcmpgeq_m): Remove.
2023-05-11arm: [MVE intrinsics] add cmp shapeChristophe Lyon2-0/+28
This patch adds the cmp shape description. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (cmp): New. * config/arm/arm-mve-builtins-shapes.h (cmp): New.
2023-05-11arm: [MVE intrinsics] factorize vcmpChristophe Lyon2-387/+135
Factorize vcmp so that they use the same pattern. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F, MVE_CMP_M_N) (MVE_CMP_M_N_F, mve_cmp_op1): New. (isu): Add VCMP* (supf): Likewise. * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>): Rename into ... (@mve_vcmp<mve_cmp_op>q_n_<mode>): ... this. (mve_vcmpeqq_m_f<mode>, mve_vcmpgeq_m_f<mode>) (mve_vcmpgtq_m_f<mode>, mve_vcmpleq_m_f<mode>) (mve_vcmpltq_m_f<mode>, mve_vcmpneq_m_f<mode>): Merge into ... (@mve_vcmp<mve_cmp_op1>q_m_f<mode>): ... this. (mve_vcmpcsq_m_u<mode>, mve_vcmpeqq_m_<supf><mode>) (mve_vcmpgeq_m_s<mode>, mve_vcmpgtq_m_s<mode>) (mve_vcmphiq_m_u<mode>, mve_vcmpleq_m_s<mode>) (mve_vcmpltq_m_s<mode>, mve_vcmpneq_m_<supf><mode>): Merge into ... (@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>): ... this. (mve_vcmpcsq_m_n_u<mode>, mve_vcmpeqq_m_n_<supf><mode>) (mve_vcmpgeq_m_n_s<mode>, mve_vcmpgtq_m_n_s<mode>) (mve_vcmphiq_m_n_u<mode>, mve_vcmpleq_m_n_s<mode>) (mve_vcmpltq_m_n_s<mode>, mve_vcmpneq_m_n_<supf><mode>): Merge into ... (@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>): ... this. (mve_vcmpeqq_m_n_f<mode>, mve_vcmpgeq_m_n_f<mode>) (mve_vcmpgtq_m_n_f<mode>, mve_vcmpleq_m_n_f<mode>) (mve_vcmpltq_m_n_f<mode>, mve_vcmpneq_m_n_f<mode>): Merge into ... (@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>): ... this.
2023-05-11Implement LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [PR109128]Joseph Myers2-3/+44
This is one part of the fix for PR109128, along with a corresponding binutils's linker change. Without this patch, what happens in the linker, when an unused object in a .a file has offload data, is that elf_link_is_defined_archive_symbol calls bfd_link_plugin_object_p, which ends up calling the plugin's claim_file_handler, which then records the object as one with offload data. That is, the linker never decides to use the object in the first place, but use of this _p interface (called as part of trying to decide whether to use the object) results in the plugin deciding to use its offload data (and a consequent mismatch in the offload data present at runtime). The new hook allows the linker plugin to distinguish calls to claim_file_handler that know the object is being used by the linker (from ldmain.c:add_archive_element), from calls that don't know it's being used by the linker (from elf_link_is_defined_archive_symbol); in the latter case, the plugin should avoid recording the object as one with offload data. PR middle-end/109128 include/ * plugin-api.h (ld_plugin_claim_file_handler_v2) (ld_plugin_register_claim_file_v2) (LDPT_REGISTER_CLAIM_FILE_HOOK_V2): New. (struct ld_plugin_tv): Add tv_register_claim_file_v2. lto-plugin/ * lto-plugin.c (register_claim_file_v2): New. (claim_file_handler_v2): New. (claim_file_handler): Wrap claim_file_handler_v2. (onload): Handle LDPT_REGISTER_CLAIM_FILE_HOOK_V2.
2023-05-11Testsuite: Add 'torture-init-done', and use it to conditionalize implicit ↵Thomas Schwinge5-8/+30
'torture-init' Recent commit d6654a4be3ba44c0d57be7c8a51d76d9721345e1 "Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS'" made 'torture-init' non-idempotent re 'LTO_TORTURE_OPTIONS', in order to catch certain classes of errors. Now, most of all '*.exp' files have 'torture-init' followed by 'set-torture-options' before 'gcc-dg-runtest' etc., and therefore don't run into the latter's "Some callers set torture options themselves; don't override those." code. Some '*.exp' files however do 'torture-init' but not 'set-torture-options', and therefore we can't any longer conditionalize the implicit 'torture-init' by '![torture-options-exist]'. gcc/testsuite/ * lib/torture-options.exp (torture-init-done): Add. * lib/gcc-dg.exp (gcc-dg-runtest): Use it to conditionalize implicit 'torture-init'. * lib/gfortran-dg.exp (gfortran-dg-runtest): Likewise. * lib/obj-c++-dg.exp (obj-c++-dg-runtest): Likewise. * lib/objc-dg.exp (objc-dg-runtest): Likewise.
2023-05-11Testsuite: Add missing 'torture-init'/'torture-finish' around ↵Thomas Schwinge3-0/+7
'LTO_TORTURE_OPTIONS' usage Recent commit d6654a4be3ba44c0d57be7c8a51d76d9721345e1 "Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS'" made it a requirement that 'LTO_TORTURE_OPTIONS' usage be within 'torture-init'/'torture-finish', and missed a few cases that didn't have that. gcc/testsuite/ * gcc.target/arm/acle/acle.exp: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage. * gcc.target/arm/cmse/cmse.exp: Likewise. * gcc.target/arm/pure-code/pure-code.exp: Likewise.
2023-05-11match.pd: Simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y)Roger Sayle4-0/+100
This patch teaches match.pd to simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y), and the related simplifications that popcount(X)+popcount(Y)-popcount(X&Y) is popcount(X|Y). As surprising as it might seem, this idiom is common in cheminformatics codes (for Tanimoto coefficient calculations). 2023-05-11 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * match.pd <popcount optimizations>: Simplify popcount(X|Y) + popcount(X&Y) as popcount(X)+popcount(Y). Likewise, simplify popcount(X)+popcount(Y)-popcount(X&Y) as popcount(X|Y), and vice versa. gcc/testsuite/ChangeLog * gcc.dg/fold-popcount-8.c: New test case. * gcc.dg/fold-popcount-9.c: Likewise. * gcc.dg/fold-popcount-10.c: Likewise.
2023-05-11match.pd: Simplify popcount/parity of bswap/rotate.Roger Sayle5-0/+210
This is the latest iteration of my patch from August 2020 https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552391.html incorperating feedback and suggestions from reviewers. This patch to match.pd optimizes away bit permutation operations, specifically bswap and rotate, in calls to popcount and parity. 2023-05-11 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * match.pd <popcount optimizations>: Simplify popcount(bswap(x)) as popcount(x). Simplify popcount(rotate(x,y)) as popcount(x). <parity optimizations>: Simplify parity(bswap(x)) as parity(x). Simplify parity(rotate(x,y)) as parity(x). gcc/testsuite/ChangeLog * gcc.dg/fold-parity-6.c: New test. * gcc.dg/fold-parity-7.c: Likewise. * gcc.dg/fold-popcount-6.c: Likewise. * gcc.dg/fold-popcount-7.c: Likewise.
2023-05-11RISC-V: Support const series vector for RVV auto-vectorizationJuzhe-Zhong6-4/+236
This patch is the prerequiste patch for more RVV auto-vectorization support. Since when we enable a very simple binary operations, we will end up with such following ICE: during RTL pass: expand add_run-1.c: In function 'main': add_run-1.c:28:1: internal compiler error: Segmentation fault 0x1618ea3 crash_signal ../../../riscv-gcc/gcc/toplev.cc:314 0xe76cd9 single_set(rtx_insn const*) ../../../riscv-gcc/gcc/rtl.h:3602 0x1080f8a emit_move_insn(rtx_def*, rtx_def*) ../../../riscv-gcc/gcc/expr.cc:4342 0x170c458 insert_value_copy_on_edge ../../../riscv-gcc/gcc/tree-outof-ssa.cc:352 0x170d58e eliminate_phi ../../../riscv-gcc/gcc/tree-outof-ssa.cc:785 0x170df17 expand_phi_nodes(ssaexpand*) ../../../riscv-gcc/gcc/tree-outof-ssa.cc:1024 0xef27e2 execute ../../../riscv-gcc/gcc/cfgexpand.cc:6818 This is because LoopVectorizer assume target is able to handle series const vector when we enable binary operations. Then it will be easily causing ICE like that. gcc/ChangeLog: * config/riscv/autovec.md (@vec_series<mode>): New pattern * config/riscv/riscv-protos.h (expand_vec_series): New function. * config/riscv/riscv-v.cc (emit_binop): Ditto. (emit_index_op): Ditto. (expand_vec_series): Ditto. (expand_const_vector): Add series vector handling. * config/riscv/riscv.cc (riscv_const_insns): Enable series vector for testing. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/series-1.c: New test. * gcc.target/riscv/rvv/autovec/series_run-1.c: New test.
2023-05-11MAINTAINERS: Add myself to write after approvalJu-Zhe Zhong1-0/+1
Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai> ChangeLog: * MAINTAINERS: Add myself.
2023-05-11Daily bump.GCC Administrator7-1/+268
2023-05-10c++: wrong std::is_convertible with cv-qual fn [PR109680]Marek Polacek2-4/+51
This PR points out that std::is_convertible has given the wrong answer in static_assert (!std::is_convertible_v <int () const, int (*) ()>, ""); since r13-2822 implemented __is_{,nothrow_}convertible. std::is_convertible uses the imaginary To test() { return std::declval<From>(); } to do its job. Here, From is 'int () const'. std::declval is defined as: template<class T> typename std::add_rvalue_reference<T>::type declval() noexcept; std::add_rvalue_reference is defined as "If T is a function type that has no cv- or ref- qualifier or an object type, provides a member typedef type which is T&&, otherwise type is T." In our case, T is cv-qualified, so the result is T, so we end up with int () const declval() noexcept; which is invalid. In other words, this is pretty much like: using T = int () const; T fn1(); // bad, fn returning a fn T& fn2(); // bad, cannot declare reference to qualified function type T* fn3(); // bad, cannot declare pointer to qualified function type using U = int (); U fn4(); // bad, fn returning a fn U& fn5(); // OK U* fn6(); // OK I think is_convertible_helper needs to simulate std::declval better. To that end, I'm introducing build_trait_object, to be used where a declval is needed. PR c++/109680 gcc/cp/ChangeLog: * method.cc (build_trait_object): New. (assignable_expr): Use it. (ref_xes_from_temporary): Likewise. (is_convertible_helper): Likewise. Check FUNC_OR_METHOD_TYPE_P. gcc/testsuite/ChangeLog: * g++.dg/ext/is_convertible6.C: New test.
2023-05-10Use [(const_int 0)] idiom consistently in i386.mdRoger Sayle1-7/+7
This cleans up the use of [(clobber (const_int 0))] in the i386 backend. 2023-05-10 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/i386/i386.md (*concat<mode><dwi>3_1): Use preferred [(const_int 0)] idiom, instead of [(clobber (const_int 0))]. (*concat<mode><dwi>3_2): Likewise. (*concat<mode><dwi>3_3): Likewise. (*concat<mode><dwi>3_4): Likewise. (*concat<mode><dwi>3_5): Likewise. (*concat<mode><dwi>3_6): Likewise. (*concat<mode><dwi>3_7): Likewise.
2023-05-10c++: adjust conversion diagnosticsJason Merrill1-11/+9
While looking at PR109247 I made this change to improve diagnostics. I don't think I'm going ahead with that patch, but this still seems like a worthy cleanup. gcc/cp/ChangeLog: * call.cc (convert_like_internal): Share ck_ref_bind handling between all bad conversions.
2023-05-10i386: Add missing vector extend patterns [PR92658]Uros Bizjak3-0/+159
Add missing insn pattern for v2qi -> v2si vector extend and named expanders to activate generation of vector extends to 8-byte and 4-byte vectors. gcc/ChangeLog: PR target/92658 * config/i386/mmx.md (sse4_1_<code>v2qiv2si2): New insn pattern. (<insn>v4qiv4hi2): New expander. (<insn>v2hiv2si2): Ditto. (<insn>v2qiv2si2): Ditto. (<insn>v2qiv2hi2): Ditto. gcc/testsuite/ChangeLog: PR target/92658 * gcc.target/i386/pr92658-sse4-4b.c: New test. * gcc.target/i386/pr92658-sse4-8b.c: New test.
2023-05-10Fortran: dump-parse-tree: Mark debug functions with DEBUG_FUNCTIONBernhard Reutner-Fischer1-16/+22
gcc/fortran/ChangeLog: * dump-parse-tree.cc (gfc_debug_expr): Remove forward declaration. (debug): Add DEBUG_FUNCTION. (show_code_node): Remove erroneous whitespace.
2023-05-10Fortran: dump-parse-tree attribs: fix unbalanced braces [PR109624]Bernhard Reutner-Fischer1-3/+13
gcc/fortran/ChangeLog: PR fortran/109624 * dump-parse-tree.cc (debug): New function for gfc_namespace. (gfc_debug_code): Delete forward declaration. (show_attr): Make sure to print balanced braces.
2023-05-10Add another new testcaseAndrew Pinski1-0/+34
While working on improving min/max detection, this code (which is reduced from worse_state in ipa-pure-const.cc) was being miscompiled. Since there was no testcase in the testsuite yet for this, this patch adds one. Committed as obvious after testing the testcase via: make check-gcc RUNTESTFLAGS="execute.exp=20230510-1.c" gcc/testsuite/ChangeLog: * gcc.c-torture/execute/20230510-1.c: New test.
2023-05-10libstdc++: [_Hashtable] Implement several small methods implicitly inlineFrançois Dumont2-132/+106
Make implementation of 3 simple _Hashtable methods implicitly inline. Avoid usage of const_iterator abstraction within _Hashtable implementation. Replace several usages of __node_type* with expected __node_ptr. libstdc++-v3/ChangeLog: * include/bits/hashtable_policy.h (_NodeBuilder<>::_S_build): Use __node_ptr. (_ReuseOrAllocNode<>): Use __node_ptr in place of __node_type*. (_AllocNode<>): Likewise. (_Equality<>::_M_equal): Remove const_iterator usages. Only preserved to call std::is_permutation in the non-unique key implementation. * include/bits/hashtable.h (_Hashtable<>::_M_update_begin()): Capture _M_begin() once. (_Hashtable<>::_M_bucket_begin(size_type)): Implement implicitly inline. (_Hashtable<>::_M_insert_bucket_begin): Likewise. (_Hashtable<>::_M_remove_bucket_begin): Likewise. (_Hashtable<>::_M_compute_hash_code): Use __node_ptr rather than const_iterator. (_Hashtable<>::find): Likewise. (_Hashtable<>::_M_emplace): Likewise. (_Hashtable<>::_M_insert_unique): Likewise.
2023-05-10MAINTAINERS: Add myself to write after approvalPan Li1-0/+1
Signed-off-by: Pan Li <pan2.li@intel.com> ChangeLog: * MAINTAINERS: Add myself.
2023-05-10c++: be stricter about constinit [CWG2543]Jason Merrill3-24/+48
DR 2543 clarifies that constinit variables should follow the language, and diagnose non-constant initializers (according to [expr.const]) even if they can actually initialize the variables statically. DR 2543 gcc/cp/ChangeLog: * constexpr.cc (cxx_eval_outermost_constant_expr): Preserve TARGET_EXPR flags. (potential_constant_expression_1): Check TARGET_EXPR_ELIDING_P. * typeck2.cc (store_init_value): Diagnose constinit sooner. gcc/testsuite/ChangeLog: * g++.dg/DRs/dr2543.C: New test.
2023-05-10c++: always check consteval addressJason Merrill6-26/+37
The restriction on the "permitted result of a constant expression" to not refer to an immediate function applies regardless of context. The previous code tried to only check in cases where we wouldn't get the check in cp_fold_r, but with the next patch I would need to add another case and it shouldn't be a problem to always check. We also shouldn't talk about immediate evaluation when we aren't dealing with one. gcc/cp/ChangeLog: * constexpr.cc (cxx_eval_outermost_constant_expr): Always check for address of immediate fn. (maybe_constant_init_1): Evaluate PTRMEM_CST. gcc/testsuite/ChangeLog: * g++.dg/DRs/dr2478.C: Handle -fimplicit-constexpr. * g++.dg/cpp23/consteval-if12.C: Adjust diagnostics. * g++.dg/cpp2a/consteval20.C: Likewise. * g++.dg/cpp2a/consteval24.C: Likewise. * g++.dg/cpp2a/srcloc20.C: Likewise.
generated by cgit v1.1 at 2025-09-18 14:22:32 +0000