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2023-12-12testsuite: Add testcase for already fixed PR [PR112822]Peter Bergner1-0/+369
Adding a testcase for PR112822 to ensure we won't regress. 2023-12-12 Peter Bergner <bergner@linux.ibm.com> gcc/testsuite/ PR tree-optimization/112822 * g++.dg/pr112822.C: New test.
2023-12-12libstdc++: Fix std::format("{}", 'c')Jonathan Wakely3-0/+68
When I added a fast path for std::format("{}", x) in r14-5587-g41a5ea4cab2c59 I forgot to handle char separately from other integral types. That caused std::format("{}", 'c') to return "99" instead of "c". libstdc++-v3/ChangeLog: * include/std/format (__do_vformat_to): Handle char separately from other integral types. * testsuite/std/format/functions/format.cc: Check for expected output for char and bool arguments. * testsuite/std/format/string.cc: Check that 0 filling is rejected for character and string formats.
2023-12-12libstdc++: Fix std::format output of %C for negative yearsJonathan Wakely2-4/+12
During discussion of LWG 4022 I noticed that we do not correctly implement floored division for the century. We were just truncating towards zero, rather than applying the floor function. For negative values that rounds the wrong way. libstdc++-v3/ChangeLog: * include/bits/chrono_io.h (__formatter_chrono::_M_C_y_Y): Fix rounding for negative centuries. * testsuite/std/time/year/io.cc: Check %C for negative years.
2023-12-12libstdc++: Remove redundant -std flags from MakefileJonathan Wakely2-8/+8
In r14-4060-gc4baeaecbbf7d0 I moved some files from src/c++98 to src/c++11 but I didn't remove the redundant -std=gnu++11 flags for those files. The flags aren't needed now, because AM_CXXFLAGS for that directory already uses -std=gnu++11. This removes them. libstdc++-v3/ChangeLog: * src/c++11/Makefile.am: Remove redundant -std=gnu++11 flags. * src/c++11/Makefile.in: Regenerate.
2023-12-12SRA: Force gimple operand in an additional corner case (PR 112822)Martin Jambor1-3/+7
PR 112822 revealed a corner case in load_assign_lhs_subreplacements where it creates invalid gimple: an assignment where on the LHS there is a complex variable which however is not a gimple register because it has partial defs and on the right hand side there is a VIEW_CONVERT_EXPR. This patch invokes force_gimple_operand_gsi on such statements (like it already does when both sides of a generated assignment have partial definitions. gcc/ChangeLog: 2023-12-12 Martin Jambor <mjambor@suse.cz> PR tree-optimization/112822 * tree-sra.cc (load_assign_lhs_subreplacements): Invoke force_gimple_operand_gsi also when LHS has partial stores and RHS is a VIEW_CONVERT_EXPR.
2023-12-12PR modula2/112984 Compiling program with -Wpedantic shows warning in librariesGaius Mulley40-53/+93
This patch tidies up the library modules so that -Wpedantic does not generate any warnings (apart from two procedures with legitimate infinite loops). gcc/m2/ChangeLog: PR modula2/112984 * gm2-libs-coroutines/SYSTEM.mod: Remove redundant import of memcpy. * gm2-libs-iso/ClientSocket.mod: Remove redundant import of IOConsts. * gm2-libs-iso/IOChan.mod: Remove redundant import of IOConsts. * gm2-libs-iso/IOLink.mod: Remove redundant import of IOChan and SYSTEM. * gm2-libs-iso/IOResult.mod: Remove redundant import of IOChan. * gm2-libs-iso/LongIO.mod: Remove redundant import of writeString. * gm2-libs-iso/LongWholeIO.mod: Remove redundant import of IOChan. * gm2-libs-iso/M2RTS.mod: Remove redundant import of ADDRESS. * gm2-libs-iso/MemStream.mod: Remove redundant import of ADDRESS. * gm2-libs-iso/RTdata.mod: Remove redundant import of DeviceTablePtr. * gm2-libs-iso/RTfio.mod: Remove redundant import of DeviceTablePtr. * gm2-libs-iso/RTgen.mod: Remove redundant import of DeviceTablePtr. * gm2-libs-iso/RealIO.mod: Remove redundant import of writeString. * gm2-libs-iso/RndFile.mod: Remove redundant import of SYSTEM. * gm2-libs-iso/SYSTEM.mod: Remove redundant import of memcpy. * gm2-libs-iso/ShortWholeIO.mod: Remove redundant import of IOConsts. * gm2-libs-iso/TextIO.mod: Remove redundant import of IOChan. * gm2-libs-iso/TextUtil.mod: Remove redundant import of IOChan. * gm2-libs-iso/WholeIO.mod: Remove redundant import of IOChan. * gm2-libs-log/BitByteOps.mod: Remove redundant import of BYTE. * gm2-libs-log/FileSystem.mod: Remove redundant import of BYTE and ADDRESS. * gm2-libs-log/InOut.mod: Remove redundant import of String. * gm2-libs-log/RealConversions.mod: Remove redundant import of StringToLongreal. * gm2-libs/FIO.mod: Remove redundant import of SIZE. * gm2-libs/FormatStrings.mod: Remove redundant import of String and ConCatChar. * gm2-libs/IO.mod: Remove redundant import of SIZE. * gm2-libs/Indexing.mod: Remove redundant import of ADDRESS. * gm2-libs/M2Dependent.mod: Remove redundant import of SIZE. * gm2-libs/M2RTS.mod: Remove redundant import of ADDRESS. * gm2-libs/OptLib.mod: Remove redundant import of DynamicStrings. * gm2-libs/SYSTEM.mod: Remove redundant import of memcpy. * gm2-libs/StringConvert.mod: Remove redundant import of String. libgm2/ChangeLog: * libm2iso/Makefile.am (libm2iso_la_M2FLAGS): Added line breaks. * libm2iso/Makefile.in: Regenerate. * libm2log/Makefile.am (libm2log_la_M2FLAGS): Added line breaks. * libm2log/Makefile.in: Regenerate. * libm2pim/Makefile.am (libm2pim_la_M2FLAGS): Added line breaks. * libm2pim/Makefile.in: Regenerate. gcc/testsuite/ChangeLog: PR modula2/112984 * gm2/switches/pedantic/pass/hello.mod: New test. * gm2/switches/pedantic/pass/switches-pedantic-pass.exp: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-12-13LoongArch: testsuite: Remove XFAIL in vect-ftint-no-inexact.cXi Ruoyao1-2/+1
After r14-6455 this no longer fails. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-ftint-no-inexact.c (xfail): Remove.
2023-12-12testsuite: fix is_nothrow_default_constructible8.CJason Merrill1-1/+1
This testcase uses variable templates, a C++14 feature. gcc/testsuite/ChangeLog: * g++.dg/ext/is_nothrow_constructible8.C: Require C++14.
2023-12-12tree: add to clobber_kindJason Merrill10-24/+52
In discussion of PR71093 it came up that more clobber_kind options would be useful within the C++ front-end. gcc/ChangeLog: * tree-core.h (enum clobber_kind): Rename CLOBBER_EOL to CLOBBER_STORAGE_END. Add CLOBBER_STORAGE_BEGIN, CLOBBER_OBJECT_BEGIN, CLOBBER_OBJECT_END. * gimple-lower-bitint.cc * gimple-ssa-warn-access.cc * gimplify.cc * tree-inline.cc * tree-ssa-ccp.cc: Adjust for rename. * tree-pretty-print.cc: And handle new values. gcc/cp/ChangeLog: * call.cc (build_trivial_dtor_call): Use CLOBBER_OBJECT_END. * decl.cc (build_clobber_this): Take clobber_kind argument. (start_preparsed_function): Pass CLOBBER_OBJECT_BEGIN. (begin_destructor_body): Pass CLOBBER_OBJECT_END. gcc/testsuite/ChangeLog: * gcc.dg/pr87052.c: Adjust expected CLOBBER output. Co-authored-by: Nathaniel Shead <nathanieloshead@gmail.com>
2023-12-12aarch64,arm: Fix branch-protection= parsingSzabolcs Nagy7-168/+116
Refactor the parsing to have a single API and fix a few parsing issues: - Different handling of "bti+none" and "none+bti": these should be rejected because "none" can only appear alone. - Accepted empty strings such as "bti++pac-ret" or "bti+", this bug was caused by using strtok_r. - Memory got leaked (str_root was never freed). And two buffers got allocated when one is enough. The callbacks now have no failure mode, only parsing can fail and all failures are handled locally. The "-mbranch-protection=" vs "target("branch-protection=")" difference in the error message is handled by a separate argument to aarch_validate_mbranch_protection. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_override_options): Update. (aarch64_handle_attr_branch_protection): Update. * config/arm/aarch-common-protos.h (aarch_parse_branch_protection): Remove. (aarch_validate_mbranch_protection): Add new argument. * config/arm/aarch-common.cc (aarch_handle_no_branch_protection): Update. (aarch_handle_standard_branch_protection): Update. (aarch_handle_pac_ret_protection): Update. (aarch_handle_pac_ret_leaf): Update. (aarch_handle_pac_ret_b_key): Update. (aarch_handle_bti_protection): Update. (aarch_parse_branch_protection): Remove. (next_tok): New. (aarch_validate_mbranch_protection): Rewrite. * config/arm/aarch-common.h (struct aarch_branch_protect_type): Add field "alone". * config/arm/arm.cc (arm_configure_build_target): Update. gcc/testsuite/ChangeLog: * gcc.target/aarch64/branch-protection-attr.c: Update. * gcc.target/aarch64/branch-protection-option.c: Update.
2023-12-12aarch64,arm: Remove accepted_branch_protection_stringSzabolcs Nagy3-27/+1
On aarch64 this caused ICE with pragma push_options since commit ae54c1b09963779c5c3914782324ff48af32e2f1 Author: Wilco Dijkstra <wilco.dijkstra@arm.com> CommitDate: 2022-06-01 18:13:57 +0100 AArch64: Cleanup option processing code The failure is at pop_options: internal compiler error: ‘global_options’ are modified in local context On arm the variable was unused. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_override_options_after_change_1): Do not override branch_protection options. (aarch64_override_options): Remove accepted_branch_protection_string. * config/arm/aarch-common.cc (BRANCH_PROTECT_STR_MAX): Remove. (aarch_parse_branch_protection): Remove accepted_branch_protection_string. * config/arm/arm.cc: Likewise.
2023-12-12tree-optimization/112736 - avoid overread with non-grouped SLP loadRichard Biener2-19/+100
The following aovids over/under-read of storage when vectorizing a non-grouped load with SLP. Instead of forcing peeling for gaps use a smaller load for the last vector which might access excess elements. This builds upon the existing optimization avoiding peeling for gaps, generalizing it to all gap widths leaving a power-of-two remaining number of elements (but it doesn't replace or improve that particular case at this point). I wonder if the poly relational compares I set up are good enough to guarantee /* remain should now be > 0 and < nunits. */. There is existing test coverage that runs into /* DR will be unused. */ always when the gap is wider than nunits. Compared to the existing gap == nunits/2 case this only adjusts the load that will cause the overrun at the end, not every load. Apart from the poly relational compares it should reliably cover these cases but I'll leave it for stage1 to remove. PR tree-optimization/112736 * tree-vect-stmts.cc (vectorizable_load): Extend optimization to avoid peeling for gaps to handle single-element non-groups we now allow with SLP. * gcc.dg/torture/pr112736.c: New testcase.
2023-12-12ipa/92606 - properly handle no_icf attribute for variablesRichard Biener3-2/+9
The following adds no_icf handling for variables where the attribute was rejected. It also fixes the check for no_icf by checking both the source and the targets decl. PR ipa/92606 gcc/c-family/ * c-attribs.cc (handle_noicf_attribute): Also allow the attribute on global variables. gcc/ * ipa-icf.cc (sem_item_optimizer::merge_classes): Check both source and alias for the no_icf attribute. * doc/extend.texi (no_icf): Document variable attribute.
2023-12-12tree-optimization/112961 - include latch in if-conversion CSERichard Biener2-2/+24
The following makes sure to also process the (empty) latch when performing CSE on the if-converted loop body. That's important to get all uses of copies propagated out on the backedge as well. To avoid CSE on the PHI nodes itself which is prohibitive (see PR90402) this temporarily adds a fake entry edge to the loop. PR tree-optimization/112961 * tree-if-conv.cc (tree_if_conversion): Instead of excluding the latch block from VN, add a fake entry edge. * g++.dg/vect/pr112961.cc: New testcase.
2023-12-12testsuite: Fix up test directive syntax errorsJakub Jelinek3-9/+9
I've noticed +ERROR: gcc.dg/gomp/pr87887-1.c: syntax error in target selector ".-4" for " dg-warning 13 "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr87887-1.c: syntax error in target selector ".-4" for " dg-warning 13 "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr89246-1.c: syntax error in target selector ".-4" for " dg-warning 11 "unsupported argument type ‘__int128’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr89246-1.c: syntax error in target selector ".-4" for " dg-warning 11 "unsupported argument type ‘__int128’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/simd-clones-2.c: unmatched open quote in list for " dg-final 19 { scan-tree-dump "_ZGVnN2ua32vl_setArray" "optimized { target aarch64*-*-* } } " +ERROR: gcc.dg/gomp/simd-clones-2.c: unmatched open quote in list for " dg-final 19 { scan-tree-dump "_ZGVnN2ua32vl_setArray" "optimized { target aarch64*-*-* } } " regressions. The following patch fixes those. 2023-12-12 Jakub Jelinek <jakub@redhat.com> * gcc.dg/gomp/pr87887-1.c: Add missing comment argument to dg-warning. * gcc.dg/gomp/pr89246-1.c: Likewise. * gcc.dg/gomp/simd-clones-2.c: Add missing " after dump name.
2023-12-12Only allow (int)trunc(x) to (int)x simplification with ↵Xi Ruoyao2-1/+14
-ffp-int-builtin-inexact [PR107723] With -fno-fp-int-builtin-inexact, trunc is not allowed to raise FE_INEXACT and it should produce an integral result (if the input is not NaN or Inf). Thus FE_INEXACT should not be raised. But (int)x may raise FE_INEXACT when x is a non-integer, non-NaN, and non-Inf value. C23 recommends to do so in a footnote. Thus we should not simplify (int)trunc(x) to (int)x if -fno-fp-int-builtin-inexact is in-effect. gcc/ChangeLog: PR middle-end/107723 * convert.cc (convert_to_integer_1) [case BUILT_IN_TRUNC]: Break early if !flag_fp_int_builtin_inexact and flag_trapping_math. gcc/testsuite/ChangeLog: PR middle-end/107723 * gcc.dg/torture/builtin-fp-int-inexact-trunc.c: New test.
2023-12-12aarch64: Add dg-options to prfm_imm_offset_2.cRichard Sandiford1-0/+1
gcc/testsuite/ * gcc.target/aarch64/prfm_imm_offset_2.c: Add dg-options.
2023-12-12Add myself to write after approvalPaul Iannetta1-0/+1
ChangeLog: * MAINTAINERS: Add myself to write after approval Signed-off-by: Paul Iannetta <piannetta@kalrayinc.com>
2023-12-12RISC-V: Disable RVV VCOMPRESS avl propagationPan Li2-10/+61
This patch would like to disable the avl propagation for the follow reasons. According to the ISA, the first vl elements of vector register group vs2 should be extracted and packed for vcompress. And the highest element of vs2 vector may be touched by the mask, which may be eliminated by avl propagation. For example, given original vl = 4 here. We have: v0 = 0b1000 v1 = {0x1, 0x2, 0x3, 0x4} v2 = {0x5, 0x6, 0x7, 0x8} Then: vcompress v1, v2, v0 (avl = 4), v1 = {0x8, 0x2, 0x3, 0x4}. <== Correct. vcompress v1, v2, v0 (avl = 2), v1 will be unchanged. <== Wrong. Finally, we cannot propagate avl of vcompress because it may has senmatics change to the result. This patch also fix the failure of gcc.c-torture/execute/990128-1.c for the following configurations. riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m4/--param=riscv-autovec-preference=fixed-vlmax riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 riscv-sim/-march=rv64gcv_zvl512b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Disable the avl propogation for the vcompress. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-12-12libquadmath: Restore linking against -lm on most targets [PR112963]Jakub Jelinek3-2/+32
The r14-4825 change added AC_CHECK_LIBM to libquadmath configure.ac and replaced unconditional linking with -lm with linking with $(LIBM) determined by that. Unfortunately that broke bare metal targets because AC_CHECK_LIBM attempts to link against -lm and this was after (unconditional) GCC_NO_EXECUTABLES. Then r14-4863 partially reverted that change (no longer AC_CHECK_LIBM), but didn't revert the Makefile.am change of -lm to $(LIBM), which had the effect that libquadmath is not linked against -lm on any arch. That is a serious problem though e.g. on Linux, because libquadmath calls a few libm entrypoints and e.g. on powerpc64le the underlinking can cause crashes in IFUNC resolvers of libm. Instead of adding further reversion of the r14-4825 commit and use -lm unconditionally again, this patch adds an AC_CHECK_LIBM like substitutions with the *-ncr-sysv4.3* target handling removed (I think we don't support such targets, especially not in libquadmath) and with the default case replaced by simple using -lm. That is something in between using -lm unconditionally and what AC_CHECK_LIBM does if it would work on bare metal - we know from GCC 13 and earlier that we can link -lm on all targets libquadmath is built for, and just white list a couple of targets which we know don't have separate -lm and don't want to link against that (like Darwin, Cygwin, ...). 2023-12-12 Jakub Jelinek <jakub@redhat.com> PR libquadmath/112963 * configure.ac (LIBM): Readd AC_CHECK_LIBM-like check without doing AC_CHECK_LIB in it. * configure: Regenerated. * Makefile.in: Regenerated.
2023-12-12LoongArch: Fix warnings building libgccXi Ruoyao1-10/+10
We are excluding loongarch-opts.h from target libraries, but now struct loongarch_target and gcc_options are not declared in the target libraries, causing: In file included from ../.././gcc/options.h:8, from ../.././gcc/tm.h:49, from ../../../gcc/libgcc/fixed-bit.c:48: ../../../gcc/libgcc/../gcc/config/loongarch/loongarch-opts.h:57:41: warning: 'struct gcc_options' declared inside parameter list will not be visible outside of this definition or declaration 57 | struct gcc_options *opts, | ^~~~~~~~~~~ So exclude the declarations referring to the C++ structs as well. gcc/ChangeLog: * config/loongarch/loongarch-opts.h (la_target): Move into #if for loongarch-def.h. (loongarch_init_target): Likewise. (loongarch_config_target): Likewise. (loongarch_update_gcc_opt_status): Likewise.
2023-12-12LoongArch: Allow -mcmodel=extreme and model attribute with ↵Xi Ruoyao6-11/+44
-mexplicit-relocs=auto There seems no real reason to require -mexplicit-relocs=always for -mcmodel=extreme or model attribute. As the linker does not know how to relax a 3-operand la.local or la.global pseudo instruction, just emit explicit relocs for SYMBOL_PCREL64, and under TARGET_CMODEL_EXTREME also SYMBOL_GOT_DISP. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p): Return true for SYMBOL_PCREL64. Return true for SYMBOL_GOT_DISP if TARGET_CMODEL_EXTREME. (loongarch_split_symbol): Check for la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE instead of TARGET_EXPLICIT_RELOCS. (loongarch_print_operand_reloc): Likewise. (loongarch_option_override_internal): Likewise. (loongarch_handle_model_attribute): Likewise. * doc/invoke.texi (-mcmodel=extreme): Update the compatibility between it and -mexplicit-relocs=. gcc/testsuite/ChangeLog: * gcc.target/loongarch/attr-model-3.c: New test. * gcc.target/loongarch/attr-model-4.c: New test. * gcc.target/loongarch/func-call-extreme-3.c: New test. * gcc.target/loongarch/func-call-extreme-4.c: New test.
2023-12-12tree-optimization/112939 - VN PHI visiting and -ftrivial-auto-var-initRichard Biener2-1/+26
The following builds upon the last fix, making sure we only value-number to visited (un-)defs, otherwise prefer .VN_TOP. PR tree-optimization/112939 * tree-ssa-sccvn.cc (visit_phi): When all args are undefined make sure we end up with a value that was visited, otherwise fall back to .VN_TOP. * gcc.dg/pr112939.c: New testcase.
2023-12-12Don't assume it's AVX_U128_CLEAN after call_insn whose ↵liuhongt3-3/+78
abi.mode_clobber(V4DImode) deosn't contains all SSE_REGS. If the function desn't clobber any sse registers or only clobber 128-bit part, then vzeroupper isn't issued before the function exit. the status not CLEAN but ANY after the function. Also for sibling_call, it's safe to issue an vzeroupper. Also there could be missing vzeroupper since there's no mode_exit for sibling_call_p. gcc/ChangeLog: PR target/112891 * config/i386/i386.cc (ix86_avx_u128_mode_after): Return AVX_U128_ANY if callee_abi doesn't clobber all_sse_regs to align with ix86_avx_u128_mode_needed. (ix86_avx_u128_mode_needed): Return AVX_U128_ClEAN for sibling_call. gcc/testsuite/ChangeLog: * gcc.target/i386/pr112891.c: New test. * gcc.target/i386/pr112891-2.c: New test.
2023-12-12untyped calls: enable target switching [PR112334]Alexandre Oliva2-2/+21
The computation of apply_args_size and apply_result_size is saved in a static variable, so that the corresponding _mode arrays are initialized only once. That is not compatible with switchable targets, and ARM's arm_set_current_function, by saving and restoring target globals, exercises this problem with a testcase such as that in the PR, in which more than one function in the translation unit calls __builtin_apply or __builtin_return, respectively. This patch moves the _size statics into the target_builtins array, with a bit of ugliness over _plus_one so that zero initialization of the struct does the right thing. for gcc/ChangeLog PR target/112334 * builtins.h (target_builtins): Add fields for apply_args_size and apply_result_size. * builtins.cc (apply_args_size, apply_result_size): Cache results in fields rather than in static variables. (get_apply_args_size, set_apply_args_size): New. (get_apply_result_size, set_apply_result_size): New.
2023-12-12i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943]Hongyu Wang2-4/+71
The ashl/lshr/ashr expanders calls ix86_expand_binary_operator, while they will be called for some post-reload split, and TARGET_APX_NDD is required for these calls to avoid force-load to memory at postreload stage. gcc/ChangeLog: PR target/112943 * config/i386/i386.md (ashl<mode>3): Add TARGET_APX_NDD to ix86_expand_binary_operator call. (<insn><mode>3): Likewise for rshift. (<insn>di3): Likewise for DImode rotate. (<insn><mode>3): Likewise for SWI124 rotate. gcc/testsuite/ChangeLog: PR target/112943 * gcc.target/i386/pr112943.c: New test.
2023-12-11analyzer: add more test coverage for tainted modulusDavid Malcolm2-0/+76
Add more test coverage for r14-6349-g0bef72539e585d. gcc/testsuite/ChangeLog: * gcc.dg/plugin/plugin.exp: Add taint-modulus.c to analyzer_kernel_plugin.c tests. * gcc.dg/plugin/taint-modulus.c: New test. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-12-12MAINTAINERS: Update my email addressFeng Wang1-1/+1
ChangeLog: * MAINTAINERS: Update my email address
2023-12-12RISC-V: Add avail interface into function_group_infoFeng Wang5-475/+503
Patch v3: Fix typo and remove the modification of rvv.exp. Patch v2: Using variadic macro and add the dependency into t-riscv. In order to add other extension about vector,this patch add unsigned int (*avail) (void) into function_group_info to determine whether to register the intrinsic based on ISA info. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Add AVAIL argument. (read_vl): Using AVAIL argument default value. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64): Ditto. (vleff): Ditto. (vadd): Ditto. (vsub): Ditto. (vrsub): Ditto. (vneg): Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x): Ditto. (vzext): Ditto. (vsext): Ditto. (vadc): Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto. (vfwcvt_rtz_xu) Ditto.: (vfwcvt_f): Ditto. (vfwcvt_x_frm): Ditto. (vfwcvt_xu_frm) Ditto.: (vfncvt_x): Ditto. (vfncvt_xu): Ditto. (vfncvt_rtz_x): Ditto. (vfncvt_rtz_xu): Ditto. (vfncvt_f): Ditto. (vfncvt_rod_f): Ditto. (vfncvt_x_frm): Ditto. (vfncvt_xu_frm): Ditto. (vfncvt_f_frm): Ditto. (vredsum): Ditto. (vredmaxu): Ditto. (vredmax): Ditto. (vredminu): Ditto. (vredmin): Ditto. (vredand): Ditto. (vredor): Ditto. (vredxor): Ditto. (vwredsum): Ditto. (vwredsumu): Ditto. (vfredusum): Ditto. (vfredosum): Ditto. (vfredmax): Ditto. (vfredmin): Ditto. (vfredusum_frm): Ditto. (vfredosum_frm): Ditto. (vfwredosum): Ditto. (vfwredusum): Ditto. (vfwredosum_frm): Ditto. (vfwredusum_frm): Ditto. (vmand): Ditto. (vmnand): Ditto. (vmandn): Ditto. (vmxor): Ditto. (vmor): Ditto. (vmnor): Ditto. (vmorn): Ditto. (vmxnor): Ditto. (vmmv): Ditto. (vmclr): Ditto. (vmset): Ditto. (vmnot): Ditto. (vcpop): Ditto. (vfirst): Ditto. (vmsbf): Ditto. (vmsif): Ditto. (vmsof): Ditto. (viota): Ditto. (vid): Ditto. (vmv_x): Ditto. (vmv_s): Ditto. (vfmv_f): Ditto. (vfmv_s): Ditto. (vslideup): Ditto. (vslidedown): Ditto. (vslide1up): Ditto. (vslide1down): Ditto. (vfslide1up): Ditto. (vfslide1down): Ditto. (vrgather): Ditto. (vrgatherei16): Ditto. (vcompress): Ditto. (vundefined): Ditto. (vreinterpret): Ditto. (vlmul_ext): Ditto. (vlmul_trunc): Ditto. (vset): Ditto. (vget): Ditto. (vcreate): Ditto. (vlseg): Ditto. (vsseg): Ditto. (vlsseg): Ditto. (vssseg): Ditto. (vluxseg): Ditto. (vloxseg): Ditto. (vsuxseg): Ditto. (vsoxseg): Ditto. (vlsegff): Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): Using variadic macro. * config/riscv/riscv-vector-builtins.h (struct function_group_info): Add avail function interface into struct. * config/riscv/t-riscv: Add dependency * config/riscv/riscv-vector-builtins-avail.h: New file.The definition of AVAIL marco.
2023-12-12RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC]Juzhe-Zhong3-40/+52
This patch moves RVV POLY VALUE estimation from riscv.cc to riscv-v.cc for future better maintain like other target hook implementation. Committed as it is obviously a code refinement. gcc/ChangeLog: * config/riscv/riscv-protos.h (estimated_poly_value): New function. * config/riscv/riscv-v.cc (estimated_poly_value): Ditto. * config/riscv/riscv.cc (riscv_estimated_poly_value): Move RVV POLY VALUE estimation to riscv-v.cc
2023-12-12LoongArch: Fix eh_return epilogue for normal returns.Yang Yujie4-13/+84
On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved and restored in the function prologue and epilogue if the given function calls __builtin_eh_return. This causes the return value to be overwritten on normal return paths and breaks a rare case of libgcc's _Unwind_RaiseException. gcc/ChangeLog: * config/loongarch/loongarch.cc: Do not restore the saved eh_return data registers ($r4-$r7) for a normal return of a function that calls __builtin_eh_return elsewhere. * config/loongarch/loongarch-protos.h: Same. * config/loongarch/loongarch.md: Same. gcc/testsuite/ChangeLog: * gcc.target/loongarch/eh_return-normal-return.c: New test.
2023-12-12MAINTAINERS: Add myself to write after approval and DCOFeng Wang1-0/+1
ChangeLog: * MAINTAINERS: Add myself to write after approval
2023-12-12Daily bump.GCC Administrator13-1/+596
2023-12-11testsuite: Disable -fstack-protector* for some strub testsJakub Jelinek4-4/+4
In our distro builds, we test with RUNTESTFLAGS='--target_board=unix\{,-fstack-protector-strong\}' because SSP is something we use widely in the distribution. 4 new strub test FAIL with that option though, as can be seen with a simple make check-gcc check-g++ RUNTESTFLAGS='--target_board=unix\{,-fstack-protector-strong\} dg.exp=strub-O*' - in particular, the expand dump \[(\]call\[^\n\]*strub_leave.*\n\[(\]code_label regexps see code_labels in there introduced for stack protector. The following patch fixes it by using -fno-stack-protector for these explicitly. 2023-12-11 Jakub Jelinek <jakub@redhat.com> * c-c++-common/strub-O2fni.c: Add -fno-stack-protector to dg-options. * c-c++-common/strub-O3fni.c: Likewise. * c-c++-common/strub-Os.c: Likewise. * c-c++-common/strub-Og.c: Likewise.
2023-12-11Fix regression causing ICE for structs with VLAs [PR 112488]Martin Uecker7-11/+65
A previous patch that fixed several ICEs related to size expressions of VM types (PR c/70418, ...) caused a regression for structs where a DECL_EXPR is not generated anymore although reqired. We now call add_decl_expr introduced by the previous patch from finish_struct. The function is revised with a new argument to not set the TYPE_NAME for the type to the DECL_EXPR in this specific case. PR c/112488 gcc/c * c-decl.cc (add_decl_expr): Revise. (finish_struct): Create DECL_EXPR. * c-parser.cc (c_parser_struct_or_union_specifier): Call finish_struct with expression for VLA sizes. * c-tree.h (finish_struct): Add argument. gcc/testsuite * gcc.dg/pr112488-1.c: New test. * gcc.dg/pr112488-2.c: New test. * gcc.dg/pr112898.c: New test. * gcc.misc-tests/gcov-pr85350.c: Adapt.
2023-12-11Resolve ICE in 'gcc/fortran/trans-openmp.cc:gfc_omp_call_is_alloc'Thomas Schwinge1-1/+1
Fix-up for recent commit 2505a8b41d3b74a545755a278f3750a29c1340b6 "OpenMP: Minor '!$omp allocators' cleanup", which caused: {+FAIL: gfortran.dg/gomp/allocate-5.f90 -O (internal compiler error: tree check: expected class 'type', have 'declaration' (function_decl) in gfc_omp_call_is_alloc, at fortran/trans-openmp.cc:8386)+} [-PASS:-]{+FAIL:+} gfortran.dg/gomp/allocate-5.f90 -O (test for excess errors) ..., and similarly in 'libgomp.fortran/allocators-1.f90', 'libgomp.fortran/allocators-2.f90', 'libgomp.fortran/allocators-3.f90', 'libgomp.fortran/allocators-4.f90', 'libgomp.fortran/allocators-5.f90'. gcc/fortran/ * trans-openmp.cc (gfc_omp_call_is_alloc): Resolve ICE.
2023-12-11analyzer: fix uninitialized bitmap [PR112955]David Malcolm1-0/+1
In r14-5566-g841008d3966c0f I added a new ctor for feasibility_state, but failed to call bitmap_clear on m_snodes_visited. Fixed thusly. gcc/analyzer/ChangeLog: PR analyzer/112955 * engine.cc (feasibility_state::feasibility_state): Initialize m_snodes_visited. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-12-11Treat "p" in asms as addressing VOIDmodeRichard Sandiford3-8/+15
check_asm_operands was inconsistent about how it handled "p" after RA compared to before RA. Before RA it tested the address with a void (unknown) memory mode: case CT_ADDRESS: /* Every address operand can be reloaded to fit. */ result = result || address_operand (op, VOIDmode); break; After RA it deferred to constrain_operands, which used the mode of the operand: if ((GET_MODE (op) == VOIDmode || SCALAR_INT_MODE_P (GET_MODE (op))) && (strict <= 0 || (strict_memory_address_p (recog_data.operand_mode[opno], op)))) win = true; Using the mode of the operand is necessary for special predicates, where it is used to give the memory mode. But for asms, the operand mode is simply the mode of the address itself (so DImode on 64-bit targets), which doesn't say anything about the addressed memory. This patch uses VOIDmode for asms but continues to use the operand mode for .md insns. It's needed to avoid a regression in the testcase with the late-combine pass. Fixing this made me realise that recog_level2 was doing duplicate work for asms after RA. gcc/ * recog.cc (constrain_operands): Pass VOIDmode to strict_memory_address_p for 'p' constraints in asms. * rtl-ssa/changes.cc (recog_level2): Skip redundant constrain_operands for asms. gcc/testsuite/ * gcc.target/aarch64/prfm_imm_offset_2.c: New test.
2023-12-11testsuite: update manglingJason Merrill3-0/+26
Since r14-6064-gc3f281a0c1ca50 this test was checking for the wrong mangling, but it still passed on targets that support ABI compatibility aliases. Let's avoid generating those aliases when checking mangling. gcc/ChangeLog: * common.opt: Add comment. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-explicit-inst1.C: Specify ABI v18. * g++.dg/cpp2a/concepts-explicit-inst1a.C: New test.
2023-12-11-finline-stringops: avoid too-wide smallest_int_mode_for_size [PR112784]Alexandre Oliva2-11/+21
smallest_int_mode_for_size may abort when the requested mode is not available. Call int_mode_for_size instead, that signals the unsatisfiable request in a more graceful way. for gcc/ChangeLog PR middle-end/112784 * expr.cc (emit_block_move_via_loop): Call int_mode_for_size for maybe-too-wide sizes. (emit_block_cmp_via_loop): Likewise. for gcc/testsuite/ChangeLog PR middle-end/112784 * gcc.target/i386/avx512cd-inline-stringops-pr112784.c: New.
2023-12-11-finline-stringops: check base blksize for memset [PR112778]Alexandre Oliva2-9/+58
The recently-added logic for -finline-stringops=memset introduced an assumption that doesn't necessarily hold, namely, that can_store_by_pieces of a larger size implies can_store_by_pieces by smaller sizes. Checks for all sizes the by-multiple-pieces machinery might use before committing to an expansion pattern. for gcc/ChangeLog PR target/112778 * builtins.cc (can_store_by_multiple_pieces): New. (try_store_by_multiple_pieces): Call it. for gcc/testsuite/ChangeLog PR target/112778 * gcc.dg/inline-mem-cmp-pr112778.c: New.
2023-12-11-finline-stringops: don't assume ptr_mode ptr in memset [PR112804]Alexandre Oliva2-1/+8
On aarch64 -milp32, and presumably on other such targets, ptr can be in a different mode than ptr_mode in the testcase. Cope with it. for gcc/ChangeLog PR target/112804 * builtins.cc (try_store_by_multiple_pieces): Use ptr's mode for the increment. for gcc/testsuite/ChangeLog PR target/112804 * gcc.target/aarch64/inline-mem-set-pr112804.c: New.
2023-12-11multiflags: fix doc warningAlexandre Oliva1-1/+1
Comply with dubious doc warning that after an @xref there must be a comma or a period, not a close parentheses. for gcc/ChangeLog * doc/invoke.texi (multiflags): Add period after @xref to silence warning.
2023-12-11strub: disable on rl78Alexandre Oliva1-0/+5
rl78 allocation of virtual registers to physical registers doesn't operate on asm statements, and strub uses asm statements in the runtime and in the generated code, to the point that the runtime won't build. Force strub disabled on that target. for gcc/ChangeLog * config/rl78/rl78.cc (TARGET_HAVE_STRUB_SUPPORT_FOR): Disable.
2023-12-11strub: add note on attribute accessAlexandre Oliva1-1/+10
Document why attribute access doesn't need the same treatment as fn spec, and check that the assumption behind it holds. for gcc/ChangeLog * ipa-strub.cc (pass_ipa_strub::execute): Check that we don't add indirection to pointer parameters, and document attribute access non-interactions.
2023-12-11libgfortran: Replace mutex with rwlockLipeng Zhu10-58/+386
This patch try to introduce the rwlock and split the read/write to unit_root tree and unit_cache with rwlock instead of the mutex to increase CPU efficiency. In the get_gfc_unit function, the percentage to step into the insert_unit function is around 30%, in most instances, we can get the unit in the phase of reading the unit_cache or unit_root tree. So split the read/write phase by rwlock would be an approach to make it more parallel. BTW, the IPC metrics can gain around 9x in our test server with 220 cores. The benchmark we used is https://github.com/rwesson/NEAT libgcc/ChangeLog: * gthr-posix.h (__GTHREAD_RWLOCK_INIT): New macro. (__gthrw): New function. (__gthread_rwlock_rdlock): New function. (__gthread_rwlock_tryrdlock): New function. (__gthread_rwlock_wrlock): New function. (__gthread_rwlock_trywrlock): New function. (__gthread_rwlock_unlock): New function. libgfortran/ChangeLog: * io/async.c (DEBUG_LINE): New macro. * io/async.h (RWLOCK_DEBUG_ADD): New macro. (CHECK_RDLOCK): New macro. (CHECK_WRLOCK): New macro. (TAIL_RWLOCK_DEBUG_QUEUE): New macro. (IN_RWLOCK_DEBUG_QUEUE): New macro. (RDLOCK): New macro. (WRLOCK): New macro. (RWUNLOCK): New macro. (RD_TO_WRLOCK): New macro. (INTERN_RDLOCK): New macro. (INTERN_WRLOCK): New macro. (INTERN_RWUNLOCK): New macro. * io/io.h (struct gfc_unit): Change UNIT_LOCK to UNIT_RWLOCK in a comment. (unit_lock): Remove including associated internal_proto. (unit_rwlock): New declarations including associated internal_proto. (dec_waiting_unlocked): Use WRLOCK and RWUNLOCK on unit_rwlock instead of __gthread_mutex_lock and __gthread_mutex_unlock on unit_lock. * io/transfer.c (st_read_done_worker): Use WRLOCK and RWUNLOCK on unit_rwlock instead of LOCK and UNLOCK on unit_lock. (st_write_done_worker): Likewise. * io/unit.c: Change UNIT_LOCK to UNIT_RWLOCK in 'IO locking rules' comment. Use unit_rwlock variable instead of unit_lock variable. (get_gfc_unit_from_unit_root): New function. (get_gfc_unit): Use RDLOCK, WRLOCK and RWUNLOCK on unit_rwlock instead of LOCK and UNLOCK on unit_lock. (close_unit_1): Use WRLOCK and RWUNLOCK on unit_rwlock instead of LOCK and UNLOCK on unit_lock. (close_units): Likewise. (newunit_alloc): Use RWUNLOCK on unit_rwlock instead of UNLOCK on unit_lock. * io/unix.c (find_file): Use RDLOCK and RWUNLOCK on unit_rwlock instead of LOCK and UNLOCK on unit_lock. (flush_all_units): Use WRLOCK and RWUNLOCK on unit_rwlock instead of LOCK and UNLOCK on unit_lock.
2023-12-11PR rtl-optimization/112380: Defend against CLOBBERs in combine.ccRoger Sayle2-3/+39
This patch addresses PR rtl-optimization/112380, an ICE-on-valid regression where a (clobber (const_int 0)) encounters a sanity checking gcc_assert (at line 7554) in simplify-rtx.cc. These CLOBBERs are used internally by GCC's combine pass much like error_mark_node is used by various language front-ends. The solutions are either to handle/accept these CLOBBERs through-out (or in more places in) the middle-end's RTL optimizers, including functions in simplify-rtx.cc that are used by passes other than combine, and/or attempt to prevent these CLOBBERs escaping from try_combine into the RTX/RTL stream. The benefit of the second approach is that it actually allows for better optimization: when try_combine fails to simplify an expression instead of substituting a CLOBBER to avoid the instruction pattern being recognized, noticing the CLOBBER often allows combine to attempt alternate simplifications/transformations looking for those that can be recognized. This first alternative is the minimal fix to address the CLOBBER encountered in the bugzilla PR. 2023-12-11 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog PR rtl-optimization/112380 * combine.cc (expand_field_assignment): Check if gen_lowpart returned a CLOBBER, and avoid calling gen_simplify_binary with it if so. gcc/testsuite/ChangeLog PR rtl-optimization/112380 * gcc.dg/pr112380.c: New test case.
2023-12-11Testsuite: restrict test to nonpic targetsFrancois-Xavier Coudert1-0/+1
The test is currently failing on x86_64-apple-darwin. gcc/testsuite/ChangeLog: PR testsuite/112297 * gcc.target/i386/pr100936.c: Require nonpic target.
2023-12-11c++: add fixed testcase [PR63378]Patrick Palka1-0/+20
We accept this testcase since r12-4453-g79802c5dcc043a. PR c++/63378 gcc/testsuite/ChangeLog: * g++.dg/template/fnspec3.C: New test.
2023-12-11aarch64: Fix wrong code for bfloat when f16 is enabled [PR 111867]Andrew Pinski1-0/+4
The problem here is when f16 is enabled, movbf_aarch64 accepts `Ufc` as a constraint: [ w , Ufc ; fconsts , fp16 ] fmov\t%h0, %1 But that is for fmov values and in this case fmov represents f16 rather than bfloat16 values. This means we would get the wrong value in the register. Built and tested for aarch64-linux-gnu with no regressions. Also tested with `-march=armv9-a+sve2, gcc.dg/torture/bfloat16-basic.c and gcc.dg/torture/bfloat16-builtin.c no longer fail. gcc/ChangeLog: PR target/111867 * config/aarch64/aarch64.cc (aarch64_float_const_representable_p): For BFmode, only accept +0.0. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
generated by cgit v1.1 at 2024-08-23 07:52:50 +0000