5 files changed, 90 insertions, 0 deletions
diff --git a/libjava/ChangeLog b/libjava/ChangeLog
index 580b350..ab17f01 100644
--- a/libjava/ChangeLog
+++ b/libjava/ChangeLog
@@ -1,3 +1,10 @@
+2007-09-06  Roman Zippel  <zippel@linux-m68k.org>
+
+	* sysdep/m68k/locks.h: New file.
+	* configure.host: Set sysdeps_dir and libgcj_interpreter for m68k.
+	* configure.ac: Set SIGNAL_HANDLER for m68*-*-linux*.
+	* configure: Regenerate.
+
 2007-09-05  Samuel Thibault  <samuel.thibault@ens-lyon.org>
 
 	* configure.host(gnu*): Set use_libgcj_bc to yes.
diff --git a/libjava/configure b/libjava/configure
index f219205..77fcb02 100755
--- a/libjava/configure
+++ b/libjava/configure
@@ -27265,6 +27265,9 @@ case "${host}" in
  mips*-*-linux*)
     SIGNAL_HANDLER=include/mips-signal.h
     ;;
+ m68*-*-linux*)
+    SIGNAL_HANDLER=include/dwarf2-signal.h
+    ;;
  powerpc*-*-darwin*)
     SIGNAL_HANDLER=include/darwin-signal.h
     ;;
diff --git a/libjava/configure.ac b/libjava/configure.ac
index c99a882..6d06ec6 100644
--- a/libjava/configure.ac
+++ b/libjava/configure.ac
@@ -1543,6 +1543,9 @@ case "${host}" in
  mips*-*-linux*)
     SIGNAL_HANDLER=include/mips-signal.h
     ;;
+ m68*-*-linux*)
+    SIGNAL_HANDLER=include/dwarf2-signal.h
+    ;;
  powerpc*-*-darwin*)
     SIGNAL_HANDLER=include/darwin-signal.h
     ;;
diff --git a/libjava/configure.host b/libjava/configure.host
index bd81450..192272d 100644
--- a/libjava/configure.host
+++ b/libjava/configure.host
@@ -146,6 +146,10 @@ case "${host}" in
 	libgcj_interpreter=yes
 	enable_hash_synchronization_default=no
 	;;
+  m68k-*)
+	sysdeps_dir=m68k
+	libgcj_interpreter=yes
+	;;
   powerpc64*-*)
 	sysdeps_dir=powerpc
 	libgcj_interpreter=yes
@@ -202,6 +206,7 @@ case "${host}" in
   ia64-* | \
   x86_64*-linux* | \
   hppa*-linux* | \
+  m68k*-linux* | \
   sh-linux* | sh[34]*-linux*)
   	can_unwind_signal=yes
 	libgcj_ld_symbolic='-Wl,-Bsymbolic'
diff --git a/libjava/sysdep/m68k/locks.h b/libjava/sysdep/m68k/locks.h
new file mode 100644
index 0000000..d70757a
--- /dev/null
+++ b/libjava/sysdep/m68k/locks.h
@@ -0,0 +1,72 @@
+// locks.h - Thread synchronization primitives. m68k implementation.
+
+/* Copyright (C) 2006  Free Software Foundation
+
+   This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
+details.  */
+
+#ifndef __SYSDEP_LOCKS_H__
+#define __SYSDEP_LOCKS_H__
+
+/* Integer type big enough for object address.  */
+typedef size_t obj_addr_t __attribute__ ((aligned (4)));
+
+// Atomically replace *addr by new_val if it was initially equal to old.
+// Return true if the comparison succeeded.
+// Assumed to have acquire semantics, i.e. later memory operations
+// cannot execute before the compare_and_swap finishes.
+static inline bool
+compare_and_swap(volatile obj_addr_t *addr,
+		 obj_addr_t old, obj_addr_t new_val)
+{
+  char result;
+  __asm__ __volatile__("cas.l %2,%3,%0; seq %1"
+	      	: "+m" (*addr), "=d" (result), "+d" (old)
+		: "d" (new_val)
+		: "memory");
+  return (bool) result;
+}
+
+// Set *addr to new_val with release semantics, i.e. making sure
+// that prior loads and stores complete before this
+// assignment.
+// On m68k, the hardware shouldn't reorder reads and writes,
+// so we just have to convince gcc not to do it either.
+static inline void
+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
+{
+  __asm__ __volatile__(" " : : : "memory");
+  *(addr) = new_val;
+}
+
+// Compare_and_swap with release semantics instead of acquire semantics.
+// On many architecture, the operation makes both guarantees, so the
+// implementation can be the same.
+static inline bool
+compare_and_swap_release(volatile obj_addr_t *addr,
+			 obj_addr_t old,
+			 obj_addr_t new_val)
+{
+  return compare_and_swap(addr, old, new_val);
+}
+
+// Ensure that subsequent instructions do not execute on stale
+// data that was loaded from memory before the barrier.
+// On m68k, the hardware ensures that reads are properly ordered.
+static inline void
+read_barrier(void)
+{
+}
+
+// Ensure that prior stores to memory are completed with respect to other
+// processors.
+static inline void
+write_barrier(void)
+{
+  // m68k does not reorder writes. We just need to ensure that gcc also doesn't.
+  __asm__ __volatile__(" " : : : "memory");
+}
+#endif