diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 277 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/cobol/ChangeLog | 72 | ||||
| -rw-r--r-- | gcc/cp/ChangeLog | 21 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 303 |
5 files changed, 674 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ea65ca2..9f28a43 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,280 @@ +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + PR target/100165 + * config/aarch64/aarch64-protos.h (aarch64_output_fmov): New prototype. + (aarch64_simd_valid_and_imm_fmov): Likewise. + * config/aarch64/aarch64-simd.md (and<mode>3<vczle><vczbe>): Allow FMOV + codegen. + * config/aarch64/aarch64.cc (aarch64_simd_valid_and_imm_fmov): New. + (aarch64_output_fmov): Likewise. + * config/aarch64/constraints.md (Df): New constraint. + * config/aarch64/predicates.md (aarch64_reg_or_and_imm): Update + predicate to support FMOV codegen. + +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + PR target/100165 + * config/aarch64/aarch64.cc (aarch64_evpc_and): New. + (aarch64_expand_vec_perm_const_1): Call aarch64_evpc_and. + * optabs.cc (vec_perm_and_mask): New. + * optabs.h (vec_perm_and_mask): New prototype. + +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + * config/aarch64/aarch64.cc (aarch64_evpc_reencode): Zero initialize + newd. + +2025-05-16 Andrew Pinski <quic_apinski@quicinc.com> + + * tree-ssa-forwprop.cc (forward_propagate_into_comparison): Dump + when replacing statement. + +2025-05-16 Martin Jambor <mjambor@suse.cz> + Michal Jires <mjires@suse.cz> + + * cgraph.h (symtab_node): Make member function get_uid const. + * cgraphclones.cc (dump_callgraph_transformation): Dump m_uid of the + call graph nodes instead of order. + * cgraph.cc (cgraph_node::remove): Likewise. + * ipa-cp.cc (ipcp_lattice<valtype>::print): Likewise. + * ipa-sra.cc (ipa_sra_summarize_function): Likewise. + * symtab.cc (symtab_node::dump_base): Likewise. + +2025-05-16 Ville Voutilainen <ville.voutilainen@gmail.com> + + * doc/invoke.texi: Add to_underlying to -ffold-simple-inlines. + +2025-05-16 Andrew Pinski <quic_apinski@quicinc.com> + + PR target/118603 + * config/aarch64/driver-aarch64.cc (aarch64_cpu_data): Add cast to unsigned + to VARIANT of the define AARCH64_CORE. + +2025-05-16 Andrew Pinski <quic_apinski@quicinc.com> + + * config/aarch64/aarch64-protos.h (struct sve_vec_cost): Change gather_load_x32_cost + and gather_load_x64_cost fields to unsigned. + +2025-05-16 Andrew Pinski <quic_apinski@quicinc.com> + + * tree-ssa-forwprop.cc (optimize_memcpy_to_memset): Add a limit on the alias walk. + +2025-05-16 Andrew Pinski <quic_apinski@quicinc.com> + + * gimple-fold.cc (optimize_memcpy_to_memset): Move to + tree-ssa-forwprop.cc. + (gimple_fold_builtin_memory_op): Remove call to + optimize_memcpy_to_memset. + (fold_stmt_1): Likewise. + * tree-ssa-forwprop.cc (optimize_memcpy_to_memset): Move from + gimple-fold.cc. + (simplify_builtin_call): Try to optimize memcpy/memset. + (pass_forwprop::execute): Try to optimize memcpy like assignment + from a previous memset. + +2025-05-16 Richard Sandiford <richard.sandiford@arm.com> + + * config/arm/arm.cc (arm_gen_load_multiple_1): Simplify use of + end_sequence. + (arm_gen_store_multiple_1): Likewise. + * expr.cc (gen_move_insn): Likewise. + * gentarget-def.cc (main): Likewise. + +2025-05-16 Richard Sandiford <richard.sandiford@arm.com> + + * asan.cc (asan_emit_allocas_unpoison): Directly return the + result of end_sequence. + (hwasan_emit_untag_frame): Likewise. + * config/aarch64/aarch64-speculation.cc + (aarch64_speculation_clobber_sp): Likewise. + (aarch64_speculation_establish_tracker): Likewise. + * config/arm/arm.cc (arm_call_tls_get_addr): Likewise. + * config/avr/avr-passes.cc (avr_parallel_insn_from_insns): Likewise. + * config/sh/sh_treg_combine.cc + (sh_treg_combine::make_not_reg_insn): Likewise. + * tree-outof-ssa.cc (emit_partition_copy): Likewise. + +2025-05-16 Richard Sandiford <richard.sandiford@arm.com> + + * asan.cc (asan_clear_shadow): Use the return value of end_sequence, + rather than calling get_insns separately. + (asan_emit_stack_protection, asan_emit_allocas_unpoison): Likewise. + (hwasan_frame_base, hwasan_emit_untag_frame): Likewise. + * auto-inc-dec.cc (attempt_change): Likewise. + * avoid-store-forwarding.cc (process_store_forwarding): Likewise. + * bb-reorder.cc (fix_crossing_unconditional_branches): Likewise. + * builtins.cc (expand_builtin_apply_args): Likewise. + (expand_builtin_return, expand_builtin_mathfn_ternary): Likewise. + (expand_builtin_mathfn_3, expand_builtin_int_roundingfn): Likewise. + (expand_builtin_int_roundingfn_2, expand_builtin_saveregs): Likewise. + (inline_string_cmp): Likewise. + * calls.cc (expand_call): Likewise. + * cfgexpand.cc (expand_asm_stmt, pass_expand::execute): Likewise. + * cfgloopanal.cc (init_set_costs): Likewise. + * cfgrtl.cc (insert_insn_on_edge, prepend_insn_to_edge): Likewise. + (rtl_lv_add_condition_to_bb): Likewise. + * config/aarch64/aarch64-speculation.cc + (aarch64_speculation_clobber_sp): Likewise. + (aarch64_speculation_establish_tracker): Likewise. + (aarch64_do_track_speculation): Likewise. + * config/aarch64/aarch64.cc (aarch64_load_symref_appropriately) + (aarch64_expand_vector_init, aarch64_gen_ccmp_first): Likewise. + (aarch64_gen_ccmp_next, aarch64_mode_emit): Likewise. + (aarch64_md_asm_adjust): Likewise. + (aarch64_switch_pstate_sm_for_landing_pad): Likewise. + (aarch64_switch_pstate_sm_for_jump): Likewise. + (aarch64_switch_pstate_sm_for_call): Likewise. + * config/alpha/alpha.cc (alpha_legitimize_address_1): Likewise. + (alpha_emit_xfloating_libcall, alpha_gp_save_rtx): Likewise. + * config/arc/arc.cc (hwloop_optimize): Likewise. + * config/arm/aarch-common.cc (arm_md_asm_adjust): Likewise. + * config/arm/arm-builtins.cc: Likewise. + * config/arm/arm.cc (require_pic_register): Likewise. + (arm_call_tls_get_addr, arm_gen_load_multiple_1): Likewise. + (arm_gen_store_multiple_1, cmse_clear_registers): Likewise. + (cmse_nonsecure_call_inline_register_clear): Likewise. + (arm_attempt_dlstp_transform): Likewise. + * config/avr/avr-passes.cc (bbinfo_t::optimize_one_block): Likewise. + (avr_parallel_insn_from_insns): Likewise. + * config/avr/avr.cc (avr_prologue_setup_frame): Likewise. + (avr_expand_epilogue): Likewise. + * config/bfin/bfin.cc (hwloop_optimize): Likewise. + * config/c6x/c6x.cc (c6x_expand_compare): Likewise. + * config/cris/cris.cc (cris_split_movdx): Likewise. + * config/cris/cris.md: Likewise. + * config/csky/csky.cc (csky_call_tls_get_addr): Likewise. + * config/epiphany/resolve-sw-modes.cc + (pass_resolve_sw_modes::execute): Likewise. + * config/fr30/fr30.cc (fr30_move_double): Likewise. + * config/frv/frv.cc (frv_split_scc, frv_split_cond_move): Likewise. + (frv_split_minmax, frv_split_abs): Likewise. + * config/frv/frv.md: Likewise. + * config/gcn/gcn.cc (move_callee_saved_registers): Likewise. + (gcn_expand_prologue, gcn_restore_exec, gcn_md_reorg): Likewise. + * config/i386/i386-expand.cc + (ix86_expand_carry_flag_compare, ix86_expand_int_movcc): Likewise. + (ix86_vector_duplicate_value, expand_vec_perm_interleave2): Likewise. + (expand_vec_perm_vperm2f128_vblend): Likewise. + (expand_vec_perm_2perm_interleave): Likewise. + (expand_vec_perm_2perm_pblendv): Likewise. + (expand_vec_perm2_vperm2f128_vblend, ix86_gen_ccmp_first): Likewise. + (ix86_gen_ccmp_next): Likewise. + * config/i386/i386-features.cc + (scalar_chain::make_vector_copies): Likewise. + (scalar_chain::convert_reg, scalar_chain::convert_op): Likewise. + (timode_scalar_chain::convert_insn): Likewise. + * config/i386/i386.cc (ix86_init_pic_reg, ix86_va_start): Likewise. + (ix86_get_drap_rtx, legitimize_tls_address): Likewise. + (ix86_md_asm_adjust): Likewise. + * config/ia64/ia64.cc (ia64_expand_tls_address): Likewise. + (ia64_expand_compare, spill_restore_mem): Likewise. + (expand_vec_perm_interleave_2): Likewise. + * config/loongarch/loongarch.cc + (loongarch_call_tls_get_addr): Likewise. + * config/m32r/m32r.cc (gen_split_move_double): Likewise. + * config/m32r/m32r.md: Likewise. + * config/m68k/m68k.cc (m68k_call_tls_get_addr): Likewise. + (m68k_call_m68k_read_tp, m68k_sched_md_init_global): Likewise. + * config/m68k/m68k.md: Likewise. + * config/microblaze/microblaze.cc + (microblaze_call_tls_get_addr): Likewise. + * config/mips/mips.cc (mips_call_tls_get_addr): Likewise. + (mips_ls2_init_dfa_post_cycle_insn): Likewise. + (mips16_split_long_branches): Likewise. + * config/nvptx/nvptx.cc (nvptx_gen_shuffle): Likewise. + (nvptx_gen_shared_bcast, nvptx_propagate): Likewise. + (workaround_uninit_method_1, workaround_uninit_method_2): Likewise. + (workaround_uninit_method_3): Likewise. + * config/or1k/or1k.cc (or1k_init_pic_reg): Likewise. + * config/pa/pa.cc (legitimize_tls_address): Likewise. + * config/pru/pru.cc (pru_expand_fp_compare, pru_reorg_loop): Likewise. + * config/riscv/riscv-shorten-memrefs.cc + (pass_shorten_memrefs::transform): Likewise. + * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Likewise. + * config/riscv/riscv.cc (riscv_call_tls_get_addr): Likewise. + (riscv_frm_emit_after_bb_end): Likewise. + * config/rl78/rl78.cc (rl78_emit_libcall): Likewise. + * config/rs6000/rs6000.cc (rs6000_debug_legitimize_address): Likewise. + * config/s390/s390.cc (legitimize_tls_address): Likewise. + (s390_two_part_insv, s390_load_got, s390_va_start): Likewise. + * config/sh/sh_treg_combine.cc + (sh_treg_combine::make_not_reg_insn): Likewise. + * config/sparc/sparc.cc (sparc_legitimize_tls_address): Likewise. + (sparc_output_mi_thunk, sparc_init_pic_reg): Likewise. + * config/stormy16/stormy16.cc (xstormy16_split_cbranch): Likewise. + * config/xtensa/xtensa.cc (xtensa_copy_incoming_a7): Likewise. + (xtensa_expand_block_set_libcall): Likewise. + (xtensa_expand_block_set_unrolled_loop): Likewise. + (xtensa_expand_block_set_small_loop, xtensa_call_tls_desc): Likewise. + * dse.cc (emit_inc_dec_insn_before, find_shift_sequence): Likewise. + (replace_read): Likewise. + * emit-rtl.cc (reorder_insns, gen_clobber, gen_use): Likewise. + * except.cc (dw2_build_landing_pads, sjlj_mark_call_sites): Likewise. + (sjlj_emit_function_enter, sjlj_emit_function_exit): Likewise. + (sjlj_emit_dispatch_table): Likewise. + * expmed.cc (expmed_mult_highpart_optab, expand_sdiv_pow2): Likewise. + * expr.cc (convert_mode_scalar, emit_move_multi_word): Likewise. + (gen_move_insn, expand_cond_expr_using_cmove): Likewise. + (expand_expr_divmod, expand_expr_real_2): Likewise. + (maybe_optimize_pow2p_mod_cmp, maybe_optimize_mod_cmp): Likewise. + * function.cc (emit_initial_value_sets): Likewise. + (instantiate_virtual_regs_in_insn, expand_function_end): Likewise. + (get_arg_pointer_save_area, make_split_prologue_seq): Likewise. + (make_prologue_seq, gen_call_used_regs_seq): Likewise. + (thread_prologue_and_epilogue_insns): Likewise. + (match_asm_constraints_1): Likewise. + * gcse.cc (prepare_copy_insn): Likewise. + * ifcvt.cc (noce_emit_store_flag, noce_emit_move_insn): Likewise. + (noce_emit_cmove): Likewise. + * init-regs.cc (initialize_uninitialized_regs): Likewise. + * internal-fn.cc (expand_POPCOUNT): Likewise. + * ira-emit.cc (emit_move_list): Likewise. + * ira.cc (ira): Likewise. + * loop-doloop.cc (doloop_modify): Likewise. + * loop-unroll.cc (compare_and_jump_seq): Likewise. + (unroll_loop_runtime_iterations, insert_base_initialization): Likewise. + (split_iv, insert_var_expansion_initialization): Likewise. + (combine_var_copies_in_loop_exit): Likewise. + * lower-subreg.cc (resolve_simple_move,resolve_shift_zext): Likewise. + * lra-constraints.cc (match_reload, check_and_process_move): Likewise. + (process_addr_reg, insert_move_for_subreg): Likewise. + (process_address_1, curr_insn_transform): Likewise. + (inherit_reload_reg, process_invariant_for_inheritance): Likewise. + (inherit_in_ebb, remove_inheritance_pseudos): Likewise. + * lra-remat.cc (do_remat): Likewise. + * mode-switching.cc (commit_mode_sets): Likewise. + (optimize_mode_switching): Likewise. + * optabs.cc (expand_binop, expand_twoval_binop_libfunc): Likewise. + (expand_clrsb_using_clz, expand_doubleword_clz_ctz_ffs): Likewise. + (expand_doubleword_popcount, expand_ctz, expand_ffs): Likewise. + (expand_absneg_bit, expand_unop, expand_copysign_bit): Likewise. + (prepare_float_lib_cmp, expand_float, expand_fix): Likewise. + (expand_fixed_convert, gen_cond_trap): Likewise. + (expand_atomic_fetch_op): Likewise. + * ree.cc (combine_reaching_defs): Likewise. + * reg-stack.cc (compensate_edge): Likewise. + * reload1.cc (emit_input_reload_insns): Likewise. + * sel-sched-ir.cc (setup_nop_and_exit_insns): Likewise. + * shrink-wrap.cc (emit_common_heads_for_components): Likewise. + (emit_common_tails_for_components): Likewise. + (insert_prologue_epilogue_for_components): Likewise. + * tree-outof-ssa.cc (emit_partition_copy): Likewise. + (insert_value_copy_on_edge): Likewise. + * tree-ssa-loop-ivopts.cc (computation_cost): Likewise. + +2025-05-16 Richard Sandiford <richard.sandiford@arm.com> + + * rtl.h (end_sequence): Return the sequence. + * emit-rtl.cc (end_sequence): Likewise. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec-opt.md (*<optab>_vx_<mode>): Add new + pattern to convert vec_duplicate + vsub.vv to vsub.vx. + * config/riscv/riscv.cc (riscv_rtx_costs): Add minus as plus op. + * config/riscv/vector-iterators.md: Add minus to iterator + any_int_binop_no_shift_vx. + 2025-05-15 Andrew MacLeod <amacleod@redhat.com> PR tree-optimization/116546 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index e01bdfb..f5d7faa 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250516 +20250517 diff --git a/gcc/cobol/ChangeLog b/gcc/cobol/ChangeLog index 87aeaba..acfdfd5 100644 --- a/gcc/cobol/ChangeLog +++ b/gcc/cobol/ChangeLog @@ -1,3 +1,75 @@ +2025-05-16 Robert Dubner <rdubner@symas.com> + + * cobol1.cc (cobol_langhook_handle_option): Eliminate OPT_M. + * except.cc (cbl_enabled_exception_t::dump): Formatting. + (symbol_declaratives_add): Remove. + (declarative_runtime_match): Change to no-blob processing. + * exceptg.h (declarative_runtime_match): Change declaration. + (symbol_declaratives_add): Remove declaration. + * gcobc: Dialect handling. + * genapi.cc (parser_compile_ecs): Formatting; add SHOW_IF_PARSE. + (parser_compile_dcls): Likewise. + (parser_statement_begin): Avoid unnecessary store_location_stuff() call. + (gg_get_depending_on_value): Streamline get_depending_on_value_from_odo(). + (depending_on_value): Likewise. + (parser_display_field): Formatting. + (parser_display): Handle case ENV_NAME_e. + (parser_file_open): Avoid unnecessary store_location_stuff. + (parser_file_close): Likewise. + (parser_file_read): Likewise. + (parser_file_write): Likewise. + (parser_file_delete): Likewise. + (parser_file_rewrite): Likewise. + (parser_file_start): Likewise. + (parser_intrinsic_subst): Streamline get_depending_on_value_from_odo(). + (parser_intrinsic_call_1): Likewise. + (parser_lsearch_start): Likewise. + (parser_bsearch_start): Likewise. + (parser_sort): Likewise. + (store_location_stuff): Avoid unnecessary assignments. + (parser_pop_exception): Formatting. + * genmath.cc (parser_add): Avoid var_decl_default_compute_error assignment + when doing fast_add(). + (parser_subtract): Likewise. + * genutil.cc (REFER): Macro for analyzing code generation. + (get_integer_value): Use data_decl_node for integer value from FldLiteralN. + (get_data_offset): Streamline exception code processing. + (get_and_check_refstart_and_reflen): Likewise. + (get_depending_on_value_from_odo): Likewise. + (get_depending_on_value): Likewise. + (refer_is_clean): Formatting. + (refer_refmod_length): Streamline exception code processing. + (refer_fill_depends): Likewise. + (refer_offset): Likewise. + (refer_size_dest): Likewise. + (refer_size_source): Likewise. + * genutil.h (get_depending_on_value_from_odo): Likewise. + * lang-specs.h: Options definition. + * lang.opt: -M as in c.opt. + * lexio.h: Formatting. + * parse.y: Expand -dialect suggestions; SECTION SEGMENT messages. + * parse_ante.h (declarative_runtime_match): Dialect handling. + (labels_dump): Likewise. + (class current_tokens_t): Likewise. + (class prog_descr_t): Make program_index size_t to prevent padding bytes. + * scan.l: POP_FILE directive. + * scan_ante.h (class enter_leave_t): Better handle line number when + processing COPY statements. + * symbols.cc (symbol_elem_cmp): Eliminate SymFunction. + (symbols_dump): Likewise. + (symbol_label_section_exists): Likewise. + * symbols.h (NAME_MAX): Eliminate. (Was part of SymFunction). + (dialect_is): Improve dialect handling. + (dialect_gcc): Likewise. + (dialect_ibm): Likewise. + (dialect_gnu): Likewise. + (enum symbol_type_t): Eliminate SymFunction. + * util.cc (symbol_type_str): Likewise. + (class unique_stack): Option -M handling. + (cobol_set_pp_option): Likewise. + (parse_file): Likewise. + * util.h (cobol_set_pp_option): Likewise. + 2025-05-10 Robert Dubner <rdubner@symas.com> PR cobol/119337 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index b102f17..174a36f 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,24 @@ +2025-05-16 Ville Voutilainen <ville.voutilainen@gmail.com> + + * cp-gimplify.cc (cp_fold): Do the conversion unconditionally, even for same-type cases. + +2025-05-16 Iain Sandoe <iain@sandoe.co.uk> + + * typeck.cc (check_return_expr): Suppress conversions for NVRO + in coroutine ramp functions. + +2025-05-16 Iain Sandoe <iain@sandoe.co.uk> + + * decl.cc (poplevel): Set BLOCK_OUTER_CURLY_BRACE_P on the + body block for functions with no subblocks. + +2025-05-16 Nathaniel Shead <nathanieloshead@gmail.com> + + * module.cc (importer_interface): Adjust flags. + (get_importer_interface): Rename flags. + (trees_out::core_bools): Clean up special casing. + (trees_out::write_function_def): Rename flag. + 2025-05-15 Patrick Palka <ppalka@redhat.com> PR c++/120161 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9e65029..f13a988 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,306 @@ +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + PR target/100165 + * gcc.target/aarch64/fmov-3-be.c: New test. + * gcc.target/aarch64/fmov-3-le.c: New test. + * gcc.target/aarch64/fmov-4-be.c: New test. + * gcc.target/aarch64/fmov-4-le.c: New test. + * gcc.target/aarch64/fmov-5-be.c: New test. + * gcc.target/aarch64/fmov-5-le.c: New test. + +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + PR target/100165 + * gcc.target/aarch64/fmov-1-be.c: New test. + * gcc.target/aarch64/fmov-1-le.c: New test. + * gcc.target/aarch64/fmov-2-be.c: New test. + * gcc.target/aarch64/fmov-2-le.c: New test. + +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + PR target/100165 + * gcc.target/aarch64/and-be.c: New test. + * gcc.target/aarch64/and-le.c: New test. + +2025-05-16 Robert Dubner <rdubner@symas.com> + + * cobol.dg/group1/declarative_1.cob: Handle modified exception handling. + +2025-05-16 Andrew Pinski <quic_apinski@quicinc.com> + + * gcc.dg/pr78408-1.c: Update scan to forwprop1 only. + +2025-05-16 Jason Merrill <jason@redhat.com> + + * g++.dg/coroutines/pr94760-mismatched-traits-and-promise-prev.C: + Remove { target c++17 }. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Take + test name for the vx combine test data. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c: Leverage + the test name to identify the test data. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add test cases + for vsub vx combine case 1 with GR2VR cost 2. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Add test cases + for vsub vx combine case 1 with GR2VR cost 1. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add test cases + for vsub vx combine case 1 with GR2VR cost 0. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Add test cases + for vsub vx combine with GR2VR cost 15. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Add test cases + for vsub vx combine with GR2VR cost 1. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Diito. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add vector sub + vx combine asm check. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test + data for vector sub vx combine. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c: New test. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add + type and op name to generate test function name. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Refine the + test helper macros to avoid conflict. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: ...here. + 2025-05-15 Jason Merrill <jason@redhat.com> * g++.dg/coroutines/co-await-syntax-09-convert.C: Add -fcoroutines. |